Chip and electronic device

Abstract

The invention provides a chip and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem of warping between film layers of the chip, and the chip comprises a cellular region and a terminal region surrounding the cellular region; the chip further comprises a substrate, a plurality of insulating layers located on one side of the substrate and a first-class nested structure located in the terminal area. Wherein the first type of nested structure comprises a first nested structure, the first nested structure comprises a first groove and a first protrusion, the first groove is formed in the substrate and faces one side of the insulating layer, the first protrusion is arranged on the insulating layer adjacent to the substrate and faces one side of the substrate, and the first groove is filled with the first protrusion.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor chips, and particularly to a chip and an electronic device. Background Art

[0002] In the manufacturing process of chips, there are various film layers involved, such as inter-layer dielectric (ILD), polysilicon, metal, insulating layer, polymer insulating layers (PID), etc. When different film layers are stacked on the same chip, the inherent properties of the materials will cause differences in the affinity between layers, resulting in warping problems between the film layers during the chip manufacturing process, and leading to poor reliability of the chips. Summary of the Invention

[0003] Embodiments of the present disclosure provide a chip and an electronic device, aiming to solve the warping problem between the film layers of the chip.

[0004] To achieve the above object, the embodiments of the present disclosure adopt the following technical solutions: On the one hand, a chip is provided. The chip includes: a cell region and a terminal region surrounding the cell region.

[0005] The chip further includes: a substrate, a multi-layer insulating layer on one side of the substrate, and a first type of nested structure in the terminal region.

[0006] Wherein, the first type of nested structure includes: a first nested structure, and the first nested structure includes: a first groove provided on the substrate and facing the insulating layer side, and a first protrusion provided on the insulating layer adjacent to the substrate and facing the substrate side, and the first protrusion fills the first groove.

[0007] In the chip provided by the above embodiments of the present disclosure, the multi-layer insulating layer provides electrical insulation, prevents current leakage between different circuit layers, and also plays a role in physical support and protection. Moreover, the multi-layer insulating layer can absorb the thermal stress generated due to temperature changes during the manufacturing and use of the chip, reduce the delamination risk caused by inter-layer shear force, and can improve the interface bonding strength; and the multi-layer insulating layer can also form multiple physical-chemical filtering barriers, which can intercept mobile ions (such as Na⁺) and environmental pollutants such as water vapor, and can prevent environmental pollutants from diffusing along the inter-layer interface to the cell region and affecting the function of the chip.

[0008] The first type of nested structure is disposed in the terminal region. The mechanical interlock structure formed by the first groove and the first protrusion of the first nested structure enables the first nested structure to serve as a breakpoint, effectively dispersing stress, that is, relieving the stress formed during wafer cutting. By absorbing energy through the geometric deformation of the groove-protrusion, it prevents stress from spreading to the cell region, reduces the stress concentration near the cutting, significantly reduces the risk of lattice dislocations and crack propagation, avoids generating new defects and weak points in the reliability assessment in the cell region. Moreover, the first nested structure can increase the contact area between the substrate and the insulating layer (the first protrusion fills the first groove), increasing the interfacial bonding strength between the substrate and the insulating layer, enhancing the adhesion between the substrate and the insulating layer, effectively solving the warping and delamination problems between the substrate and the insulating layer, avoiding problems such as discharge caused by delamination, and enhancing the reliability of the chip.

[0009] In addition, the physical barrier formed at the junction of the first protrusion and the first groove between the substrate and the insulating layer can intercept environmental pollutants such as mobile ions, water vapor, and foreign contaminants, improving the blocking efficiency, preventing these environmental pollutants from diffusing along the interlayer interface to the core region of the cell region, and thus improving the electrical reliability of the chip.

[0010] In some embodiments, the depth range of the first groove is from 0.02 μm to 5 μm.

[0011] In some embodiments, the first type of nested structure includes: a second nested structure.

[0012] The second nested structure includes: a second groove disposed on the first insulating layer and facing away from the substrate, and a second protrusion disposed on the second insulating layer and facing the substrate, and the second protrusion fills the second groove.

[0013] Wherein, the first insulating layer and the second insulating layer are adjacently arranged, and the second insulating layer is located on the side of the first insulating layer away from the substrate.

[0014] In some embodiments, in the orthographic projection onto the substrate, the first nested structure and the second nested structure overlap.

[0015] In some embodiments, along the first direction, the number of the first type of nested structures is multiple, and the multiple first type of nested structures are spaced apart. Wherein, the first direction surrounds the cell region.

[0016] In some embodiments, the orthographic projection of the first type of nested structure on the substrate includes at least one of a circle and a polygon.

[0017] In some embodiments, the first type of nested structure is arranged in a ring shape along the first direction.

[0018] In some embodiments, in the multi-layer insulating layer, the number of the second nested structures further away from the substrate is greater than or equal to the number of the second nested structures closer to the substrate.

[0019] In some embodiments, along the second direction, the number of the first type of nested structures is multiple, and the multiple first type of nested structures are arranged at intervals. Wherein, the second direction is the direction away from the cell region.

[0020] In some embodiments, the multi-layer insulating layer includes: an interlayer dielectric layer and a passivation layer located on the side of the interlayer dielectric layer away from the substrate.

[0021] In the terminal region, there is a first sub-region. In the positive projection onto the substrate, the first sub-region is located on the side of the first type of nested structure away from the cell region; in the first sub-region, the substrate, the interlayer dielectric layer, and the passivation layer are sequentially in contact.

[0022] The chip further includes: a through hole penetrating the interlayer dielectric layer, and a part of the passivation layer penetrates the through hole and is in contact with the substrate.

[0023] In some embodiments, the chip further includes: at least one conductive layer located on one side of the substrate and a second type of nested structure located in the cell region. The conductive layer includes a first conductive layer, and the first conductive layer is located on the side of the insulating layer away from the substrate.

[0024] The second type of nested structure includes: a third trench provided on the substrate and / or the insulating layer and facing away from the first conductive layer, and a third protrusion provided on the first conductive layer and facing the substrate side, and the third protrusion fills the third trench.

[0025] In some embodiments, along the third direction, the number of the second type of nested structures is multiple, and the multiple second type of nested structures are arranged at intervals. Wherein, the third direction is the direction extending along the edge of the first conductive layer.

[0026] In some embodiments, the second nested structure is arranged in a ring shape along the third direction.

[0027] In some embodiments, along the fourth direction, the number of the second type of nested structures is multiple, and the multiple second type of nested structures are arranged at intervals. Wherein, the fourth direction is the direction away from the terminal region.

[0028] In some embodiments, the positive projection of the second type of nested structure on the substrate includes: at least one of a circle and a polygon.

[0029] In some embodiments, it includes: a semiconductor device located in the cell region. The semiconductor device includes: any one of a metal-oxide-semiconductor field effect transistor, a Schottky barrier diode, a junction field effect transistor, an insulated gate bipolar transistor, and a high electron mobility transistor.

[0030] On the other hand, an electronic device is provided. The electronic device includes: a chip.

[0031] It can be understood that for the electronic device provided in the above embodiments of the present disclosure, the beneficial effects that can be achieved can refer to the beneficial effects of the chip in the foregoing text, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for some embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual sizes of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present disclosure.

[0033] Figure 1 It is a schematic structural diagram of a chip according to some embodiments; Figure 2 It is a schematic structural diagram of a partially enlarged chip according to some embodiments; Figure 3 It is a schematic structural diagram of a partially enlarged chip according to some other embodiments; Figure 4 It is a schematic structural diagram of a partially enlarged chip according to some other embodiments; Figure 5 It is a schematic structural diagram of a chip according to some other embodiments; Figure 6 It is a schematic structural diagram of a chip according to some other embodiments; Figure 7 It is a schematic structural diagram of a partially enlarged chip according to some other embodiments; Figure 8 It is a schematic structural diagram of a partially enlarged chip according to some other embodiments; Figure 9 It is a schematic structural diagram of a partially enlarged chip according to some other embodiments; Figure 10 It is a schematic structural diagram of a partially enlarged chip according to some other embodiments; Figure 11 It is a schematic structural diagram of a chip according to some other embodiments; Figure 12 It is a schematic structural diagram of a chip according to some other embodiments; Figure 13 It is a schematic structural diagram of a chip according to some other embodiments; Figure 14 It is a schematic structural diagram of the chip of Embodiment 1. Detailed Implementation Modes

[0034] The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided by the present disclosure fall within the protection scope of the present disclosure.

[0035] In the description of the present disclosure, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present disclosure.

[0036] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner. [[ID=ll]]

[0037] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.

[0038] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0039] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0040] As used herein, "about," "substantially," or "approximately" includes the stated value and an average within an acceptable deviation range of a particular value, where the acceptable deviation range is determined by one of ordinary skill in the art in view of the measurement being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).

[0041] In the context of the present disclosure, the meanings of "on," "above," and "over" should be construed in the broadest manner such that "on" not only means "directly on something," but also includes "on something" with intervening features or layers therebetween, and "above" or "over" not only means "above" or "over" something, but also includes "above" or "over" something with no intervening features or layers therebetween (i.e., directly on something).

[0042] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Accordingly, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations resulting from, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0043] As used herein, the term "substrate" refers to a material upon which subsequent layers of material can be added. The substrate itself can be patterned. The material added to the substrate can be patterned or can remain unpatterned. Additionally, the substrate can include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0044] The following explains the technical terms in the embodiments of the present disclosure as follows: Semiconductor: A semiconductor is a material whose electrical conductivity at room temperature lies between that of a conductor and an insulator. Semiconductors include intrinsic semiconductors and extrinsic semiconductors. A pure semiconductor without impurities and defects has equal concentrations of electrons and holes inside, which is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an extrinsic semiconductor or non-intrinsic semiconductor. Among them, the impurities doped in the extrinsic semiconductor can provide a certain concentration of carriers (such as holes or electrons. Among them, an extrinsic semiconductor doped with impurities that provide electrons (such as pentavalent phosphorus) is also called an electron-type semiconductor or N (negative) type semiconductor, and an extrinsic semiconductor doped with impurities that provide holes (such as trivalent boron) is also called a hole-type semiconductor or P (positive) type semiconductor). When it can improve the electrical conductivity of the intrinsic semiconductor, generally, the greater the carrier concentration, the lower the resistivity of the semiconductor and the better its electrical conductivity. In the embodiments of the present disclosure, this type of extrinsic semiconductor is also called a conductive semiconductor. For example, for a conductive silicon carbide material, the doped impurities are nitrogen N, boron B, aluminum Al, etc. In addition, when the impurities doped in the extrinsic semiconductor can perform impurity compensation on the extrinsic semiconductor, the donor electrons are just enough to fill the acceptor energy level, but cannot provide electrons and holes to the conduction band and valence band, making the semiconductor material with a wider bandgap have a resistivity similar to that of an insulator. For example, in the embodiments of the present disclosure, doping a transition metal into a silicon carbide material realizes impurity compensation for the silicon carbide material, thereby increasing the resistivity of the silicon carbide material. This type of extrinsic semiconductor is also called a semi-insulating semiconductor or semi-insulator, or has semi-insulator characteristics.

[0045] In addition, in the present disclosure, orientation terms such as "upper" and "lower" are defined relative to the orientation of the components shown in the drawings. It should be understood that these directional terms are relative concepts, which are used for relative description and clarification, and they can change accordingly with the change of the orientation of the components placed in the drawings.

[0046] It should be noted that in the present disclosure, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present disclosure should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, using words such as "exemplary" or "for example" aims to present relevant concepts in a specific way.

[0047] It should be noted that, for example, 1 / 2 appearing in the drawings of the present disclosure means that both component 1 and component 2 can refer to this component. For example, Figure 2 21 / 211 in the figure means that both the first type of nested structure 21 and the first nested structure 211 can be represented by this component. Other similar reference numerals appearing in the drawings also follow the above description.

[0048] The technical solutions of the present disclosure can be applied to electronic devices, which can be different types of user devices or terminal devices such as computers, mobile phones, tablet computers, wearable devices, and in-vehicle devices; the electronic devices can also be network devices such as base stations. The electronic device can also be a device such as a power amplifier in the above-mentioned electronic devices. The specific form of the above-mentioned electronic device is not particularly limited in the embodiments of the present disclosure.

[0049] An embodiment of the present disclosure provides an electronic device, including: a chip 100.

[0050] An electronic device is a miniaturized electronic circuit, containing multiple components such as transistors, diodes, resistors, and capacitors, integrated on a chip 100.

[0051] In the manufacturing process of the chip 100, there are various film layers, such as interlayer insulating layers, polysilicon, metal, insulating layers, polymer insulating layers, etc. When different film layers are stacked on the same chip 100, the inherent properties of the materials will cause differences in interlayer affinity, resulting in warping problems during the process. More importantly, when the chip 100 is undergoing reliability assessment, the thermal stress caused by high temperature and high pressure will exacerbate this phenomenon, resulting in voids, splitting, etc. When the chip 100 is cut into bare dies (i.e., bare dice), the stress generated by the cutting will extend towards the center of the chip 100, which will induce new defects and weak points in the reliability assessment, resulting in a reduction in the reliability of the chip 100.

[0052] Based on this, an embodiment of the present disclosure provides a chip 100. As Figure 1 shown, the chip 100 includes: a cell region 1a and a terminal region 2a surrounding the cell region 1a.

[0053] The terminal region 2a of the chip 100 is usually located near the scribe line and plays a voltage withstand role when the device is turned off. The cell region 1a of the chip 100 is the region where the core functions of the chip 100 are located.

[0054] Exemplarily, the cell region 1a can be an array of semiconductor devices 10.

[0055] As Figure 2 shown, the chip 100 further includes: a substrate 3, a multi-layer insulating layer 4 on one side of the substrate 3, and a first type of nested structure 21 in the terminal region 2a.

[0056] The substrate 3, as the bottom carrier of the chip 100, can provide mechanical support and a thermal stability reference for the film layers on one side of the substrate 3, such as the multi-layer insulating layer 4.

[0057] Exemplarily, the substrate 3 can be either a substrate or a substrate provided with an epitaxial layer.

[0058] Exemplarily, the materials of each layer of the multi-layer insulating layer 4 can be the same or different.

[0059] Exemplarily, the material of the insulating layer 4 can be any one of SiO, SiN, Boron Phospho-Silicate Glass (BPSG), Phospho-Silicate Glass (PSG), SiON, and polymer.

[0060] The multi-layer insulating layer 4 provides electrical insulation to prevent current leakage between different circuit layers, and also plays a role in physical support and protection; moreover, during the manufacturing and use of the chip 100, due to temperature changes, thermal stress will be generated inside the chip 100. If this thermal stress cannot be effectively released and absorbed, it may lead to failure phenomena such as cracking or delamination of the chip 100. The setting of the multi-layer insulating layer 4 can absorb these thermal stresses and reduce the delamination risk of the chip 100; moreover, the multi-layer insulating layer 4 can also form a multiple physical-chemical filtering barrier, which can intercept environmental pollutants such as mobile ions and water vapor, and prevent environmental pollutants from diffusing along the interlayer interface to the cell region 1a, affecting the function of the chip 100.

[0061] Exemplarily, the multi-layer insulating layer 4 can be an interlayer insulating layer, a gate insulating layer, a field oxide insulating layer, an insulating layer, a polymer insulating layer, a surface passivation layer (SiO2 or polymer material), etc.

[0062] Exemplarily, when the semiconductor device 10 arranged in an array in the cell region 1a of the chip 100 is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), the insulating layer 4 closer to the substrate 3 in the multi-layer insulating layer 4 can be a field oxide insulating layer.

[0063] As Figures 2 to 4 shown, among them, the first type of nested structure 21 includes: a first nested structure 211. The first nested structure 211 includes: a first trench 211G provided on the substrate 3 and facing the insulating layer 4 side, and a first protrusion 211T provided on the insulating layer 4 adjacent to the substrate 3 and facing the substrate 3 side. The first protrusion 211T fills the first trench 211G.

[0064] That is to say, in the first type of nested structure 21, the mechanical interlocking structure formed by the first groove 211G and the first protrusion 211T enables the first nested structure 211 to serve as a breakpoint, which can effectively disperse stress, that is, relieve the stress formed during wafer cutting. The energy is absorbed through the geometric deformation of the groove-protrusion, preventing the stress from spreading to the cell region 1a. The stress concentration near the cutting can be reduced, significantly reducing the risk of lattice dislocations and crack propagation, and avoiding the generation of new defects and weak points in the reliability assessment in the cell region 1a. Moreover, the first nested structure 211 can increase the contact area between the substrate 3 and the insulating layer 4 (the first protrusion 211T fills the first groove 211G), increasing the interfacial bonding strength between the substrate 3 and the insulating layer 4, enhancing the adhesion between the substrate 3 and the insulating layer 4, effectively solving the warping and delamination problems between the substrate 3 and the insulating layer 4, avoiding problems such as discharge caused by delamination, and enhancing the reliability of the chip 100.

[0065] In addition, the physical barrier formed at the junction of the substrate 3 and the insulating layer 4 at the first protrusion 211T and the first groove 211G can intercept environmental pollutants such as mobile ions, water vapor, and foreign contaminants, improve the blocking efficiency, prevent these environmental pollutants from diffusing along the interlayer interface to the core region of the cell region 1a, and thus improve the electrical reliability of the chip 100.

[0066] In some embodiments, the depth H of the first groove 211G ranges from 0.02 μm to 5 μm.

[0067] Exemplarily, the depth H of the first groove 211G can be 0.02 μm, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc., and there is no limitation here.

[0068] It can be understood that setting the depth H of the first groove 211G within the range of 0.02 μm to 5 μm can not only better reduce the stress concentration during cutting, prevent the interfacial crack from extending to the cell region 1a, and inhibit the interfacial delamination between the substrate 3 and the insulating layer 4, but also cooperate with the thickness of the substrate 3 to improve the process feasibility of the first groove 211G.

[0069] In some embodiments, as Figures 2 to 4 shown, the first type of nested structure 21 includes: a second nested structure 212.

[0070] The second nested structure 212 includes: a second groove 212G provided on the first insulating layer 41 and facing away from the substrate 3, and a second protrusion 212T provided on the second insulating layer 42 and facing the substrate 3, and the second protrusion 212T fills the second groove 212G.

[0071] Wherein, the first insulating layer 41 and the second insulating layer 42 are arranged adjacent to each other, and the second insulating layer 42 is located on the side of the first insulating layer 41 away from the substrate 3.

[0072] That is to say, the second nested structure 212 is disposed between adjacent insulating layers 4 of the multi-layer insulating layer 4. A physical interlock is formed through the nested structure of the second groove 212G and the second protrusion 212T. Compared with the parallel planar contact between the two, such a setting can make the adjacent insulating layers 4 use the second nested structure 212 as an anchoring point, increase the bonding strength between the adjacent insulating layers 4, improve the adhesion between the adjacent insulating layers 4, and further reduce the peeling risk between the insulating layers 4, thereby increasing the reliability of the semiconductor device 10. In addition, the second nested structure 212 can also serve as a contamination capture point for environmental contaminants to improve the cleanliness of the cell region 1a and the electrical performance of the semiconductor device 10.

[0073] In some embodiments, such as Figure 3 and Figure 4 shown, in the positive projection onto the substrate 3, the first nested structure 211 and the second nested structure 212 overlap.

[0074] It can be understood that the overlapping portion of the first nested structure 211 and the second nested structure 212 can form a composite stress absorption layer, and the overlapping portion can be complementary to improve the bonding strength between the substrate 3 and the insulating layer 4 and between the multi-layer insulating layers 4, and further inhibit delamination at the film interface; in addition, the overlapping portion of the first nested structure 211 and the second nested structure 212 can form multiple physical barrier paths, which can further block the migration channels of environmental contaminants, intercept environmental contaminants such as mobile ions, water vapor, and foreign contamination, improve the blocking efficiency, and prevent these environmental contaminants from diffusing along the interlayer interface to the core region of the cell region 1a, thereby improving the electrical reliability of the chip 100.

[0075] In some embodiments, such as Figure 5 shown, along the first direction X, the number of the first type of nested structures 21 is multiple, and the multiple first type of nested structures 21 are spaced apart. Wherein, the first direction X surrounds the cell region 1a.

[0076] Exemplarily, the positive projection of the first type of nested structure 21 on the substrate 3 includes at least one of a circle and a polygon, such as a rectangle, a hexagon, etc.

[0077] That is to say, the first type of nested structure 21 can be arranged at intervals in an island shape around the cell region 1a. At the same time, setting the number of the first type of nested structure 21 to be multiple can make there be multiple first nested structures 211 between the substrate 3 and the insulating layer 4. In this way, multiple first nested structures 211 can cooperate with each other to further relieve the stress generated during wafer cutting, prevent the stress from spreading to the cell region 1a, further improve the delamination problem between the substrate 3 and the insulating layer 4, and further prevent impurities from diffusing along the interface between the substrate 3 and the insulating layer 4 to the semiconductor device 10 in the cell region 1a. It can also make there be multiple second nested structures 212 between the multiple insulating layers 4. Multiple second nested structures 212 can cooperate with each other to further strengthen the bonding strength between the first insulating layer 41 and the second insulating layer 42 and reduce the delamination risk between the multiple insulating layers 4.

[0078] In some embodiments, as Figure 6 shown, the first type of nested structure 21 is arranged in a ring shape along the first direction X. The first direction X surrounds the cell region 1a.

[0079] It can be understood that the above-mentioned ring-shaped arrangement can make the terminal region 2a of the chip 100 include the first type of nested structure 21 around the cell region 1a, further improve the pushing and pulling force between the film layers, enhance the adhesion between the film layers, and reduce the delamination risk between the film layers. It can also further prevent environmental pollutants from entering the semiconductor device 10 in the cell region 1a.

[0080] In some embodiments, the number of the second nested structures 212 in the insulating layer 4 that is farther from the substrate 3 in the multiple insulating layers 4 is greater than or equal to the number of the second nested structures 212 in the insulating layer 4 that is closer to the substrate 3.

[0081] It can be understood that the second nested structure 212 is farther from the substrate 3 than the first nested structure 211. That is to say, the second nested structure 212 is closer to the surface of the chip 100. The first type of nested structure 21 serves as a physical barrier and an anchoring point between the film layers. When the number of the second nested structures 212 closer to the surface of the chip 100 is large, there are more physical barriers and anchoring points closer to the surface of the chip 100, so as to enhance the adhesion between the surface of the chip 100 and the inside of the chip 100, further reduce the delamination risk between the film layers. It can also further prevent environmental pollutants from entering the semiconductor device 10 in the cell region 1a to protect the cleanliness inside the semiconductor device 10 and minimize the drift of electrical properties of the semiconductor device 10 such as the threshold voltage (V th ), flat-band voltage (V f ), mobility (μ), etc.

[0082] In some embodiments, as Figure 5As shown, along the second direction Y, the number of the first type of nested structures 21 is multiple, and the multiple first type of nested structures 21 are arranged at intervals. Among them, the second direction Y is the direction away from the cell region 1a.

[0083] Exemplarily, when the first type of nested structure 21 is arranged in a ring along the first direction X, in the terminal region 2a, there are multiple first type of nested structures 21 arranged in a ring around the cell region 1a, and a certain distance is separated between each first type of nested structure 21 arranged in a ring, that is, they are arranged in a progressive manner through the second direction Y.

[0084] It can be understood that multiple first type of nested structures 21 are arranged in the terminal region 2a, so that the entire terminal region 2a has a physical barrier formed by multiple first type of nested structures 21, which can not only relieve the stress generated during the cutting of the wafer, avoid the spread of stress to the cell region 1a, further improve the adhesion between each film layer, and reduce the peeling risk between each film layer; but also further prevent environmental pollutants from entering the semiconductor device 10 in the cell region 1a.

[0085] In some embodiments, as Figure 4 shown, the multi-layer insulating layer 4 includes: an interlayer dielectric layer 42L and a passivation layer 43 located on the side of the interlayer dielectric layer 42L away from the substrate 3.

[0086] The terminal region 2a has a first sub-region 2A. In the orthographic projection onto the substrate 3, the first sub-region 2A is located on the side of the first type of nested structure 21 away from the cell region 1a. In the first sub-region 2A, the substrate 3, the interlayer dielectric layer 42L, and the passivation layer 43 are sequentially in contact.

[0087] The chip 100 further includes: a through hole K penetrating the interlayer dielectric layer 42L, and a part of the passivation layer 43 penetrates through the through hole K and is in contact with the substrate 3.

[0088] It can be understood that the passivation layer 43 is usually silicon nitride (SiN) or silicon dioxide (SiO2), which is used to protect the film layers near the substrate 3 from environmental pollutants. Through the through hole K, a part of the passivation layer 43 is directly in contact with the substrate 3, which can increase the adhesion force between the passivation layer 43 and the substrate 3, form a more reliable connection, protect other film layers located between the passivation layer 43 and the substrate 3 from environmental pollutants, and form the first barrier for foreign matters such as water vapor.

[0089] In some embodiments, as Figures 7 to 9 shown, the chip 100 further includes: at least one conductive layer 5 located on one side of the substrate 3 and a second type of nested structure 22 located in the cell region 1a. The conductive layer 5 includes a first conductive layer 51, and the first conductive layer 51 is located on the side of the insulating layer 4 away from the substrate 3.

[0090] The second type of nested structure 22 includes: a third trench 22G disposed on the substrate 3 and / or the insulating layer 4 and facing away from the first conductive layer 51, and a third protrusion 22T disposed on the first conductive layer 51 and facing the substrate 3, and the third protrusion 22T fills the third trench 22G.

[0091] Exemplarily, as Figure 7 and Figure 8 shown, the second type of nested structure 22 is a third trench 22G disposed on the substrate 3 and facing away from the first conductive layer 51, and a third protrusion 22T disposed on the first conductive layer 51 and facing the substrate 3, and the third protrusion 22T fills the third trench 22G.

[0092] Exemplarily, as Figure 9 and Figure 10 shown, the second type of nested structure 22 is a third trench 22G disposed on the insulating layer 4 and facing away from the first conductive layer 51, and a third protrusion 22T disposed on the first conductive layer 51 and facing the substrate 3, and the third protrusion 22T fills the third trench 22G.

[0093] Exemplarily, the positions of the third protrusion 22T and the third trench 22G may be located between the gate 7 (for example, a dual-color gate, including a metal gate 71 and a polysilicon gate 72, that is, both metal and polysilicon are used as gate materials) and the semiconductor device 10.

[0094] It can be understood that the conductive layer 5 can be used for electrical connection and signal transmission, and the second type of nested structure 22 is provided between the first conductive layer 51 and the substrate 3, so that the interconnectivity between the first conductive layer 51 and the substrate 3 is enhanced, and it can adapt to more complex circuit layouts; moreover, it can also enhance the structural stability of the chip 100 and improve its mechanical strength.

[0095] In some embodiments, as Figure 11 shown, along the third direction Z, the number of the second type of nested structures 22 is multiple, and the multiple second type of nested structures 22 are arranged at intervals. Wherein, the third direction Z is along the direction in which the edge of the first conductive layer 51 extends.

[0096] Exemplarily, when the semiconductor device 10 is a metal-oxide-semiconductor field effect transistor, as Figure 1 shown, the pad 6 in the cell region 1a can be a gate pad. At this time, the second type of nested structure 22 is arranged along the direction in which the edge of the first conductive layer 51 extends and also surrounds the gate pad in the cell region 1a.

[0097] The second type of nested structure 22 can be arranged at intervals in an island shape around the terminal area 2a. At the same time, setting the number of the second type of nested structure 22 to be multiple can make there be multiple second type of nested structures 22 between the first conductive layer 51 and the substrate 3. In this way, multiple second type of nested structures 22 can cooperate with each other, further enhancing the interconnection ability between the first conductive layer 51 and the substrate 3, and being able to adapt to a more complex circuit layout; moreover, it can also enhance the structural stability of the chip 100 and improve its mechanical strength.

[0098] In some embodiments, as Figure 12 shown, the second type of nested structure 22 is arranged in a ring shape along the third direction Z. The third direction Z is along the direction in which the edge of the first conductive layer 51 extends.

[0099] It can be understood that the above ring-shaped arrangement can make the cell area 1a of the chip 100 include the second type of nested structure 22 around the terminal area 2a, reduce the stress concentration in the cell area 1a, avoid the risk of local breakdown of the chip 100, and improve the breakdown voltage performance of the chip 100.

[0100] In some embodiments, as Figure 13 shown, along the fourth direction P, the number of the second type of nested structure 22 is multiple, and multiple second type of nested structures 22 are arranged at intervals. Among them, the fourth direction P is the direction away from the terminal area 2a.

[0101] Exemplarily, the orthographic projection of the second type of nested structure 22 on the substrate 3 includes at least one of a circle and a polygon, such as a rectangle, a hexagon, etc.

[0102] Exemplarily, when the second type of nested structure 22 is arranged in a ring shape along the fourth direction P, there are multiple second type of nested structures 22 arranged in a ring shape around the terminal area 2a in the cell area 1a, and a certain distance is separated between each second type of nested structure 22 arranged in a ring shape, that is, they are arranged in a progressive manner along the fourth direction P.

[0103] It can be understood that setting multiple second type of nested structures 22 in the cell area 1a can enhance the interconnection ability between the first conductive layer 51 and the substrate 3 of the entire cell area 1a, be able to adapt to a more complex circuit layout; moreover, it can also enhance the structural stability of the chip 100 and improve its mechanical strength.

[0104] In some embodiments, as Figure 1As shown in the figure, the chip 100 includes: a semiconductor device 10 located in the cell region 1a. The semiconductor device 10 includes: any one of a metal-oxide-semiconductor field-effect transistor, a Schottky Barrier Diode (SBD), a Junction Field-Effect Transistor (JFET), an Insulated Gate Bipolar Transistor (IGBT), and a High Electron Mobility Transistor (HEMT).

[0105] Exemplarily, the semiconductor devices 10 may be arranged in an array within the cell region 1a.

[0106] The metal-oxide-semiconductor field-effect transistor is composed of a conductive layer 5 (such as metal), a metal gate 71 / polycrystalline silicon gate 72, an oxide insulating layer (SiO2 / SiON), and a substrate 3, and the on-state of the conductive channel is regulated by the gate voltage.

[0107] The Schottky Barrier Diode is formed by the contact between a metal and a semiconductor. This contact forms a Schottky barrier, which has unidirectional conductivity. The film layer of the Schottky Barrier Diode includes: a conductive layer 5 (such as aluminum, titanium, gold, etc.), and a semiconductor layer (such as silicon, GaAs).

[0108] The Junction Field-Effect Transistor controls the current between the drain and the source by changing the width of the channel by changing the voltage between the gate and the source.

[0109] The Insulated Gate Bipolar Transistor combines the easy drivability of the metal-oxide-semiconductor field-effect transistor and the high current-carrying capacity of the bipolar transistor. It has both the gate control characteristics of the metal-oxide-semiconductor field-effect transistor and the low on-resistance of the bipolar transistor, and can carry a large current.

[0110] The High Electron Mobility Transistor conducts electricity by using the two-dimensional electron gas formed at the heterojunction interface. Since the electron mobility in the two-dimensional electron gas is very high, the High Electron Mobility Transistor has very high speed and frequency characteristics. The High Electron Mobility Transistor device includes multiple film layers such as a conductive layer 5, a gate 7, and an insulating layer 4.

[0111] It can be seen from this that the above semiconductor devices 10 can all be semiconductor devices 10 with multiple film layers. By providing a first type of nested structure 21 and a second type of nested structure 22 on the chip 100 formed by using these semiconductor devices 10, the reliability of the chip 100 can be improved.

[0112] In the following, taking a metal-oxide-semiconductor field-effect transistor as an example, the chip 100 of the present disclosure will be described in detail in Embodiment 1.

[0113] Embodiment 1 Embodiment 1 provides a chip 100, which is combined with Figure 14 , and its preparation process is as follows: steps (1) to (8).

[0114] (1) A first trench 211G is etched on the substrate 3, and the depth H of the first trench 211G is 0.2 μm - 5 μm.

[0115] Exemplarily, when the formed metal-oxide-semiconductor field-effect transistor is a planar device, the first trench 211G can be formed during zero-layer lithography; when the formed metal-oxide-semiconductor field-effect transistor is a trench device, the first trench 211G can be formed by lithography while lithographing the pole piece trench at zero layer, and the specific depth is consistent with the etching depth of the same film layer.

[0116] (2) A structure region 9 is formed by ion implantation on the substrate 3.

[0117] Exemplarily, the structure region 9 can be an N-well and a P-well.

[0118] (3) A first insulating layer 41 is formed on one side of the substrate 3, and the first insulating layer 41 is filled into the first trench 211G to form a first protrusion 211T, so as to obtain a structure in which the first protrusion 211T fills the first trench 211G, and the first insulating layer 41 is etched to form a second trench 212G. The thickness of the first insulating layer 41 can be 0.6 μm to 3 μm. Here, the first insulating layer 41 is a field oxide insulating layer (FOX).

[0119] Exemplarily, the forming method of the first insulating layer 41 can be any one of plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, and thermal deposition.

[0120] (4) A gate oxide layer 8 and a polysilicon gate 72 are formed on the side of the first insulating layer 41 away from the substrate 3. The thickness of the gate oxide layer 8 is 50 μm to 200 μm, and the thickness of the polysilicon gate 72 is 0.1 μm to 1 μm.

[0121] Exemplarily, the forming method of the gate oxide layer 8 can be any one of plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, and thermal deposition.

[0122] Exemplarily, the forming method of the polysilicon gate 72 is low-pressure chemical vapor deposition.

[0123] (5) A second insulating layer 42 is formed. A part of the material of the second insulating layer 42 is filled into the second trench 212G on the first insulating layer 41 to form a second protrusion 212T on the second insulating layer 42, so as to obtain a structure in which the second protrusion 212T fills the second trench 212G. Meanwhile, the second insulating layer 42 in the terminal region 2a is etched to form the second trench 212G, and the second insulating layer 42 in the first sub-region 2A of the terminal region 2a is etched to form a through hole K penetrating the second insulating layer 42, and the second insulating layer 42 in the cell region 1a is etched to form a third trench 22G. Here, the second insulating layer 42 is an interlayer insulating layer.

[0124] Exemplarily, the material of the interlayer insulating layer can be at least one of SiO, SiN, BPSG, PSG, and SiON.

[0125] Exemplarily, the formation method of the interlayer insulating layer can be any one of plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, and thermal deposition.

[0126] (6) The second insulating layer 42 is etched to contact the polysilicon gate 72.

[0127] (7) The metal of the first conductive layer 51 is deposited into the third trench 22G to obtain a structure in which the third protrusion 22T fills the third trench 22G, the first conductive layer 51 is formed, and at the same time, a metal gate 71 is etched. Here, the first conductive layer 51 can be a source electrode.

[0128] Exemplarily, the metal can be Al, Ag, Cu, etc.

[0129] Exemplarily, the formation method is physical vapor deposition or evaporation.

[0130] (8) A passivation layer 43 is formed. A part of the material of the passivation layer 43 is filled into the second trench 212G on the second insulating layer 42 to form a second protrusion 212G on the passivation layer 43, so as to obtain a structure in which the second protrusion 212T fills the second trench 212G. Meanwhile, the material of the passivation layer 43 is filled into the through hole K so that the material of the passivation layer 43 contacts the substrate 3. Here, the passivation layer 43 can be a combination of multiple film layers and can still be set in an intercalated mode. The passivation layer 43 can be a dielectric layer, a polymer, or a combination of both.

[0131] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A chip, characterized in that, Comprising: A cell region and a terminal region surrounding the cell region; The chip further comprises: a substrate, a multi-layer insulating layer on one side of the substrate, and a first type of nested structure in the terminal region; Wherein, the first type of nested structure comprises: a first nested structure, and the first nested structure comprises: a first trench provided on the substrate and facing the insulating layer side, and a first protrusion provided on the insulating layer adjacent to the substrate and facing the substrate side, and the first protrusion fills the first trench.

2. The chip according to claim 1, characterized in that, The depth range of the first trench is 0.02μm to 5μm.

3. The chip according to claim 1, wherein The first type of nested structure comprises: a second nested structure; The second nested structure comprises: a second trench provided on the first insulating layer and facing away from the substrate direction, and a second protrusion provided on the second insulating layer and facing the substrate direction, and the second protrusion fills the second trench; Wherein, the first insulating layer and the second insulating layer are adjacent to each other, and the second insulating layer is located on the side of the first insulating layer away from the substrate.

4. The chip according to claim 3, wherein In the orthographic projection onto the substrate, the first nested structure and the second nested structure overlap.

5. The chip according to claim 4, wherein Along a first direction, the number of the first type of nested structures is multiple, and the multiple first type of nested structures are arranged at intervals; wherein, the first direction surrounds the cell region.

6. The chip according to claim 5, characterized in that, The orthographic projection of the first type of nested structure on the substrate includes at least one of a circle and a polygon.

7. The chip according to claim 5, characterized in that, The first type of nested structure is arranged in a ring shape along the first direction.

8. The chip according to claim 3, wherein Among the multi-layer insulating layers, the number of the second nested structures further away from the substrate is greater than or equal to the number of the second nested structures closer to the substrate.

9. The chip according to claim 1, characterized in that, Along a second direction, the number of the first type of nested structures is multiple, and the multiple first type of nested structures are arranged at intervals; wherein, the second direction is the direction away from the cell region.

10. The chip according to claim 1, characterized in that, The multi-layer insulating layer includes: an interlayer dielectric layer and a passivation layer on the side of the interlayer dielectric layer away from the substrate; In the terminal region, there is a first sub-region, and in the orthographic projection onto the substrate, the first sub-region is located on the side of the first type of nested structure away from the cell region; in the first sub-region, the substrate, the interlayer dielectric layer, and the passivation layer are sequentially in contact. The chip further comprises: a through hole penetrating the interlayer dielectric layer, and a part of the passivation layer penetrates the through hole and contacts the substrate.

11. The chip according to claim 1, characterized in that, Further comprising: At least one conductive layer on one side of the substrate and a second type of nested structure in the cell region; The conductive layer includes a first conductive layer, and the first conductive layer is located on the side of the insulating layer away from the substrate; The second type of nested structure comprises: a third trench provided on the substrate and / or the insulating layer and facing away from the first conductive layer side, and a third protrusion provided on the first conductive layer and facing the substrate side, and the third protrusion fills the third trench.

12. The chip according to claim 11, characterized in that, Along a third direction, the number of the second type of nested structures is multiple, and the multiple second type of nested structures are arranged at intervals; wherein, the third direction is the direction extending along the edge of the first conductive layer.

13. The chip according to claim 11, wherein The second type of nested structure is arranged in a ring shape along the third direction.

14. The chip according to claim 12 or 13, characterized in that, Along the fourth direction, the number of the second type of nested structures is multiple, and the multiple second type of nested structures are arranged at intervals; wherein, the fourth direction is the direction away from the terminal region.

15. The chip according to claim 14, characterized in that, The orthographic projection of the second type of nested structure on the substrate includes at least one of a circle and a polygon.

16. The chip according to claim 1, wherein Comprising: A semiconductor device located in the cell region; The semiconductor device includes any one of a metal-oxide-semiconductor field effect transistor, a Schottky barrier diode, a junction field effect transistor, an insulated gate bipolar transistor, and a high electron mobility transistor.

17. An electronic device, characterized in that, Including the chip according to any one of claims 1 to 16.

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