A constant-time soft-start circuit and method for power transistors independent of input voltage.

Abstract

This invention discloses a constant-time soft-start circuit and method for power transistors independent of input voltage. It includes a power transistor NM1, a soft-start current generation circuit, a current mirror circuit, a soft-start capacitor Cs, and a soft-start loop. The drain of power transistor NM1 is connected to the input signal VIN, and the source of power transistor NM1 generates an output signal VOUT. The soft-start current generation circuit generates a soft-start current Is1. The current mirror circuit replicates the soft-start current Is1 and charges the soft-start capacitor Cs to generate a ramp signal V2. The gate of power transistor NM1 is connected to a signal VG. The soft-start loop clamps the voltage divider signal V1 of signal VG to follow the ramp signal V2. This invention uses a negative feedback loop to control the gate voltage of the power transistor to follow a ramp signal that varies with the input voltage, decoupling the soft-start time from the input voltage, ultimately achieving a constant-time soft-start of the power transistor independent of the input voltage.

Description

Technical Field

[0001] This invention relates to a soft-start circuit and method, particularly a constant-time soft-start circuit and method for power transistors that is independent of input voltage, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] In power management systems, soft-start technology is one of the core mechanisms for ensuring system reliability and safety. During the startup phase of traditional power systems, the instantaneous conduction of power devices (such as MOSFETs) and the rapid charging of the input capacitor can lead to extremely large inrush currents, potentially causing overcurrent damage to power transistors, a drop in input power supply voltage, and failure of downstream loads due to voltage overshoot. Furthermore, the rapid charging and discharging of large-capacity energy storage components exacerbates electromagnetic interference (EMI), affecting system stability. While existing technologies employ simple RC delay circuits or fixed-slope startup strategies to limit current surges to some extent, their soft-start time is significantly affected by the input voltage. The soft-start time for high-voltage and low-voltage inputs can differ by 5 to 10 times, making them unsuitable for applications requiring rapid startup. Therefore, it is necessary to propose a constant-time soft-start circuit for power transistors that is independent of the input voltage. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a power transistor constant-time soft-start circuit and method that is independent of the input voltage, so as to realize the power transistor constant-time soft-start independent of the input voltage.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0005] A constant-time soft-start circuit for a power transistor independent of input voltage includes a power transistor NM1, a soft-start current generation circuit, a current mirror circuit, a soft-start capacitor Cs, and a soft-start loop. The drain of the power transistor NM1 is connected to the input signal VIN, and the source of the power transistor NM1 generates an output signal VOUT. The soft-start current generation circuit generates a soft-start current Is1. The current mirror circuit replicates the soft-start current Is1 and charges the soft-start capacitor Cs to generate a ramp signal V2. The gate of the power transistor NM1 is connected to the signal VG. The soft-start loop clamps the voltage divider signal V1 of the signal VG to follow the ramp signal V2.

[0006] Furthermore, it also includes a charge pump, the input of which is connected to the input signal VIN, and the output of which generates the signal VCP.

[0007] Furthermore, the soft-start current generation circuit includes PMOS transistors PM2 and PM4, NMOS transistor NM3, resistor Rs, and an operational amplifier. The source of PMOS transistor PM2 is connected to the input signal VIN. The drain of PMOS transistor PM2 is connected to the gate of PMOS transistor PM2 and the source of PMOS transistor PM4. The drain of PMOS transistor PM4 is connected to the gate of PMOS transistor PM4 and the drain of NMOS transistor NM3. The gate of NMOS transistor NM3 is connected to the output terminal of operational amplifier A2. The source of NMOS transistor NM3 is connected to one end of resistor Rs and the inverting input terminal of operational amplifier A2 to generate signal V4. The other end of resistor Rs is grounded. The non-inverting input terminal of operational amplifier A2 is connected to signal V3.

[0008] Furthermore, the signal V3 is generated by a first voltage divider circuit, which includes resistors R3 and R4. One end of resistor R3 is connected to signal VCP, and the other end of resistor R3 is connected to one end of resistor R4 to generate signal V3. The other end of resistor R4 is grounded.

[0009] Furthermore, the current mirror circuit includes PMOS transistors PM1, PM2, PM3, and PM4. The source of PMOS transistor PM1 and the source of PMOS transistor PM2 are connected to the input signal VIN. The gate of PMOS transistor PM1 is connected to the gate of PMOS transistor PM2, the drain of PMOS transistor PM2, and the source of PMOS transistor PM4. The drain of PMOS transistor PM1 is connected to the source of PMOS transistor PM3. The gate of PMOS transistor PM3 is connected to the gate of PMOS transistor PM4, the drain of PMOS transistor PM4, and the drain of NMOS transistor NM3. The drain of PMOS transistor PM3 is connected to one end of the soft-start capacitor Cs and generates a ramp signal V2. The other end of the soft-start capacitor Cs is grounded.

[0010] Furthermore, the soft-start loop includes a second voltage divider circuit, an operational amplifier A1, a current source ICP, and an NMOS transistor NM2. The input terminal of the second voltage divider circuit is connected to signal VG, and the output terminal of the second voltage divider circuit is connected to the non-inverting input terminal of the operational amplifier A1 to generate signal V1. The inverting input terminal of the operational amplifier A1 is connected to a ramp signal V2. The output terminal of the operational amplifier A1 is connected to the gate of the NMOS transistor NM2. The source of the NMOS transistor NM2 is grounded, and the drain of the NMOS transistor NM2 is connected to one end of the current source ICP and signal VG. The other end of the current source ICP is connected to signal VCP.

[0011] Furthermore, the second voltage divider circuit includes resistors R1 and R2. One end of resistor R1 is connected to signal VG, and the other end of resistor R1 is connected to one end of resistor R2 to generate signal V1. The other end of resistor R2 is grounded.

[0012] A soft-start method for a power transistor constant-time soft-start circuit independent of input voltage includes the following steps:

[0013] The power transistor NM1 is used to turn the input voltage and load on or off.

[0014] Resistors R3 and R4 form a second voltage divider circuit, which divides the signal VCP output by the charge pump according to a preset ratio to obtain signal V3. Signal V3 satisfies the following relationship:

[0015] ,

[0016] Operational amplifier A2, NMOS transistor NM3, PMOS transistors PM2 and PM4, and resistor Rs form a negative feedback loop, generating a soft-start current Is1. Operational amplifier A2 receives signal V3 at its non-inverting input and signal V4 at its inverting input. When V4 > V3, the output voltage of operational amplifier A2 decreases, causing a decrease in the source voltage of NMOS transistor NM3, thus forming negative feedback. Ultimately, this results in V4 = V3. Therefore, the soft-start current Is1 across resistor Rs satisfies the following relationship:

[0017]

[0018] PMOS transistors PM1, PM2, PM3, and PM4 form a current mirror circuit. PMOS transistors PM1 and PM2 have the same width-to-length ratio, and PMOS transistors PM3 and PM4 have the same width-to-length ratio. Therefore, the current Is2 on PMOS transistor PM1 is equal to the soft-start current Is1. This current Is2 charges the soft-start capacitor Cs, generating a ramp signal V2. The ramp signal V2 satisfies the following relationship:

[0019]

[0020] Resistors R1 and R2 form a voltage divider circuit, dividing the gate voltage of the power transistor according to a preset ratio. Assuming the gate voltage of the power transistor is VG and the voltage signal after voltage division is V1, then V1 satisfies the following relationship.

[0021] ,

[0022] Operational amplifier A1, NMOS transistor NM2, resistors R1 and R2 form a negative feedback soft-start loop. Operational amplifier A1 receives signal V1 at its non-inverting input and ramp signal V2 at its inverting input. When V1 > V2, the output voltage of operational amplifier A1 rises, and the gate voltage VG of power transistor NM1 drops. This causes signal V1 to decrease, thus creating negative feedback, ultimately resulting in V1 = V2.

[0023]

[0024] t is the soft-start time. Since the gate voltage of power transistor NM1 will be charged to the charge pump output signal VCP when the soft-start ends, the above equation simplifies to:

[0025]

[0026] Therefore, the soft-start time t is determined only by the soft-start capacitor Cs, resistor Rs, the ratio of resistor R3 and resistor R4, and the ratio of resistor R1 and resistor R2, and is independent of the input signal VIN.

[0027] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a power transistor constant-time soft-start circuit and method independent of input voltage. Through negative feedback loop control, the gate voltage of the power transistor follows a ramp signal that varies with the input voltage, thereby decoupling the soft-start time from the input voltage and ultimately realizing a power transistor constant-time soft-start independent of the input voltage. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a power transistor constant-time soft-start circuit that is independent of input voltage according to the present invention. Detailed Implementation

[0029] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0030] like Figure 1 As shown, the present invention provides a constant-time soft-start circuit for a power transistor independent of input voltage, comprising a power transistor NM1, a soft-start current generation circuit, a current mirror circuit, a soft-start capacitor Cs, and a soft-start loop. The drain of the power transistor NM1 is connected to the input signal VIN, and the source of the power transistor NM1 generates an output signal VOUT. The soft-start current generation circuit generates a soft-start current Is1. The current mirror circuit replicates the soft-start current Is1 and charges the soft-start capacitor Cs to generate a ramp signal V2. The gate of the power transistor NM1 is connected to the signal VG. The soft-start loop clamps the voltage divider signal V1 of the signal VG to follow the ramp signal V2.

[0031] The power transistor constant-time soft-start circuit of the present invention, which is independent of input voltage, further includes a charge pump, the input terminal of which is connected to the input signal VIN, and the output terminal of which generates the signal VCP.

[0032] The soft-start current generation circuit includes PMOS transistors PM2 and PM4, NMOS transistor NM3, resistor Rs, and an operational amplifier. The source of PMOS transistor PM2 is connected to the input signal VIN. The drain of PMOS transistor PM2 is connected to the gate of PMOS transistor PM2 and the source of PMOS transistor PM4. The drain of PMOS transistor PM4 is connected to the gate of PMOS transistor PM4 and the drain of NMOS transistor NM3. The gate of NMOS transistor NM3 is connected to the output terminal of operational amplifier A2. The source of NMOS transistor NM3 is connected to one end of resistor Rs and the inverting input terminal of operational amplifier A2 to generate signal V4. The other end of resistor Rs is grounded. The non-inverting input terminal of operational amplifier A2 is connected to signal V3.

[0033] The signal V3 is generated by the first voltage divider circuit, which includes resistors R3 and R4. One end of resistor R3 is connected to signal VCP, and the other end of resistor R3 is connected to one end of resistor R4 to generate signal V3. The other end of resistor R4 is grounded.

[0034] The current mirror circuit includes PMOS transistors PM1, PM2, PM3, and PM4. The sources of PMOS transistors PM1 and PM2 are connected to the input signal VIN. The gates of PMOS transistors PM1 and PM2, the drain of PMOS transistors PM2 and PM4 are connected to the source. The drain of PMOS transistors PM1 and PM3 is connected to the source. The gates of PMOS transistors PM3 and PM4, the drain of PMOS transistors PM4 and NMOS transistor NM3 are connected to the drain. The drain of PMOS transistor PM3 is connected to one end of the soft-start capacitor Cs and generates a ramp signal V2. The other end of the soft-start capacitor Cs is grounded.

[0035] The soft-start loop includes a second voltage divider circuit, operational amplifier A1, current source ICP, and NMOS transistor NM2. The input of the second voltage divider circuit is connected to signal VG, and the output of the second voltage divider circuit is connected to the non-inverting input of operational amplifier A1 to generate signal V1. The inverting input of operational amplifier A1 is connected to ramp signal V2, and the output of operational amplifier A1 is connected to the gate of NMOS transistor NM2. The source of NMOS transistor NM2 is grounded, and the drain of NMOS transistor NM2 is connected to one end of current source ICP and signal VG. The other end of current source ICP is connected to signal VCP.

[0036] The second voltage divider circuit includes resistors R1 and R2. One end of resistor R1 is connected to signal VG, and the other end of resistor R1 is connected to one end of resistor R2 to generate signal V1. The other end of resistor R2 is grounded.

[0037] A soft-start method for a power transistor constant-time soft-start circuit independent of input voltage includes the following steps:

[0038] The power transistor NM1 is used to turn on or off the input voltage and load.

[0039] Resistors R3 and R4 form a second voltage divider circuit, which divides the signal VCP output by the charge pump according to a preset ratio to obtain signal V3. Signal V3 satisfies the following relationship:

[0040] ,

[0041] Operational amplifier A2, NMOS transistor NM3, PMOS transistors PM2 and PM4, and resistor Rs form a negative feedback loop, generating a soft-start current Is1. Operational amplifier A2 receives signal V3 at its non-inverting input and signal V4 at its inverting input. When V4 > V3, the output voltage of operational amplifier A2 decreases, causing a decrease in the source voltage of NMOS transistor NM3, thus forming negative feedback. Ultimately, this results in V4 = V3. Therefore, the soft-start current Is1 across resistor Rs satisfies the following relationship:

[0042]

[0043] PMOS transistors PM1, PM2, PM3, and PM4 form a current mirror circuit. PMOS transistors PM1 and PM2 have the same width-to-length ratio, and PMOS transistors PM3 and PM4 have the same width-to-length ratio. Therefore, the current Is2 on PMOS transistor PM1 is equal to the soft-start current Is1. This current Is2 charges the soft-start capacitor Cs, generating a ramp signal V2. The ramp signal V2 satisfies the following relationship:

[0044]

[0045] Resistors R1 and R2 form a voltage divider circuit, dividing the gate voltage of the power transistor according to a preset ratio. Assuming the gate voltage of the power transistor is VG and the voltage signal after voltage division is V1, then V1 satisfies the following relationship.

[0046] ,

[0047] Operational amplifier A1, NMOS transistor NM2, resistors R1 and R2 form a negative feedback soft-start loop. Operational amplifier A1 receives signal V1 at its non-inverting input and ramp signal V2 at its inverting input. When V1 > V2, the output voltage of operational amplifier A1 rises, and the gate voltage VG of power transistor NM1 drops. This causes signal V1 to decrease, thus creating negative feedback, ultimately resulting in V1 = V2.

[0048]

[0049] t is the soft-start time. Since the gate voltage of power transistor NM1 will be charged to the charge pump output signal VCP when the soft-start ends, the above equation simplifies to:

[0050]

[0051] Therefore, the soft-start time t is determined only by the soft-start capacitor Cs, resistor Rs, the ratio of resistor R3 and resistor R4, and the ratio of resistor R1 and resistor R2, and is independent of the input signal VIN.

[0052] This invention provides a constant-time soft-start circuit and method for power transistors that is independent of input voltage. By controlling the negative feedback loop, the gate voltage of the power transistor follows a ramp signal that varies with the input voltage, thereby decoupling the soft-start time from the input voltage and ultimately achieving a constant-time soft-start of the power transistor that is independent of the input voltage.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A constant-time soft-start circuit for a power transistor independent of input voltage, characterized in that: It includes a power transistor NM1, a soft-start current generation circuit, a current mirror circuit, a soft-start capacitor Cs, and a soft-start loop. The drain of the power transistor NM1 is connected to the input signal VIN, the source of the power transistor NM1 generates the output signal VOUT, the soft-start current generation circuit generates the soft-start current Is1, the current mirror circuit replicates the soft-start current Is1 and charges the soft-start capacitor Cs to generate a ramp signal V2, the gate of the power transistor NM1 is connected to the signal VG, and the soft-start loop clamps the voltage divider signal V1 of the signal VG to follow the ramp signal V2. It also includes a charge pump, whose input terminal is connected to the input signal VIN, and whose output terminal generates the signal VCP; The soft-start current generation circuit includes PMOS transistors PM2 and PM4, NMOS transistor NM3, resistor Rs, and an operational amplifier. The source of PMOS transistor PM2 is connected to the input signal VIN. The drain of PMOS transistor PM2 is connected to the gate of PMOS transistor PM2 and the source of PMOS transistor PM4. The drain of PMOS transistor PM4 is connected to the gate of PMOS transistor PM4 and the drain of NMOS transistor NM3. The gate of NMOS transistor NM3 is connected to the output terminal of operational amplifier A2. The source of NMOS transistor NM3 is connected to one end of resistor Rs and the inverting input terminal of operational amplifier A2 to generate signal V4. The other end of resistor Rs is grounded. The non-inverting input terminal of operational amplifier A2 is connected to signal V3. The signal V3 is generated by a first voltage divider circuit, which includes resistors R3 and R4. One end of resistor R3 is connected to signal VCP, and the other end of resistor R3 is connected to one end of resistor R4 to generate signal V3. The other end of resistor R4 is grounded. The current mirror circuit includes PMOS transistors PM1, PM2, PM3, and PM4. The source of PMOS transistor PM1 and the source of PMOS transistor PM2 are connected to the input signal VIN. The gate of PMOS transistor PM1 is connected to the gate of PMOS transistor PM2, the drain of PMOS transistor PM2 is connected to the source of PMOS transistor PM4, the drain of PMOS transistor PM1 is connected to the source of PMOS transistor PM3, the gate of PMOS transistor PM3 is connected to the gate of PMOS transistor PM4, the drain of PMOS transistor PM4 is connected to the drain of NMOS transistor NM3, and the drain of PMOS transistor PM3 is connected to one end of the soft-start capacitor Cs to generate a ramp signal V2. The other end of the soft-start capacitor Cs is grounded. The soft-start loop includes a second voltage divider circuit, an operational amplifier A1, a current source ICP, and an NMOS transistor NM2. The input of the second voltage divider circuit is connected to signal VG, and the output of the second voltage divider circuit is connected to the non-inverting input of operational amplifier A1 to generate signal V1. The inverting input of operational amplifier A1 is connected to a ramp signal V2. The output of operational amplifier A1 is connected to the gate of NMOS transistor NM2. The source of NMOS transistor NM2 is grounded, and the drain of NMOS transistor NM2 is connected to one end of the current source ICP and signal VG. The other end of the current source ICP is connected to signal VCP.

2. The power transistor constant-time soft-start circuit independent of input voltage according to claim 1, characterized in that: The second voltage divider circuit includes resistors R1 and R2. One end of resistor R1 is connected to signal VG, and the other end of resistor R1 is connected to one end of resistor R2 to generate signal V1. The other end of resistor R2 is grounded.

3. A soft-start method based on the constant-time soft-start circuit of the power transistor independent of input voltage as described in claim 2, characterized in that... Includes the following steps: The power transistor NM1 is used to turn the input voltage and load on or off. Resistors R3 and R4 form a second voltage divider circuit, which divides the signal VCP output by the charge pump according to a preset ratio to obtain signal V3. Signal V3 satisfies the following relationship: ， Operational amplifier A2, NMOS transistor NM3, PMOS transistors PM2 and PM4, and resistor Rs form a negative feedback loop, generating a soft-start current Is1. Operational amplifier A2 receives signal V3 at its non-inverting input and signal V4 at its inverting input. When V4 > V3, the output voltage of operational amplifier A2 decreases, causing a decrease in the source voltage of NMOS transistor NM3, thus forming negative feedback. Ultimately, this results in V4 = V3. Therefore, the soft-start current Is1 across resistor Rs satisfies the following relationship: PMOS transistors PM1, PM2, PM3, and PM4 form a current mirror circuit. PMOS transistors PM1 and PM2 have the same width-to-length ratio, and PMOS transistors PM3 and PM4 have the same width-to-length ratio. Therefore, the current Is2 on PMOS transistor PM1 is equal to the soft-start current Is1. This current Is2 charges the soft-start capacitor Cs, generating a ramp signal V2. The ramp signal V2 satisfies the following relationship: Resistors R1 and R2 form a voltage divider circuit, dividing the gate voltage of the power transistor according to a preset ratio. Assuming the gate voltage of the power transistor is VG and the voltage signal after voltage division is V1, then V1 satisfies the following relationship. ， Operational amplifier A1, NMOS transistor NM2, resistors R1 and R2 form a negative feedback soft-start loop. Operational amplifier A1 receives signal V1 at its non-inverting input and ramp signal V2 at its inverting input. When V1 > V2, the output voltage of operational amplifier A1 rises, and the gate voltage VG of power transistor NM1 drops. This causes signal V1 to decrease, thus creating negative feedback, ultimately resulting in V1 = V2. t is the soft-start time. Since the gate voltage of power transistor NM1 will be charged to the charge pump output signal VCP when the soft-start ends, the above equation simplifies to: Therefore, the soft-start time t is determined only by the soft-start capacitor Cs, resistor Rs, the ratio of resistor R3 and resistor R4, and the ratio of resistor R1 and resistor R2, and is independent of the input signal VIN.

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