Single-resistor sampling method, electronic equipment, storage medium and product

Abstract

The invention discloses a single-resistor sampling method, electronic equipment, a storage medium and a product, and relates to the technical field of motor control, and the disclosed single-resistor sampling method comprises the steps: configuring the size of a sampling window and the moving size of a sampling point under a hardware topology in which a single sampling resistor is connected in series with a bus, determining a sampling moment according to the size of the sampling window and the moving size of the sampling point; and in each carrier period, two-phase current is selected for current sampling according to a predefined sampling mode at a sampling moment. According to the invention, a current sampling mode for a square-wave high-frequency signal injection scene can be optimized.

Description

Technical Field

[0001] The present application relates to the technical field of motor control, and particularly to a single-resistor sampling method, an electronic device, a storage medium, and a product. Background Art

[0002] In motor control, the position of the motor rotor is estimated by injecting a square-wave high-frequency signal and extracting the corresponding high-frequency response current, thereby improving the control performance of the motor.

[0003] During the injection of the square-wave high-frequency signal, it is necessary to accurately sample the high-frequency response current. In the current sampling of the motor, there are mainly three sampling methods: single-resistor, double-resistor, and triple-resistor. Among them, the double-resistor and triple-resistor sampling modes are fixed during the zero vector period during sampling, resulting in heat generation and wiring problems. The single-resistor sampling mode has a non-fixed sampling time, complex calculation, and large error.

[0004] In summary, how to optimize the current sampling method for the square-wave high-frequency signal injection scenario has become an urgent technical problem in this field. Summary of the Invention

[0005] The main purpose of the present application is to provide a single-resistor sampling method, an electronic device, a storage medium, and a product, aiming to optimize the current sampling method for the square-wave high-frequency signal injection scenario.

[0006] To achieve the above object, the present application proposes a single-resistor sampling method, which includes:

[0007] Under the hardware topology where a single sampling resistor is connected in series to the bus, configure the sampling window size and the sampling point movement size, and determine the sampling time according to the sampling window size and the sampling point movement size;

[0008] In each carrier period, select two-phase currents for current sampling according to a predefined sampling mode at the sampling time.

[0009] In an embodiment, the step of configuring the sampling window size and the sampling point movement size, and determining the sampling time according to the sampling window size and the sampling point movement size includes:

[0010] Determine the sampling window size and the sampling point movement size according to the MOS transistor switch delay time and the switch oscillation time;

[0011] Adopt an edge-aligned timer counting mode to determine the position of the sampling window;

[0012] Take the midpoint of the sampling window as the default sampling time, and move the sampling time forward and backward from the default sampling time according to the sampling point movement size.

[0013] In one embodiment, the sampling mode includes a dynamic sampling mode. In each carrier period, the step of selecting two-phase currents for current sampling according to a predefined sampling mode at the sampling moment includes:

[0014] In the dynamic sampling mode, in each carrier period, two-phase currents are selected for sampling according to the sector where the current voltage vector is located at the sampling moment.

[0015] In one embodiment, the sampling mode includes a fixed sampling mode and a sector reconstruction sampling mode. In each carrier period, the step of selecting two-phase currents for current sampling according to a predefined sampling mode at the sampling moment includes:

[0016] In the fixed sampling mode, in each carrier period, the b-phase current and the c-phase current are selected for current sampling at the sampling moment;

[0017] According to the amplitude of the synthesized voltage vector, the fixed sampling mode is dynamically switched to the sector reconstruction sampling mode, where the sector reconstruction sampling mode is to reconstruct three-phase currents according to sectors at dynamically changing sampling moments.

[0018] In one embodiment, the step of dynamically switching the fixed sampling mode to the sector reconstruction sampling mode according to the amplitude of the synthesized voltage vector includes:

[0019] Obtain the amplitude of the synthesized voltage vector in real time;

[0020] When the amplitude of the synthesized voltage vector exceeds a preset threshold, the fixed sampling mode is dynamically switched to the sector reconstruction sampling mode, and when switching, it is necessary to satisfy that the current sector is consistent with the sampling sector for collecting the b-phase current and the c-phase current in the sector reconstruction sampling mode.

[0021] In one embodiment, the sampling moment includes a first sampling moment and a second sampling moment. In the fixed sampling mode, the step of selecting the b-phase current and the c-phase current for current sampling at the sampling moment in each carrier period includes:

[0022] In the fixed sampling mode, the minimum high-level time limit of the upper bridge of the a-phase is one sampling window time, the maximum high-level time limit of the upper bridge of the a-phase is the carrier period minus the sampling window time, the minimum high-level time limit of the upper bridge of the b-phase is twice the sampling window time; the maximum high-level time limit of the c-phase is the carrier period minus twice the sampling window time;

[0023] In each carrier period, the b-phase current is selected for current sampling at the first sampling moment, and the c-phase current is selected for current sampling at the second sampling moment.

[0024] In one embodiment, before the steps of configuring the sampling window size and the sampling point movement size and determining the sampling moment according to the sampling window size and the sampling point movement size under the hardware topology where a single sampling resistor is connected in series to the bus, the method further includes:

[0025] Connect a single sampling resistor in series to the DC bus, differentially amplify the voltage signal of the sampling resistor through an operational amplifier, and input the amplified voltage signal into the AD channel.

[0026] In addition, to achieve the above object, the present application further provides an electronic device, which includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, and the computer program is configured to implement the steps of the single-resistor sampling method as described above.

[0027] In addition, to achieve the above object, the present application further provides a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium, and when the computer program is executed by the processor, it implements the steps of the single-resistor sampling method as described above.

[0028] In addition, to achieve the above object, the present application further provides a computer program product, which includes a computer program, and when the computer program is executed by the processor, it implements the steps of the single-resistor sampling method as described above.

[0029] The present application provides a single-resistor sampling method. Under the hardware topology where a single sampling resistor is connected in series to the bus, the sampling window size and the sampling point movement size are configured, and the sampling moment is determined according to the sampling window size and the sampling point movement size; within each carrier period, two-phase currents are selected for current sampling according to a predefined sampling pattern at the sampling moment.

[0030] In summary, in the present application, by connecting a single sampling resistor in series to the bus and configuring the sampling window size and the sampling point movement size, two-phase current sampling at a fixed moment within each carrier period is realized. Compared with the traditional double-resistor and triple-resistor sampling modes, it can reduce the power consumption of the sampling resistor, reduce the heating problem, simplify the hardware layout at the same time, reduce the wiring difficulty and cost. At the same time, by fixing the sampling moment and selecting specific phase currents for sampling, the calculation process of high-frequency response current can be simplified, the calculation error can be reduced, thereby optimizing the control effect and improving the motor control performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0032] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0033] Figure 1 It is a schematic flowchart provided for Embodiment 1 of the single-resistor sampling method of the present application;

[0034] Figure 2 It is a schematic diagram of a hardware topology provided for Embodiment 2 of the single-resistor sampling method of the present application;

[0035] Figures 3(a) to 3(f) It is a switching waveform diagram of each sector provided for Embodiment 2 of the single-resistor sampling method of the present application;

[0036] Figure 4 It is another schematic diagram of a hardware topology provided for Embodiment 2 of the single-resistor sampling method of the present application;

[0037] Figures 5(a) to 5(f) It is another switching waveform diagram of each sector provided for Embodiment 2 of the single-resistor sampling method of the present application;

[0038] Figure 6 It is a schematic diagram of the device structure of the hardware operating environment involved in the single-resistor sampling method in the embodiments of the present application.

[0039] The realization of the purpose, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0040] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0041] To better understand the technical solutions of the present application, the following will be described in detail in combination with the accompanying drawings of the specification and the specific implementation manners.

[0042] In motor control, the position of the motor rotor is estimated by injecting a square-wave high-frequency signal and extracting the corresponding high-frequency response current, thereby improving the control performance of the motor.

[0043] During the injection of the square-wave high-frequency signal, it is necessary to accurately sample the high-frequency response current. In the current sampling of the motor, it is mainly divided into three sampling methods: single resistor, double resistor and triple resistor. Among them, the double-resistor and triple-resistor sampling modes are fixed during the zero vector period during sampling, resulting in heating and wiring problems. The single-resistor sampling mode has a non-fixed sampling moment, complex calculation and large error.

[0044] Specifically, in the single-update mode, the injection frequency of square-wave high-frequency injection can be half of the carrier frequency. Herein, the single-update mode means that only one PWM (Pulse-Width Modulation) update is performed within one carrier period. Currently, the commonly used sampling methods in the market are the dual-resistor sampling mode or the three-resistor sampling mode. Since these two modes sample at the zero vector with all three lower bridges fully open, the high-frequency current generated by the high-frequency voltage injected in the previous carrier period can be sampled. As the current flowing through the sampling resistor is the phase current, applications using the high-frequency injection algorithm are generally high-power applications. High-frequency injection requires extracting the high-frequency response current and has high requirements for sampling accuracy. Therefore, the resistance value of the sampling resistor should not be too small. In the dual-resistor sampling mode, the sampling resistor string is on the lower bridge arm or the motor phase line. Under a large phase current, the sampling resistor generates serious heat due to excessive power consumption, and the board cost is high and it is prone to wiring difficulties due to the limitation of the board structure; while in the single-resistor sampling mode, the sampling resistor string is on the bus, and the average power consumption is much lower than that when it is connected in series on the lower bridge arm or the motor phase line. Therefore, the sampling resistor generates less heat. Under the condition of being compatible with both the power consumption of the sampling resistor and the sampling accuracy, the single-resistor sampling can be applied to higher-power applications compared with the dual-resistor sampling, and the wiring is simple and the cost is low. Therefore, it is necessary to develop a solution for the high-frequency injection algorithm using the single-resistor sampling mode; in the traditional single-resistor sampling mode for reconstructing the phase current according to the sector, since the sampling moment within one carrier period is not fixed, complex calculations are required to obtain the high-frequency current generated within one carrier period, and the calculation result has a large error, which affects the control effect.

[0045] In summary, how to optimize the current sampling method for the square-wave high-frequency signal injection scenario has become an urgent technical problem in this field.

[0046] The main solution of the embodiment of this application is: under the hardware topology with a single sampling resistor connected in series on the bus, configure the sampling window size and the sampling point movement size, and determine the sampling moment according to the sampling window size and the sampling point movement size; within each carrier period, select two-phase currents for current sampling according to the predefined sampling mode at the sampling moment.

[0047] Thus, by connecting a single sampling resistor in series on the bus and configuring the sampling window size and the sampling point movement size, two-phase current sampling at a fixed moment within each carrier period is realized. Compared with the traditional dual-resistor and three-resistor sampling modes, it can reduce the power consumption of the sampling resistor, reduce the heat generation problem, simplify the hardware layout at the same time, reduce the wiring difficulty and cost. At the same time, by fixing the sampling moment and selecting specific phase currents for sampling, the calculation process of the high-frequency response current can be simplified, the calculation error can be reduced, thereby optimizing the control effect and improving the motor control performance.

[0048] It should be noted that the execution subject of this embodiment can be a motor control system with data processing and program running functions.

[0049] Based on this, an embodiment of the present application provides a single-resistance sampling method. Refer to Figure 1 , Figure 1 which is a schematic flowchart of the first embodiment of the single-resistance sampling method of the present application.

[0050] In this embodiment, the single-resistance sampling method includes steps S10 to S20:

[0051] Step S10, under the hardware topology where a single sampling resistor is connected in series to the bus, configure the sampling window size and the sampling point movement size, and determine the sampling moment according to the sampling window size and the sampling point movement size;

[0052] Under the hardware topology structure where a single sampling resistor is connected in series to the bus, according to the operating parameters of the motor, such as the mos switch delay time, the switch oscillation time, etc., configure the start time, the duration, and the sampling moment of the sampling window. Among them, the sampling window refers to a specific time interval for current sampling within each carrier period, and the carrier period refers to a complete cycle of the carrier signal in the pulse width modulation (PWM) signal. The sampling point moves forward and backward based on the center position of the sampling window. Specifically, the setting of the sampling window needs to ensure that current sampling can be performed at a fixed moment within each carrier period, thereby avoiding problems such as complex calculation and large errors caused by non-fixed sampling moments.

[0053] In a feasible embodiment, before step S10, step A10 may further be included:

[0054] Step A10, connect a single sampling resistor in series to the DC bus, perform differential amplification on the voltage signal of the sampling resistor through an operational amplifier, and input the amplified voltage signal into the AD channel.

[0055] Before configuring the sampling window, first connect a single sampling resistor in series to the DC bus. Perform differential amplification processing on the voltage signal on the sampling resistor through an operational amplifier, and input the amplified voltage signal into the analog-to-digital converter (AD) channel.

[0056] In a feasible embodiment, step S10 may include steps S101 to S103:

[0057] Step S101, determine the sampling window size and the sampling point movement size according to the mos tube switch delay time and the switch oscillation time;

[0058] It should be noted that the switching delay time of the MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) refers to the time delay from when the MOS transistor receives a control signal to when it actually starts to conduct or cut off, and the switching oscillation time refers to the duration of the voltage or current fluctuation that may occur at the moment of switching of the MOS transistor.

[0059] The two parameters of the switching delay time and the switching oscillation time of the MOS transistor directly affect the setting of the sampling window size and the movement size of the sampling point, because the sampling window needs to avoid these unstable time periods to ensure the accuracy and reliability of the sampling signal.

[0060] Step S102: Use the edge-aligned timer counting mode to determine the position of the sampling window;

[0061] It should be noted that the edge-aligned timer counting mode is a timing control method that triggers the opening and closing of the sampling window at a specific edge (such as the rising edge or the falling edge) of the timer counter.

[0062] Using the edge-aligned timer counting mode to determine the position of the sampling window means that the timer counter operates according to the preset counting mode within each carrier period, and the start time and end time of the sampling window are determined by specific count values of the counter, ensuring the synchronization of the sampling window with the carrier period, thereby improving the accuracy and stability of sampling.

[0063] Step S103: Use the midpoint of the sampling window as the default sampling moment and move the sampling moment before and after the default sampling moment according to the movement size of the sampling point.

[0064] Using the midpoint of the sampling window as the default sampling moment, or moving the sampling moment before and after the default sampling moment according to the movement size of the sampling point, specifically needs to be determined according to the switching delay time and the switching oscillation time of the MOS transistor, which can minimize the influence of factors such as the switching delay and switching oscillation of the MOS transistor on the sampling signal, ensure that the sampling moment is within a relatively stable time period of the current signal, and thereby improve the accuracy and reliability of sampling.

[0065] Exemplarily, in a feasible implementation scenario, in the fixed sampling mode, the midpoint of the sampling window (i.e., the default sampling moment) is located before the underflow point of the timing counter. This setting can ensure that during the switching process of the MOS transistor, the sampling moment avoids possible current fluctuations and unstable states, thereby improving the stability and accuracy of sampling. Specifically, the timing counter counts down within each carrier period, and when the counter value reaches the preset underflow threshold, the sampling window closes. Setting the sampling moment before the underflow point can effectively avoid the influence of current fluctuations during the MOS transistor switching process on the sampling result.

[0066] In the dynamic sampling mode, the midpoint of the sampling window (i.e., the default sampling moment) is located after the carrier period reload count point. Within each carrier period, the sampling moment is fixed. At this time, according to the sector where the current voltage vector is located, two-phase currents are dynamically selected for sampling to adapt to different sampling requirements and further improve the flexibility and accuracy of sampling. Specifically, the timing counter counts up within each carrier period, and when the counter value reaches the preset reload threshold, the sampling window opens. Setting the sampling moment after the reload count point can dynamically select two-phase currents for sampling according to the sector where the current voltage vector is located, thereby improving the adaptability and accuracy of sampling.

[0067] Step S20, within each carrier period, select two-phase currents for current sampling at the sampling moment according to the predefined sampling mode.

[0068] It should be noted that the predefined sampling mode refers to the current sampling strategy preset according to the motor control requirements. The sampling mode can be a fixed sampling mode (for example, fixed sampling of phase b current and phase c current) or a dynamic sampling mode (for example, dynamically selecting two-phase currents according to the sector where the current voltage vector is located). Different sampling modes are applicable to different working conditions to meet the precise sampling requirements of high-frequency response currents.

[0069] Within each carrier period, according to the predefined sampling mode, select two-phase currents for current sampling at the sampling moment, where the sampling mode can be a fixed sampling mode or a dynamic sampling mode.

[0070] In this way, in the embodiment of the present application, by connecting a single sampling resistor in series on the bus and configuring the sampling window, two-phase current sampling at a fixed moment within each carrier period is realized. Compared with the traditional double-resistor and triple-resistor sampling modes, it can reduce the power consumption of the sampling resistor, reduce the heating problem, simplify the hardware layout at the same time, reduce the wiring difficulty and cost. At the same time, by fixing the sampling moment and selecting specific phase currents for sampling, the calculation process of high-frequency response currents can be simplified, the calculation error can be reduced, thereby optimizing the control effect and improving the motor control performance.

[0071] Based on the first embodiment of this application, in the second embodiment of this application, the same or similar content as in the above-mentioned first embodiment can be referred to the above introduction and will not be repeated hereinafter. On this basis, the sampling mode includes a dynamic sampling mode, and step S20 may include step S201:

[0072] Step S201, in the dynamic sampling mode, within each carrier period, at the sampling moment, two-phase currents are selected for sampling according to the sector where the current voltage vector is located.

[0073] The dynamic sampling mode is a flexible sampling strategy that dynamically adjusts the selection of sampled phase currents according to the sector where the voltage vector is located during motor operation. Within each carrier period, the sampling moment is fixed, and at this time, two-phase currents are dynamically selected for sampling according to the sector where the current voltage vector is located.

[0074] For example, when the current voltage vector is in sector one, phase a is sampled first and then phase c; when the current voltage vector is in sector two, phase b is sampled first and then phase c; when the current voltage vector is in sector three, phase b is sampled first and then phase a; when the current voltage vector is in sector four, phase c is sampled first and then phase a; when the current voltage vector is in sector five, phase c is sampled first and then phase b; when the current voltage vector is in sector six, phase a is sampled first and then phase b. This dynamic selection mechanism can flexibly adjust the sampling strategy according to the actual operating state of the motor, thereby improving the sampling accuracy and control effect.

[0075] Exemplarily, in the dynamic sampling mode, the hardware topology is as Figure 2 shown. The DC power supply Udc is used as the input. Through the bridge circuit composed of switching elements S1 - S6 and diodes VD1 - VD6, the currents ia, ib, and ic flowing through the output terminals A, B, and C are controlled to flow to the three-phase motor load N connected on the right. The figure also includes a current sampling circuit. The sampling resistor Rs is connected in series on the DC bus. The current flowing through the motor is detected through the sampling resistor Rs, and an operational amplifier is used to differentially amplify the voltage on the sampling resistor Rs. The amplified voltage signal is input into an AD channel for sampling. Sampling is performed twice within each carrier period, and it is determined which two phases the two sampling results correspond to according to the sector.

[0076] The switching waveform diagrams of each sector are as Figures 3(a) to 3(f)As shown, where Figure 3(a) shows the switching waveform diagrams of phases a, b, and c in Sector 1, Figure 3(b) shows the switching waveform diagrams of phases a, b, and c in Sector 2, Figure 3(c) shows the switching waveform diagrams of phases a, b, and c in Sector 3, Figure 3(d) shows the switching waveform diagrams of phases a, b, and c in Sector 4, Figure 3(e) shows the switching waveform diagrams of phases a, b, and c in Sector 5, Figure 3(f) shows the switching waveform diagrams of phases a, b, and c in Sector 6. Here, AR, BR, and CR respectively represent the reference signal waveforms of the currents in phases a, b, and c. AH and AL are respectively the complementary output signal waveforms of the upper and lower bridges of phase a after inserting the dead zone according to the reference signal AR. BL and BH are respectively the complementary output signal waveforms of the upper and lower bridges of phase b after inserting the dead zone according to the reference signal BR. CL and CH are respectively the complementary output signal waveforms of the upper and lower bridges of phase c after inserting the dead zone according to the reference signal CR. In this example, the counter adopts an edge-aligned upward counting method. After the carrier period reload counting point, two windows are fixedly opened for sampling the currents of two phases. Which two phases to sample specifically depends on the sector where the current output vector is located. In this example, when the output vector (i.e., the current voltage vector) is in Sector 1, phase a is sampled first and then phase c. When the output vector is in Sector 2, phase b is sampled first and then phase c. When the output vector is in Sector 3, phase b is sampled first and then phase a. When the output vector is in Sector 4, phase c is sampled first and then phase a. When the output vector is in Sector 5, phase c is sampled first and then phase b. When the output vector is in Sector 6, phase a is sampled first and then phase b. The two dashed lines respectively represent the moments of the first and second phase current samplings. The two sampling moments are defaulted to be at the middle moments of the two sampling windows. Since the turn-on delay, turn-off delay, switch oscillation time, etc. of different boards are all different, the time sizes of the two sampling windows and the positions of the sampling points within the windows can be set.

[0077] In a feasible embodiment, the sampling mode includes a fixed sampling mode and a sector reconstruction sampling mode. Step S20 may include steps S202 to S203:

[0078] Step S202, in the fixed sampling mode, within each carrier period, at the sampling moment, phase b current and phase c current are selected for current sampling;

[0079] In the fixed sampling mode, within each carrier period, phase b and phase c currents are fixedly selected for sampling. The advantage of this mode compared with the dynamic sampling mode is that it can prevent the problem of current distortion caused by sector switching and avoid the influence of current distortion on the operation effect of the high-frequency injection algorithm. By fixedly selecting phase b current and phase c current for sampling at the fixed sampling moment, the current signal can be stably obtained within each carrier period, thereby improving the stability and reliability of the control system.

[0080] In a feasible embodiment, the sampling instants include a first sampling instant and a second sampling instant, and step S202 may include steps S2021 to S2022:

[0081] Step S2021, in the fixed sampling mode, the minimum high-level time limit of the upper bridge of phase a is one sampling window time, the maximum high-level time limit of the upper bridge of phase a is the carrier period minus the sampling window time, the minimum high-level time limit of the upper bridge of phase b is two sampling window times; the maximum high-level time limit of phase c is the carrier period minus two sampling window times;

[0082] In the fixed sampling mode, the high-level time of each phase upper bridge is restricted to ensure the effectiveness of the sampling window and the stability of the sampling instants. The specific restrictions are as follows:

[0083] The minimum high-level time limit of the upper bridge of phase a is one sampling window time. This restriction ensures that within each carrier period, the high-level time of the upper bridge of phase a is long enough to prevent the sampling window from not being able to be normally opened due to too short a high-level time.

[0084] The maximum high-level time limit of the upper bridge of phase a is the carrier period minus the sampling window time. This restriction ensures that within each carrier period, the high-level time of the upper bridge of phase a will not be too long, thus leaving enough time for the opening of the sampling window.

[0085] The minimum high-level time limit of the upper bridge of phase b is two sampling window times. This restriction ensures that within each carrier period, the high-level time of the upper bridge of phase b is long enough to prevent the sampling window from not being able to be normally opened due to too short a high-level time.

[0086] The maximum high-level time limit of phase c is the carrier period minus two sampling window times. This restriction ensures that within each carrier period, the high-level time of the upper bridge of phase c will not be too long, thus leaving enough time for the opening of the sampling window.

[0087] These restriction conditions are set to ensure that within each carrier period, the sampling window can be normally opened and effective current sampling can be carried out, while avoiding sampling errors caused by too short or too long high-level times.

[0088] Step S2022, within each carrier period, phase b current is selected for current sampling at the first sampling instant, and phase c current is selected for current sampling at the second sampling instant.

[0089] Within each carrier period, the first sampling moment is earlier than the second sampling moment. At the first sampling moment, the b-phase current is selected for current sampling, and at the second sampling moment, the c-phase current is selected for current sampling. By sampling the b-phase current and the c-phase current at fixed sampling moments, it is possible to ensure stable acquisition of two-phase current signals within each carrier period, thereby improving the stability and reliability of the control system.

[0090] Step S203: Dynamically switch the fixed sampling mode to the sector reconstruction sampling mode according to the magnitude of the synthesized voltage vector, where the sector reconstruction sampling mode is to reconstruct the three-phase current according to the sector at dynamically changing sampling moments.

[0091] It should be noted that the magnitude of the synthesized voltage vector refers to the modulus of the equivalent voltage vector generated by space vector pulse width modulation (SVPWM) in motor control. When the magnitude of the synthesized voltage vector exceeds the preset threshold, it indicates that a higher voltage utilization rate is required (such as under large load or high-speed operation), and the sampling mode needs to be switched at this time.

[0092] Dynamically switch the fixed sampling mode to the sector reconstruction sampling mode according to the magnitude of the synthesized voltage vector to avoid the limitation of the maximum synthesized voltage vector magnitude by the fixed sampling mode. The sector reconstruction sampling mode refers to reconstructing the three-phase current for current sampling according to the sector at dynamically changing sampling moments. In the sector reconstruction sampling mode, two-phase currents are dynamically selected for sampling according to the current voltage vector sector, and the three-phase current is reconstructed through a complex algorithm.

[0093] In a feasible embodiment, step S203 may include steps S2031 to S2032:

[0094] Step S2031: Real-time obtain the magnitude of the synthesized voltage vector;

[0095] Step S2032: When the magnitude of the synthesized voltage vector exceeds the preset threshold, dynamically switch the fixed sampling mode to the sector reconstruction sampling mode, and when switching, it is necessary to ensure that the current sector is consistent with the sampling sector for collecting the b-phase current and the c-phase current in the sector reconstruction sampling mode.

[0096] During the operation of the motor control system, the synthetic voltage vector amplitude is continuously monitored. When the synthetic voltage vector amplitude obtained in real time exceeds the preset threshold, the current sampling mode is switched from the fixed sampling mode to the sector reconstruction sampling mode. The following conditions must be met during the switching: the current sector is consistent with the sampling sector for collecting the b-phase current and the c-phase current in the sector reconstruction sampling mode. That is, when switching the sampling mode, it is necessary to ensure that the sector where the current voltage vector is located matches the sector that can sample the b-phase current and the c-phase current in the sector reconstruction sampling mode. This matching ensures the smoothness and continuity of the sampling mode switching, avoiding sampling errors or control instability caused by sector mismatch.

[0097] For example, in fixed sampling mode, the hardware topology is as follows: Figure 4 As shown, a DC power supply Udc is used as the input. A bridge circuit composed of switching elements S1 to S6 and diodes VD1 to VD6 controls the currents ia, ib, and ic at the output terminals A, B, and C to flow to the three-phase motor load N connected to the right. The figure also includes a current sampling circuit. A sampling resistor Rs is connected in series to the DC bus. The current flowing through the motor is detected by the sampling resistor Rs, and the voltage across the sampling resistor Rs is differentially amplified using an operational amplifier. The amplified voltage signal is input to an AD channel for sampling. The b and c phase currents are sampled in a time-sharing manner. The first sampling window samples the b phase current, and the second sampling window samples the negative c phase current. The a phase current is calculated based on the b and c phase currents.

[0098] The switching waveforms of each sector are as follows: Figures 5(a) to 5(f)As shown, Figure 5(a) shows the switching waveform diagrams of phases a, b, and c in Sector 1, Figure 5(b) shows the switching waveform diagrams of phases a, b, and c in Sector 2, Figure 5(c) shows the switching waveform diagrams of phases a, b, and c in Sector 3, Figure 5(d) shows the switching waveform diagrams of phases a, b, and c in Sector 4, Figure 5(e) shows the switching waveform diagrams of phases a, b, and c in Sector 5, and Figure 5(f) shows the switching waveform diagrams of phases a, b, and c in Sector 6. Among them, AR, BR, and CR respectively represent the reference signal waveforms of the currents in phases a, b, and c. AH and AL are respectively the complementary output signal waveforms of the upper and lower bridges of phase a after inserting the dead zone according to the reference signal AR. BL and BH are respectively the complementary output signal waveforms of the upper and lower bridges of phase b after inserting the dead zone according to the reference signal BR. CL and CH are respectively the complementary output signal waveforms of the upper and lower bridges of phase c after inserting the dead zone according to the reference signal CR. In this example, the counter adopts an edge-aligned down-counting method. Two windows are fixedly opened before the underflow point of the carrier period to fixedly sample the currents in phases b and c. The two sampling windows are before the underflow point of the counter. This method can avoid current sampling errors caused by the charging current of the junction capacitance passing through the bus sampling resistor during the on process of the lower bridge within the sampling window. The two dashed lines respectively represent the sampling moments of the currents in phases b and c. The sampling moment is default at the middle moment of the two sampling windows. Since the turn-on delay, turn-off delay, switching oscillation time, etc. of different boards are different, the time sizes of the two sampling windows and the positions of the sampling points within the windows can be set. The high-frequency injection algorithm requires accurate sampling of high-frequency currents with small amplitudes. To ensure normal current sampling, the minimum high-level time of the upper bridge of phase a is limited to one sampling window time, and the maximum high-level time is limited to the carrier period minus the sampling window time. The minimum high-level time of the upper bridge of phase b is limited to twice the sampling window time. The maximum high-level time of phase c is limited to the carrier period minus twice the sampling window time. Therefore, at high currents, the sampling window needs to be opened larger to ensure normal sampling, resulting in a greater limitation on the voltage utilization rate, and further resulting in the torque and speed of the motor not being able to reach the maximum requirements. To solve the above problems, when the amplitude of the synthesized voltage vector is greater than a certain threshold, the fixed sampling mode is switched to the sector reconstruction sampling mode, and the voltage utilization rate is further improved. To ensure smooth switching between the two sampling modes, the switching condition not only needs to satisfy that the amplitude of the synthesized voltage vector is greater than a certain threshold, but also needs to be switched during the sector period corresponding to sampling the currents in phases b and c in the sector reconstruction sampling mode. The high-frequency injection algorithm only estimates the motor rotor position at zero speed and low speed. The program at medium and high speeds will switch to the back electromotive force estimator or the flux observer to estimate the motor rotor position. Generally, at zero speed and low speed, when reaching the maximum current required by the inverter, the voltage utilization rate is relatively low, far from reaching the voltage limit condition. Therefore, the sampling mode switch only occurs in the stage where the motor rotor position comes from the back electromotive force estimator or the flux observer, and both the sector reconstruction sampling mode and the fixed sampling mode can operate normally in this stage.

[0099] An embodiment of the present application provides an electronic device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the single-resistance sampling method in the first embodiment above.

[0100] Reference is made below Figure 6 to FIG., which shows a schematic structural diagram of an electronic device suitable for implementing the embodiments of the present application. The electronic device in the embodiments of the present application may include, but is not limited to, an entire machine device such as a multimedia interactive all-in-one machine, a touch all-in-one machine device, etc. Figure 6 The electronic device shown is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present application.

[0101] As Figure 6 shown, the electronic device may include a processing device 1001 (such as a central processing unit, a graphics processing unit, etc.), which may perform various appropriate actions and processes according to a program stored in the read-only memory 1002 or a program loaded from the storage device 1003 into the random access memory 1004. In the random access memory 1004, various programs and data required for the operation of the electronic device are also stored. The processing device 1001, the read-only memory 1002, and the random access memory 1004 are connected to each other through a bus 1005. The input / output interface 1006 is also connected to the bus. Generally, the following systems may be connected to the input / output interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 may allow the electronic device to communicate with other devices wirelessly or wiredly to exchange data. Although the figure shows an electronic device having various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be alternatively implemented or had.

[0102] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product that includes a computer program carried on a computer-readable medium, and the computer program contains program codes for executing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a read-only memory 1002. When the computer program is executed by a processing device 1001, the above-mentioned functions defined in the methods of the embodiments disclosed in the present application are executed.

[0103] The electronic device provided by the embodiment of the present application adopts the single-resistance sampling method in the above-mentioned embodiment, and can optimize the current sampling method for the square-wave high-frequency signal injection scenario. Compared with the prior art, the beneficial effects of the electronic device provided by the embodiment of the present application are the same as those of the single-resistance sampling method provided by the above-mentioned embodiment, and other technical features in the electronic device are the same as the features disclosed in the single-resistance sampling method of the previous embodiment, and will not be elaborated here.

[0104] It should be understood that the various parts disclosed in the embodiments of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0105] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, and all of them should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

[0106] The embodiment of the present application provides a computer-readable storage medium with computer-readable program instructions (i.e., computer programs) stored thereon, and the computer-readable program instructions are used to execute the single-resistance sampling method in the above-mentioned embodiment.

[0107] The computer-readable storage medium provided by the embodiments of the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or flash memory, optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program may be used by or in combination with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0108] The above computer-readable storage medium may be included in an electronic device; or it may exist separately without being assembled into the electronic device.

[0109] The above computer-readable storage medium carries one or more programs. When the one or more programs are executed by an electronic device, the electronic device is caused to: configure a sampling window size and a sampling point movement size under a hardware topology where a single sampling resistor is connected in series to a bus, and determine a sampling moment according to the sampling window size and the sampling point movement size; and select two-phase currents for current sampling according to a predefined sampling pattern at the sampling moment within each carrier period.

[0110] Computer program code for performing the operations of the embodiments of the present application may be written in one or more programming languages or combinations thereof. The above-mentioned programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (for example, by connecting through the Internet service provider via the Internet).

[0111] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0112] The modules described in the embodiments of the present application may be implemented in software or in hardware. Among them, the name of the module does not constitute a limitation to the unit itself in some cases.

[0113] The readable storage medium provided by the embodiments of the present application is a computer-readable storage medium. The computer-readable storage medium stores computer-readable program instructions (i.e., computer programs) for performing the above-mentioned single-resistor sampling method, and can optimize the current sampling method for the square-wave high-frequency signal injection scenario. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the embodiments of the present application are the same as those of the single-resistor sampling method provided by the above embodiments, and will not be elaborated here.

[0114] An embodiment of the present application also provides a computer program product, including a computer program, which implements the steps of the single-resistance sampling method as described above when executed by a processor.

[0115] The computer program product provided by the embodiment of the present application can mine effective information from the data generated by an information technology system. Compared with the prior art, the beneficial effects of the computer program product provided by the embodiment of the present application are the same as those of the single-resistance sampling method provided by the above embodiment, and will not be elaborated here.

[0116] The above are only partial embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structural transformation made by using the content of the specification and drawings of the present application under the technical concept of the present application, or any direct / indirect application in other related technical fields is included in the patent protection scope of the present application.

Claims

1. A single-resistor sampling method, characterized in that, The single-resistor sampling method includes: Under the hardware topology where a single sampling resistor is connected in series to the bus, configure the sampling window size and the sampling point movement size, and determine the sampling moment according to the sampling window size and the sampling point movement size; Within each carrier period, select two-phase currents for current sampling at the sampling moment according to a predefined sampling pattern.

2. The single-resistance sampling method according to claim 1, characterized in that The steps of configuring the sampling window size and the sampling point movement size, and determining the sampling moment according to the sampling window size and the sampling point movement size include: Determine the sampling window size and the sampling point movement size according to the MOS transistor switching delay time and the switching oscillation time; Adopt an edge-aligned timer counting mode to determine the position of the sampling window; Use the midpoint of the sampling window as the default sampling moment, and move the sampling moment forward and backward from the default sampling moment according to the sampling point movement size.

3. The single-resistance sampling method according to claim 1, wherein The sampling pattern includes a dynamic sampling pattern. The step of selecting two-phase currents for current sampling at the sampling moment within each carrier period according to a predefined sampling pattern includes: In the dynamic sampling pattern, within each carrier period, select two-phase currents for sampling at the sampling moment according to the sector where the current voltage vector is located.

4. The single resistor sampling method according to claim 1, wherein: The sampling pattern includes a fixed sampling pattern and a sector reconstruction sampling pattern. The step of selecting two-phase currents for current sampling at the sampling moment within each carrier period according to a predefined sampling pattern includes: In the fixed sampling pattern, within each carrier period, select the b-phase current and the c-phase current for current sampling at the sampling moment; Dynamically switch the fixed sampling pattern to the sector reconstruction sampling pattern according to the magnitude of the synthesized voltage vector, where the sector reconstruction sampling pattern is to reconstruct the three-phase current according to the sector at a dynamically changing sampling moment.

5. The single-resistance sampling method according to claim 4, wherein The steps of dynamically switching the fixed sampling pattern to the sector reconstruction sampling pattern according to the magnitude of the synthesized voltage vector include: Obtain the magnitude of the synthesized voltage vector in real time; When the magnitude of the synthesized voltage vector exceeds a preset threshold, dynamically switch the fixed sampling pattern to the sector reconstruction sampling pattern, and when switching, it is necessary to ensure that the current sector is consistent with the sampling sector for collecting the b-phase current and the c-phase current in the sector reconstruction sampling pattern.

6. The single-resistance sampling method according to claim 4, wherein, The sampling moment includes a first sampling moment and a second sampling moment. The step of selecting the b-phase current and the c-phase current for current sampling at the sampling moment within each carrier period in the fixed sampling pattern includes: In the fixed sampling pattern, the minimum high-level time limit of the a-phase upper bridge is one sampling window time, the maximum high-level time limit of the a-phase upper bridge is the carrier period minus the sampling window time, the minimum high-level time limit of the b-phase upper bridge is twice the sampling window time; the maximum high-level time limit of the c-phase is the carrier period minus twice the sampling window time; Within each carrier period, select the b-phase current for current sampling at the first sampling moment, and select the c-phase current for current sampling at the second sampling moment.

7. The single-resistance sampling method according to any one of claims 1 to 6, characterized in that Before the step of configuring the sampling window size and the sampling point movement size and determining the sampling moment according to the sampling window size and the sampling point movement size under the hardware topology where a single sampling resistor is connected in series to the bus, the method further includes: Connect a single sampling resistor in series to the DC bus, differentially amplify the voltage signal of the sampling resistor through an operational amplifier, and input the amplified voltage signal into the AD channel.

8. An electronic device, characterized in that, The electronic device includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, where the computer program is configured to implement the steps of the single-resistor sampling method as described in any one of claims 1 to 7.

9. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium, where the computer program, when executed by the processor, implements the steps of the single-resistor sampling method as described in any one of claims 1 to 7.

10. A computer program product, characterized in that, The computer program product includes a computer program, where the computer program, when executed by the processor, implements the steps of the single-resistor sampling method as described in any one of claims 1 to 7.

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