Fractional order differential analog-to-digital conversion device for neural peak potential acquisition

Abstract

The invention provides a fractional order differential analog-to-digital conversion device for neural peak potential acquisition. Firstly, a fractional order difference operator is designed to calculate any fractional order increment code, nerve peak potential sparsity can be more effectively utilized, the nerve peak potential compression ratio is remarkably improved, meanwhile, higher flexibility is achieved, the difference order is adjustable, and the method can adapt to more nerve peak potential collection application scenes. Secondly, a fractional order buffer module is designed, and any fractional order increment coding value can be generated in a simple and efficient mode. And finally, a serialized bit stream generator is designed, the fractional order incremental data collected by a plurality of parallel channels can be subjected to serialized packaging, the expandability is very high, the method can be suitable for multi-channel collection, and the method can be reliably connected with a subsequent synchronous clock wireless transmission system. The overhead and delay of synchronous-asynchronous interface coordination are avoided, and the nerve peak potential acquisition efficiency is further improved.

Description

Technical Field

[0001] The present invention belongs to the field of brain-computer interfaces, and in particular relates to a fractional-order difference analog-to-digital conversion device for neural spike acquisition. Background Art

[0002] As a disruptive technology in the interdisciplinary field of neuroscience and engineering, invasive brain-computer interfaces directly capture cortical electrical activities through implantable electrode arrays, and are reshaping the paradigm of rehabilitation for paralyzed patients and the treatment of neurological diseases. This technology can not only analyze motor intention signals to help spinal cord injury patients control robotic arms to complete grasping actions, but also intervene in abnormal brain rhythms through closed-loop electrical stimulation to provide precise treatment plans for Parkinson's disease tremor control. Its high spatio-temporal resolution signal decoding ability enables researchers to explore the neural circuit mechanisms of cognitive functions with single-neuron precision, accelerating the deep integration of brain-computer fusion theory and clinical translational research.

[0003] In invasive systems, neural spikes, as the core bioelectrical signals reflecting single-neuron discharges, the quality of their acquisition directly determines the decoding efficiency of brain-computer interfaces. Such signals are generated by the conduction of neuron action potentials and have characteristics of millivolt-level amplitude and millisecond-level duration. To accurately capture their discharge timing, microelectrode arrays need to penetrate the cortical layer to reach the vicinity of target neurons, and use high-impedance probes and adaptive threshold detection techniques to separate the action potential waveforms. Since the spike amplitude is easily affected by changes in cell membrane impedance, the system needs to integrate a dynamic gain compensation module and a multi-channel signal alignment algorithm to maintain coding consistency. However, this cell-level electrophysiological recording poses more stringent requirements on the morphology of the electrode tip, the stability of the tissue interface, and the suppression of signal crosstalk. Any distortion of the action potential waveform will lead to misinterpretation of the encoded information of neuron clusters.

[0004] Traditional acquisition architectures generally use Nyquist analog-to-digital converters (ADCs) to uniformly sample neural spikes over the full frequency band. This design faces severe energy efficiency challenges when implementing multi-channel high-density neural spike recordings. Since neural spikes, as the characteristic signals of single-neuron action potentials, their effective information is concentrated in the high-frequency band of 500 Hz - 8 kHz, and has sub-millisecond transient discharge characteristics. Using a fixed-rate broadband sampling strategy leads to signal sparsity problems - approximately 85% of the sampled data only records baseline noise. This not only causes inefficient use of analog-to-digital conversion resources, but also makes the power consumption density of the implanted system increase exponentially. When the number of microelectrode channels expands to 256, the static power consumption of the front-end sampling module may exceed the 20 mW safety threshold. The resulting local tissue heat deposition effect not only accelerates the impedance drift at the electrode-tissue interface, but may also affect the normal discharge patterns of neighboring neurons.

[0005] In order to break through the energy efficiency barrier, event-driven incremental coding analog-to-digital conversion technology (such as Delta-ADC) came into being. This solution innovatively introduces a dynamic threshold comparison mechanism, which triggers the quantization operation only when the signal change amplitude exceeds the preset threshold. This adaptive sampling strategy makes full use of the sparse characteristics of neural spikes in the time dimension, so that in scenarios such as Parkinson's disease monitoring and rhythm acquisition, the data throughput can be reduced by more than 82%. By constructing a multi-level differential coding tree, the system can simultaneously extract the amplitude mutation and slope change information of the signal, significantly reducing the power consumption of a single channel while maintaining the details of the action potential waveform, thereby extending the battery life of the implanted device.

[0006] However, while delta-ADCs can theoretically significantly improve acquisition efficiency, existing implementations still face several key issues. First, the incremental encoding method used by delta-ADCs is not always superior to traditional Nyquist sampling-based analog-to-digital converters. In certain application scenarios, particularly when signals are frequently changing or complex, the performance of delta-ADCs may actually be inferior to that of traditional successive approximation analog-to-digital converters. Furthermore, existing delta-ADCs generally use first-order difference calculations to generate first-order incremental encoding. However, first-order incremental encoding does not fully utilize the sparsity of neural spikes, resulting in limited compression effectiveness and inability to fully improve acquisition efficiency. Finally, most existing delta-ADC systems use asynchronous sampling, while wireless brain-computer interface systems typically employ synchronous digital processing. This results in significant overhead and latency in coordinating between system interfaces, further impacting overall performance and energy efficiency.

[0007] Therefore, to meet the demands of modern brain-computer interfaces for efficient acquisition, low-energy transmission, and high-quality signal recovery, it is crucial to design a new analog-to-digital converter that can effectively compress neural spike signals, improve acquisition efficiency, and adapt to wireless transmission requirements. This design not only needs to fully exploit the sparse nature of neural spikes, but also consider the system's power consumption, sampling efficiency, and compatibility with subsequent processing modules. Summary of the Invention

[0008] To overcome the problem of low efficiency in neural spike acquisition in the prior art, the present invention provides a fractional order difference analog-to-digital converter (FOD-ADC) for neural spike acquisition, which comprehensively improves the signal acquisition efficiency while maintaining the simplicity of the circuit topology. First, a fractional order difference operator is designed to calculate arbitrary fractional order delta encoding. Compared with the existing first-order delta encoding, it can not only make more effective use of the sparsity of neural spikes, significantly improve the neural spike compression ratio, but also has higher flexibility. The differential order is adjustable, which can adapt to more neural spike acquisition application scenarios. Second, a fractional order buffer module is designed to generate arbitrary fractional order delta encoding values in a simple and efficient manner. Finally, a serialized bitstream generator is designed to serialize and pack the fractional order delta data collected from multiple parallel channels. It not only has high scalability and can be applied to multi-channel acquisition, but also can be reliably docked with the subsequent synchronous clock wireless transmission system, avoiding the overhead and delay of synchronous-asynchronous interface coordination, and further improving the neural spike acquisition efficiency.

[0009] The fractional order difference analog-to-digital converter for neural spike acquisition involved in the present invention is composed of a multiplexer, a fractional order buffer module, a DAC controller, a DAC, a comparator, an increment counter, and a serialized bitstream generator. Among them, the multiplexer is controlled by the global clock CLK of the FOD-ADC ADC and switches the acquisition channel every clock cycle and stabilizes the current acquisition signal to support multi-channel parallel acquisition.

[0010] Furthermore, the fractional order buffer module is controlled by the global clock CLK of the FOD-ADC ADC and is responsible for storing and outputting the previous acquisition value of each channel to support the calculation of arbitrary fractional order delta encoding.

[0011] Even further, the DAC controller is used to read the previous acquisition value of the fractional order buffer module and generate a DAC control code in combination with the output of the increment counter.

[0012] Even further, the DAC reads the DAC control code output by the DAC controller, converts it into a signal to be compared. After multiple comparisons, the final DAC output is stored as the current acquisition value of the current channel in the fractional order buffer module.

[0013] Even further, the comparator is used to compare the signal to be acquired output by the multiplexer and the signal to be compared output by the DAC, and input the comparison result into the increment counter for increment counting.

[0014] Furthermore, the increment counter is controlled by the global clock CLK of the FOD-ADC. In each clock cycle, it reads the output result of the comparator, calculates the fractional-order increment of the current acquisition signal and the previous acquisition value, and transmits the increment to the DAC controller and the serialized bitstream generator. ADC Furthermore, the serialized bitstream generator is controlled by the global clock CLK of the FOD-ADC. In each clock cycle, it stores and converts the signal increment output by the increment counter into a bitstream, realizes data compression, and performs serialization and packaging to ensure the synchronization of data transmission, generating the final bitstream output by the FOD-ADC.

[0015] Furthermore, the serialized bitstream generator is controlled by the global clock CLK of the FOD-ADC. ADC In each clock cycle, it stores the signal increment output by the increment counter and converts it into a bitstream, realizes data compression, and performs serialization and packaging to ensure the synchronization of data transmission, generating the final bitstream output by the FOD-ADC.

[0016] The present invention provides a fractional-order differential analog-to-digital conversion device for neural spike acquisition. First, a fractional-order differential operator is designed to calculate any fractional-order increment coding, which can more effectively utilize the sparsity of neural spikes, significantly improve the compression ratio of neural spikes, and at the same time have higher flexibility. The differential order is adjustable and can adapt to more neural spike acquisition application scenarios. Secondly, a fractional-order buffer module is designed to generate any fractional-order increment coding value in a simple and efficient manner. Finally, a serialized bitstream generator is designed to serialize and package the fractional-order increment data collected by multiple parallel channels. It not only has high scalability and can be applied to multi-channel acquisition, but also can be reliably docked with the subsequent synchronous clock wireless transmission system, avoiding the overhead and delay of synchronous-asynchronous interface coordination, and further improving the neural spike acquisition efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0018] Figure 1 It is the overall architecture of the fractional-order differential analog-to-digital conversion device for neural spike acquisition proposed by the present invention;

[0019] Figure 2 It is a schematic diagram of the fractional-order buffer module;

[0020] Figure 3 It is a process diagram of the fractional-order buffer module;

[0021] Figure 4 It is a working principle diagram of the DAC controller;

[0022] Figure 5 It is the structure diagram of the DAC;

[0023] Figure 6 It is the structure diagram of the comparator;

[0024] Figure 7 It is the working principle diagram of the increment counter;

[0025] Figure 8 It is the example timing diagram of the increment counter;

[0026] Figure 9 It is the working principle diagram of the serialization bit stream generator;

[0027] Figure 10 They are the data results collected by two types of ADCs;

[0028] Figure 11 They are the results of normalizing the data collected by two types of ADCs;

[0029] Figure 12 They are the results of converting the data collected by two types of ADCs into bit streams;

[0030] [[ID=3_2]] Figure 13 It is to count the number of 0s and 1s in the bit stream and the total number of binary values. Detailed implementation manners

[0031] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system structures, technologies, etc. are proposed to thoroughly understand the embodiments of the present invention. However, those skilled in the art should clearly understand that the present invention can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present invention.

[0032] For an N-point neural spike time series signal X = [x1, x2, …, x N T , its f-order difference operator is defined as:

[0033]

[0034] where x i is the i-th element in the signal X, f is any fraction greater than 0, j! represents the factorial of j, Γ(·) represents the GAMMA function, D f is the f-order difference operator, and Y is the increment after the signal X is calculated by the f-order difference. Fractional-order difference involves infinite series, but in practical applications, due to the limited length of the neural spike signal, truncation is required. Therefore, it is truncated to terms. At this time, the f-order difference operator is defined as: ​

[0035]

[0036] As can be seen from the above formula, when calculating the f-th order increment of the currently acquired data point, the values of the previous g acquired data points need to be obtained.

[0037] Taking the 1.3-order difference operator as an example, its matrix form is:

[0038]

[0039] When calculating the 1.3-order difference increment value of the currently acquired neural spike data point, first, the values of the previous 2 acquired neural spike data points need to be obtained. After calculation, the 1.3-order minuend y i = 1.3x i-1 - 0.195x i-2 , and then the currently acquired data point x i is used to subtract y i to obtain the 1.3-order difference increment value z i = x i - y i = x i - (1.3x i-1 - 0.195x i-2 ).

[0040] Taking the 2.5-order difference operator as an example, its matrix form is:

[0041]

[0042] When calculating the 2.5-order difference increment value of the currently acquired neural spike data point, first, the values of the previous 3 acquired data points need to be obtained. After calculation, the 2.5-order minuend y i = 3.5x i-1 - 4.375x i-2 + 2.1875x i-3 , and then the currently acquired data point x i is used to subtract y i to obtain the 2.5-order difference increment value z i = x i - y i = x i - (3.5x i-1 - 4.375x i-2 + 2.1875x i-3 ).

[0043] To achieve f-th order increment acquisition, the present invention proposes a fractional-order difference analog-to-digital conversion device for neural spike acquisition, and the overall architecture is as shown in Figure 1As shown. The device consists of a multiplexer, a fractional buffer module, a DAC controller, a DAC, a comparator, an incremental counter, and a serialized bitstream generator.

[0044] The multiplexer is controlled by the global clock CLK of the FOD-ADC, switches the acquisition channels every clock cycle, and stabilizes the current acquisition signal after the channel switch, thus supporting multi-channel parallel acquisition. The multiplexer in this circuit adopts a standard time-division multiplexing structure, allowing the signals of L channels to share a physical channel for transmission, and occupying this channel sequentially within different CLK ADC cycles to achieve efficient data acquisition. ADC In the present invention, the time-division multiplexing structure is implemented through a multiplexer circuit, and the switch position is switched once every clock cycle to select different acquisition channels. After the multiplexer, the signal enters a sample-and-hold circuit, where a switched-capacitor circuit is used to physically hold the signal to ensure the stability of the signal during the acquisition process and guarantee the accuracy and reliability of subsequent acquisitions.

[0045] As shown, the fractional buffer module is controlled by the global clock CLK of the FOD-ADC, and is responsible for storing and outputting the values of the previous g acquisition data points of each channel to support the calculation of the f-order minuend, while avoiding the complexity of the traditional first-in-first-out buffer structure.

[0046] Specifically, this module consists of a storage matrix, a calculation matrix, and an adder tree. The storage matrix contains g rows and L columns. In each clock cycle, the data input from the DAC is input to the left side of the g-th row, and the data on the rightmost side of each row is shifted out of the storage matrix and input to the calculation matrix for calculation. At the same time, the data in the storage matrix undergoes a circular shift, that is, the data shifted out from the lower row is simultaneously shifted into the left side of the upper row. Except for the g-th row which can input data from the DAC, the data of other rows can only be shifted in from the corresponding lower row and cannot receive external input data from outside the module. It can be seen that this storage matrix forms a 1-input g-output structure. The design of this structure is aimed at cooperating with the calculation matrix to read data in a fixed form, thus avoiding increasing the circuit complexity and power consumption due to frequent switching of the readout ports. Figure 2 As shown, the fractional buffer module is controlled by the global clock CLK of the FOD-ADC, and is responsible for storing and outputting the values of the previous g acquisition data points of each channel to support the calculation of the f-order minuend, while avoiding the complexity of the traditional first-in-first-out buffer structure. ADC Specifically, this module consists of a storage matrix, a calculation matrix, and an adder tree. The storage matrix contains g rows and L columns. In each clock cycle, the data input from the DAC is input to the left side of the g-th row, and the data on the rightmost side of each row is shifted out of the storage matrix and input to the calculation matrix for calculation. At the same time, the data in the storage matrix undergoes a circular shift, that is, the data shifted out from the lower row is simultaneously shifted into the left side of the upper row. Except for the g-th row which can input data from the DAC, the data of other rows can only be shifted in from the corresponding lower row and cannot receive external input data from outside the module. It can be seen that this storage matrix forms a 1-input g-output structure. The design of this structure is aimed at cooperating with the calculation matrix to read data in a fixed form, thus avoiding increasing the circuit complexity and power consumption due to frequent switching of the readout ports.

[0047] Specifically, the module includes a storage matrix, a calculation matrix, and an adder tree. The storage matrix includes g rows and L columns. In each clock cycle, the data input from the DAC is input to the left of the g-th row, and the data on the rightmost side of each row is shifted out of the storage matrix and input to the calculation matrix for calculation. At the same time, the data in the storage matrix is circularly shifted, that is, the data shifted out from the lower row is simultaneously shifted into the left of the upper row. Except for the g-th row that can input data from the DAC, the data of other rows can only be shifted in from the corresponding lower row and cannot receive external input data from outside the module. Thus, this storage matrix forms a 1-input g-output structure. The design of this structure is intended to cooperate with the calculation matrix to read data in a fixed form, thereby avoiding increasing the circuit complexity and power consumption due to frequent switching of the readout ports.

[0048] The calculation matrix consists of a series of multiplication units, multiplies the data taken out from the storage matrix by the corresponding difference operator coefficients, and then inputs the data to the adder tree. The adder tree accumulates the data that has been multiplied by the coefficients to obtain the f-order minuend, and outputs the f-order minuend to the DAC controller to complete the task of the fractional buffer module.

[0049] The fractional-order buffer module is under the control of the global clock CLK of the FOD-ADC, and receives one data, performs one storage matrix read, one calculation, and one accumulation per cycle. Taking the 2.5-order FOD-ADC as an example, assuming the current is the i-th cycle and the first channel is to be collected, the collected value ADC is obtained. At this time, the 2.5-order minuend is Then the execution process is as shown below: Figure 3 Specifically:

[0050] Assume that the data stored in the current storage matrix is:

[0051]

[0052] Step 1: Take the first 3 collected values of the first channel from the 3 output terminals of the storage matrix and Input these three collected values into the calculation matrix for calculation operations respectively.

[0053] Step 2: Activate three multiplication units in the calculation matrix, numbered 1, 2, and 3 respectively. Input into multiplication unit 1, multiply it by the coefficient 2.1875 to get Input into multiplication unit 2, multiply it by the coefficient -4.375 to get Input into multiplication unit 3, multiply it by the coefficient 3.5 to get

[0054] Step 3: Input the results of the three multiplication units into the adder tree for accumulation to obtain the 2.5-order minuend

[0055] As Figure 4 shown, the DAC controller is used to read the f-order minuend output by the fractional-order buffer module, and combine it with the output of the increment counter to generate the DAC control code.

[0056] Specifically, under the control of the global clock CLK ADC , the FOD-ADC is to collect L channels in sequence, and collect the data of one channel per clock cycle. Assume that the first channel is to be collected currently, and the collected value is obtained. Then the working process of the DAC controller is as follows:

[0057] Step 1: Calculate the f-order minuend y through the fractional-order buffer module i .

[0058] Step 2: The increment counter inputs the increment value kΔ, and adds it to the f-order minuend yi Add them up to obtain the value y to be compared i +kΔ, where Δ is the minimum quantization unit of the FOD-ADC. The initial value of the increment value is 0Δ.

[0059] Step 3: Use the value y to be compared i +kΔ as the DAC control code, input it into the DAC, and convert it into the corresponding signal to be compared

[0060] Step 4: Input the signal to be compared into the comparator and compare it with the signal to be acquired. If the signal to be acquired is greater than the signal to be compared, the increment counter is incremented by 1Δ and the increment value becomes (k + 1)Δ; otherwise, it is decremented by 1Δ and the increment value becomes (k - 1)Δ.

[0061] Step 5: Loop through Steps 2 to 4 until the difference between the signal to be acquired and the signal to be compared is less than 1Δ. At this point, stop the loop and use the output of the DAC at this time as the acquisition value

[0062] Step 6: Store into the fractional-order buffer module and update the values of each row in the fractional-order buffer module

[0063] Subsequently, according to the above process, continue to acquire channels 2 to L. After acquiring the Lth channel, return to acquire the first channel

[0064] As Figure 5 shown, the DAC reads the DAC control code output by the DAC controller, converts it into the signal to be compared. After multiple comparisons, the final DAC output is used as the acquisition value of the current channel for this acquisition and stored in the fractional-order buffer module

[0065] Specifically, the DAC adopts an 8-bit capacitive voltage division structure, consisting of an array of 8 weighted capacitors. The sizes of the 8 capacitors are C, 2C, 4C, 8C, C, 2C, 4C, and 8C respectively. Before starting the conversion, close the Reset switch, ground the upper plates of all capacitors, and discharge the capacitor array. During the conversion phase, the Reset switch is opened, and the lower plates of the 8 binary weighted capacitors are connected to V ref or ground according to the control code. In addition, a 1.067C attenuation capacitor is connected to divide the capacitor array into two parts, thereby reducing the types of capacitors. The rightmost side of the DAC forms a voltage follower structure through an operational amplifier with negative feedback to isolate the capacitor array from the DAC output, reduce the output impedance, and enhance the load driving ability

[0066] As Figure 6As shown, the comparator is used to compare the signal to be acquired output by the multiplexer with the signal to be compared output by the DAC, and input the comparison result into the increment counter for increment counting. To reduce power consumption, a dynamic comparator is adopted in the FOD-ADC. The signal to be acquired is input from the V inp terminal, the signal to be compared is input from the V inn terminal, and the comparison result is output from the V out terminal.

[0067] As Figure 7 shown, the increment counter is controlled by the global clock CLK ADC of the FOD-ADC. In each clock cycle, it reads the output result of the comparator, calculates the fractional-order increment of the current acquired signal and the previous acquired value, and transfers the increment to the DAC controller and the serialized bitstream generator.

[0068] Specifically, the increment counter contains two modules. The sign register is composed of a 1-bit register circuit and is used to store the sign of the increment value. The 8-bit binary counter is composed of 8 D flip-flops and is used to store the magnitude of the increment value.

[0069] The working mode of the increment counter is as follows: The initial value of the increment value is 0Δ. When the output of the comparator is positive, it is determined that the signal to be acquired is greater than the signal to be compared, then the increment counter is incremented by 1Δ, the sign register is a positive sign, and the increment value becomes (0 + 1)Δ. When the output of the comparator is negative, it is determined that the signal to be acquired is less than the signal to be compared, then the increment counter is decremented by 1Δ, the sign register is a negative sign, and the increment value becomes (0 - 1)Δ. After each judgment, the increment value is output to the DAC controller to generate the DAC control code. The above judgment steps are looped until the difference between the signal to be acquired and the signal to be compared is less than 1Δ. At this time, the loop stops, and the sign in the sign register and the value in the 8-bit binary counter are concatenated to obtain the final fractional-order increment value.

[0070] As Figure 8 shown, it is an example timing diagram of the increment counter. In each period of the global clock CLK ADC , one channel is acquired respectively. In each clock cycle, the output of the multiplexer remains stable for the increment counter to perform analog-to-digital conversion.

[0071] In the first cycle, the increment counter performs analog-to-digital conversion on the CH1 channel. During the low level of CLK ADC , both the signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the signal to be compared for the CH1 channel. During the CLK ADCDuring the high level of, the increment counter starts the analog-to-digital conversion. The first comparison finds that the signal to be compared is less than the signal to be acquired. Therefore, after incrementing by 1Δ, the comparison continues. After incrementing by 1Δ six times, the difference between the signal to be compared and the signal to be acquired is less than 1Δ, and the conversion is completed at this time. At the beginning of the next CLK ADC cycle, the increment counter outputs the increment value of channel CH1, which is +6Δ.

[0072] In the second cycle, the increment counter performs analog-to-digital conversion on channel CH2. During the low level of CLK ADC , both the signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the signal to be compared for channel CH2. During the high level of CLK ADC , the increment counter starts the analog-to-digital conversion. The first comparison finds that the difference between the signal to be compared and the signal to be acquired is less than 1Δ, and the conversion is completed at this time. At the beginning of the next CLK ADC cycle, the increment counter outputs the increment value of channel CH2, which is 0Δ. At this time, it is considered that there is no increment between this acquisition and the previous acquisition of channel CH2.

[0073] In the third cycle, the increment counter performs analog-to-digital conversion on channel CH3. During the low level of CLK ADC , both the signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the signal to be compared for channel CH3. During the high level of CLK ADC , the increment counter starts the analog-to-digital conversion. The first comparison finds that the signal to be compared is greater than the signal to be acquired. Therefore, after decrementing by 1Δ, the comparison continues. After decrementing by 1Δ four times, the difference between the signal to be compared and the signal to be acquired is less than 1Δ, and the conversion is completed at this time. At the beginning of the next CLK ADC cycle, the increment counter outputs the increment value of channel CH3, which is -4Δ.

[0074] Other channels perform analog-to-digital conversion cycle by cycle according to the above conversion rules.

[0075] As Figure 9 shown, the serialized bitstream generator is controlled by the global clock CLK ADC of the FOD-ADC. In each clock cycle, it stores the signal increment output by the increment counter and converts it into a bitstream, realizes data compression, and performs serialization and packaging to ensure the synchronization of data transmission, and generates the final bitstream output by the FOD-ADC.

[0076] Specifically, in each global clock CLK ADCOn the rising edge of , the event determiner reads the increment value from the increment counter and determines whether it constitutes a fractional-order increment event. If the increment value is not 0Δ, indicating that the current acquired signal differs from the signal to be compared, it is determined to be a fractional-order increment event. At this point, the increment value is stored in the event register.

[0077] Each fractional increment event requires 9+log2L bits of storage space, where log2L bits are used to number the L channels, 1 bit is used for the increment sign, and 8 bits are used to store the increment amplitude. In addition, the system is equipped with a 9+log2L bit replica memory for parallel data caching and processing to improve data throughput efficiency.

[0078] After all L channels have completed one acquisition, a complete data acquisition frame is formed. After each acquisition frame is completed, the finite state machine generates an enable signal ENA and inputs it to the bitstream clock generator. The clock generator has a built-in ring oscillator and is dedicated to providing the clock CLK for bitstream packaging. BIT .

[0079] Then, the finite state machine scans the data in the event register and generates a BIT The clock is used to pack the bit stream and finally generate the FOD-ADC data bit stream.

[0080] The proposed FOD-ADC was compared with the state-of-the-art Nyquist ADC. The experimental setup was as follows: Anesthetized test animals were kept stationary in a cage. Electrodes were implanted in the head, eliciting two electrode channels. The same neural spike potential was present on each channel. Channel 1 was acquired using a Nyquist ADC, while channel 2 was acquired using a FOD-ADC. The FOD-ADC differential orders were set to 1.3, 2.5, and 3.7, respectively, for comprehensive comparison. The acquired data was transmitted via wired communication to a computer for analysis.

[0081] The data collected by the two ADCs are as follows: Figure 10 As shown, it can be seen that the data collected by the Nyquist ADC has a large fluctuation and a large amplitude, while the data collected by the FOD-ADC has a small fluctuation. The vast majority of the collected values are very close to 0, and only a few of them are relatively large, showing a high sparsity.

[0082] The data collected by the two ADCs are arranged in descending order and normalized. Figure 11 As shown in Figure 2, it can be seen that the data collected by FOD-ADC is significantly sparser than the data collected by Nyquist ADC.

[0083] The data collected by the two ADCs are converted into bit streams, such as Figure 12As shown, it can be seen that the bitstream of the FOD-ADC is sparser than that of the Nyquist ADC.

[0084] Convert the data collected by the two ADCs into bitstreams, and count the number of 0s and 1s in the bitstream as well as the total number of binary values, as Figure 13 shown. It can be concluded that the data volume of the 1.3-order FOD-ADC bitstream is 18.1% of the data volume of the Nyquist ADC bitstream, the data volume of the 2.5-order FOD-ADC bitstream is 24.6% of the data volume of the Nyquist ADC bitstream, and the data volume of the 3.7-order FOD-ADC bitstream is 18.2% of the data volume of the Nyquist ADC bitstream.

[0085] The above shows that the amount of data required to be transmitted by the FOD-ADC is significantly lower than that required by the Nyquist ADC, thus having higher energy efficiency.

[0086] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not imply the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0087] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the above division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiments can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of the present application. The specific working processes of the units and modules in the above system can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0088] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0089] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. A professional technician can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present invention.

[0090] In the embodiments provided by the present invention, it should be understood that the disclosed device / terminal device and method can be implemented in other ways. For example, the device / terminal device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in an electrical, mechanical or other form.

[0091] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0092] In addition, the functional units in each embodiment of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0093] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above-described embodiment methods of the present invention, it can also be completed by a computer program instructing relevant hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-described various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice within the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0094] The above-described embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention and should all be included in the protection scope of the present invention.

Claims

1. A fractional order difference analog-to-digital converter (FOD-ADC) for neural spike acquisition, characterized in that, The device consists of a multiplexer, a fractional buffer module, a DAC controller, a DAC, a comparator, an incremental counter, and a serialized bitstream generator, and is used to collect neural spike signals; The multiplexer, fractional buffer module, increment counter, and serialized bitstream generator are all controlled by the global clock CLK of the FOD-ADC ADC to implement the corresponding functions; The multiplexer switches the acquisition channels in each clock cycle and stabilizes the currently acquired signal to support multi-channel parallel acquisition; The fractional buffer module is responsible for storing and outputting the previous acquisition value of each channel to support the calculation of arbitrary fractional incremental encoding; The DAC controller is used to read the previous acquisition value of the fractional buffer module and generate a DAC control code in combination with the output of the incremental counter; The DAC reads the DAC control code output by the DAC controller, converts it into a signal to be compared, and after multiple comparisons, stores the final DAC output as the current acquisition value of the current channel in the fractional buffer module; The comparator is used to compare the signal to be acquired output by the multiplexer with the signal to be compared output by the DAC, and inputs the comparison result into the incremental counter for incremental counting; In each clock cycle, the incremental counter reads the output result of the comparator, calculates the fractional increment of the current acquisition signal and the previous acquisition value, and transmits the increment to the DAC controller and the serialized bitstream generator; In each clock cycle, the serialized bitstream generator stores and converts the signal increment output by the incremental counter into a bitstream to generate the final bitstream output by the FOD-ADC.

2. The fractional differential analog-to-digital conversion device according to claim 1, wherein the multiplexer adopts a time-division multiplexing structure, and the time-division multiplexing structure is implemented by a multiplexer circuit, and the switch position is switched once in each clock cycle to select different acquisition channels.

3. The fractional differential analog-to-digital conversion device according to claim 1, wherein the fractional buffer module consists of a storage matrix, a calculation matrix, and an adder tree; The storage matrix contains g rows and L columns; in each clock cycle, the data input from the DAC is input to the left side of the g-th row, and the data on the rightmost side of each row is removed from the storage matrix and input to the calculation matrix for calculation; the data in the storage matrix moves circularly; The calculation matrix multiplies the data taken out from the storage matrix by the corresponding differential operator coefficient, and then inputs it into the adder tree; The adder tree accumulates the data that has been multiplied by the coefficient to obtain the f-th minuend, and outputs the f-th minuend to the DAC controller to complete the task of the fractional buffer module.

4. The fractional differential analog-to-digital conversion device according to claim 1, wherein the working process of the DAC controller is as follows: First step, the minuend y of order f is calculated through the fractional-order buffer module i ; Step 2: The increment counter inputs an increment value kΔ and adds it to the f-th minuend y i to obtain a value y i + kΔ, where Δ is the minimum quantization unit of the FOD-ADC; the initial value of the increment value is 0Δ; Step 3: Use the value y to be compared i +kΔ as the DAC control code and input it into the DAC to convert it into the corresponding signal to be compared; Step 4: Input the signal to be compared into the comparator to compare with the signal to be acquired; if the signal to be acquired is greater than the signal to be compared, the incremental counter is incremented by 1Δ, and the increment value becomes (k + 1)Δ, otherwise it is decremented by 1Δ, and the increment value becomes (k - 1)Δ; Step 5: Loop through Steps 2 to 4 until the difference between the signal to be acquired and the signal to be compared is less than 1Δ. At this point, stop the loop and use the output of the DAC at this time as the acquired value Step 6: Store in the fractional buffer module and update the value of each row in the fractional buffer module.

5. The fractional differential analog-to-digital conversion device according to claim 1, wherein the incremental counter includes a sign register and an 8-bit binary counter. The sign register is composed of a 1-bit register circuit and is used to store the sign of the increment value. The 8-bit binary counter is composed of 8 D flip-flops and is used to store the amplitude of the increment value.

6. The fractional-order difference analog-to-digital conversion device according to claim 5, wherein the working mode of the increment counter is as follows: the initial value of the increment value is 0Δ; when the output of the comparator is positive, it is determined that the signal to be acquired is greater than the signal to be compared, then the increment counter is incremented by 1Δ, the sign register is a positive sign, and the increment value becomes (0 + 1)Δ; when the output of the comparator is negative, it is determined that the signal to be acquired is less than the signal to be compared, then the increment counter is decremented by 1Δ, the sign register is a negative sign, and the increment value becomes (0 - 1)Δ; after each judgment, the increment value is output to the DAC controller to generate a DAC control code; the above judgment steps are cycled until the difference between the signal to be acquired and the signal to be compared is less than 1Δ, at which time the loop is stopped, and the sign in the sign register and the value in the 8-bit binary counter are concatenated to obtain the final fractional-order increment value.

7. The fractional-order difference analog-to-digital conversion device according to claim 1, wherein the serialized bitstream generator is composed of an event judge, an event register, a finite state machine, a bitstream clock generator, and a bitstream packer.

8. The fractional-order difference analog-to-digital conversion device according to claim 7, wherein the serialization bit stream generator reads the increment value from the increment counter by the event judge at the rising edge of each global clock CLK ADC and judges whether the increment value forms a fractional-order increment event; When the increment value is not 0Δ, it indicates that the currently acquired signal is different from the signal to be compared, and thus it can be determined as a fractional-order increment event; at this time, the increment value is stored in the event register. After all L channels complete one acquisition, a complete data acquisition frame is formed. Upon completion of each acquisition frame, the finite state machine generates an enable signal ENA and inputs it to the bitstream clock generator; this clock generator incorporates a ring oscillator dedicated to providing the clock CLK for bitstream packaging BIT ; Subsequently, the finite state machine scans the data in the event register and performs bitstream packing based on the CLK BIT clock to finally generate the FOD-ADC data bitstream.

9. The fractional-order difference analog-to-digital conversion device according to claim 1, wherein the DAC is implemented by an 8-bit capacitive voltage division structure; the comparator is implemented by a dynamic comparator.

10. The fractional-order difference analog-to-digital conversion device according to claim 1, wherein the calculation matrix is composed of a series of multiplication units.

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