Column memory circuit, chip, image sensor, and imaging apparatus

Abstract

The invention provides a column memory circuit, a chip, an image sensor and an imaging apparatus. The column memory circuit comprises M * N memory bank modules, N read-out modules and a data transmission module, and a correlated double-sampling module of the column memory circuit is arranged in the read-out module; the first end of the memory bank module receives a first data signal, the second end of the memory bank module is coupled with the first end of the reading module corresponding to the memory bank module, and the second end of the reading module is coupled with the data transmission module; the memory bank module converts a received first data signal into a second data signal, the reading module performs correlated double sampling processing on the second data signal through the correlated double sampling module to obtain a third data signal, and the data transmission module outputs the third data signal. According to the column memory circuit, the area of the column memory circuit can be obviously reduced, the circuit performance can be well ensured, and the cost of an image sensor can be obviously reduced by adopting the column memory circuit provided by the invention.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing, and particularly to a column memory circuit, a chip, an image sensor, and an imaging device. Background Art

[0002] An image sensor generally includes components such as a pixel array, an analog-to-digital converter, and a column memory circuit. An image sensor is a device that converts an optical image into an electrical signal. Exemplarily, please refer to Figure 1 , which schematically shows the flow diagram of data signals during the imaging process. As Figure 1 can be seen, the pixel unit 111 of the pixel array 110 ( Figure 1 not shown in the figure, see Figure 7 below) is responsible for converting the collected image optical signal into a voltage signal and outputting the voltage signal to the analog-to-digital converter 120 (Analog-to-digital Converter, ADC). The analog-to-digital converter 120 is responsible for comparing the received voltage signal with a ramp signal and generating a pulse signal when the two signals are equal; the column memory (Column) circuit 130 latches the data of the counter when receiving the pulse signal, and serially outputs the data to the image processor (Image Signal Processing, ISP) 150 after processing the data in a certain manner. The image processor 150 extracts and optimizes the received image data (such as color correction, Gamma correction, etc.) to obtain an image that can be displayed, stored, and / or further processed, and outputs it through the interface (Interface) circuit 160.

[0003] It has been found through research that the current column memory circuit has a large area and high power consumption. Although it has been well applied in high-performance image sensors, it is difficult to be applied in low-cost image sensors.

[0004] It should be noted that the information disclosed in the background art part of this invention is only intended to deepen the understanding of the general background art of the present invention, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art known to those skilled in the art. Summary of the Invention

[0005] Aiming at the technical problems of the column memory circuit of the image sensor in the prior art, such as large area and high power consumption, the present invention provides a column memory circuit, a chip, an image sensor, and an imaging device. The present invention can significantly reduce the area of the column memory circuit and well ensure the circuit performance. By using the column memory circuit provided by the present invention, the cost of the image sensor can be significantly reduced.

[0006] To achieve the above object, the present invention is implemented through the following technical solutions: A column memory circuit for an image sensor, the column memory circuit includes M×N memory bank modules, N readout modules, and a data transmission module, and the correlated double sampling module of the column memory circuit is arranged in the readout module; a first end of the memory bank module is configured to receive a first data signal, a second end of the memory bank module is coupled to a first end of the corresponding readout module, a second end of the readout module is coupled to the data transmission module, and M≥2;

[0007] The memory bank module is configured to convert the received first data signal into a second data signal, the readout module is configured to perform correlated double sampling processing on the second data signal through the correlated double sampling module to obtain a third data signal, and the data transmission module is configured to output the third data signal.

[0008] Optionally, the correlated double sampling module includes a plurality of first transistors.

[0009] Optionally, each memory bank module includes a first latch, a transcoding module, and a buffer module that are sequentially coupled, the readout module further includes a second latch, a trigger, and a multiplexer, and the second latch, the correlated double sampling module, the trigger, and the multiplexer are sequentially coupled;

[0010] The first latch is configured to latch the first data signal when receiving a first control signal of the image sensor, and send the latched first data signal to the transcoding module; the transcoding module is configured to transcode the first data signal to obtain a fourth data signal; the buffer module is configured to buffer the fourth data signal to obtain a first set of the second data signals for sending to the second latch and buffer a second set of the second data signals for sending to the correlated double sampling module after obtaining the first set of the second data signals;

[0011] The second latch is configured to latch the first set of the second data signals when receiving a second control signal; the correlated double sampling module is configured to perform correlated double sampling processing on the second set of the second data signals according to the first set of the second data signals to obtain the third data signal, the trigger sends the third data signal to the multiplexer when receiving a third control signal of the image sensor, and the multiplexer is configured to select a corresponding third data signal according to a fourth control signal of the image sensor and send it to the data transmission module.

[0012] Optionally, the first data signal adopts a Gray code encoding method, and the fourth data signal adopts a binary encoding method.

[0013] Optionally, the trigger includes a D flip-flop.

[0014] Optionally, each of the memory bank modules includes a first latch and a buffer module connected in sequence, and the readout module further includes a transcoding module, a second latch, a trigger, and a multiplexer; the transcoding module, the second latch, the correlated double sampling module, the trigger, and the multiplexer are connected in sequence;

[0015] The first latch is configured to latch the first data signal when receiving a first control signal of the image sensor and send the latched first data signal to the buffer module, and the buffer module is configured to buffer the first data signal to obtain the second data signal and send the second data signal to the transcoding module;

[0016] The transcoding module is configured to transcode the second data signal to obtain a first set of fifth data signals for sending to the second latch, and after obtaining the first set of fifth data signals, transcode the subsequent received second data signals to obtain a second set of fifth data signals for sending to the correlated double sampling module; the second latch is configured to latch the first set of fifth data signals when receiving a second control signal; the correlated double sampling module is configured to perform correlated double sampling processing according to the first set of fifth data signals and the second set of fifth data signals to obtain the third data signal, and the trigger sends the third data signal to the multiplexer when receiving a third control signal of the image sensor, and the multiplexer is configured to select a corresponding third data signal according to a fourth control signal of the image sensor and send it to the data transmission module.

[0017] Optionally, the transcoding module includes a plurality of second transistors.

[0018] To achieve the above object, the present invention also provides a chip for an image sensor, and the above-mentioned column memory circuit is integrated on the chip.

[0019] To achieve the above object, the present invention also provides an image sensor, and the image sensor includes the above-mentioned column memory circuit or the above-mentioned chip.

[0020] To achieve the above object, the present invention also provides an imaging device, and the imaging device includes the above-mentioned column memory circuit, or the above-mentioned chip, or the above-mentioned image sensor.

[0021] Compared with the prior art, a column memory circuit, a chip, an image sensor, and an imaging device provided by the present invention have the following advantages:

[0022] The column memory circuit provided by the present invention abandons the design method in the prior art of setting the correlated double sampling module in the memory bank module, and adopts the design method of setting the correlated double sampling module in the readout module. Based on the objective fact that the number of the readout modules is much smaller than the number of the memory bank modules, the number of the correlated double sampling modules can be significantly reduced, which not only saves costs, but also reduces the circuit area occupied by the correlated double sampling modules. Furthermore, the area of the column memory circuit can be significantly reduced, and the circuit performance can be well guaranteed. By adopting the column memory circuit provided by the present invention, the cost of the image sensor can be significantly reduced, and the column memory circuit provided by the present invention can be well applied to low-cost image sensors.

[0023] Since the chip for an image sensor, the image sensor and the imaging device provided by the present invention belong to the same inventive concept as the column memory circuit provided by the present invention, therefore, the chip for an image sensor, the image sensor and the imaging device provided by the present invention at least have all the advantages of the column memory circuit provided by the present invention. For the detailed content of the beneficial effects of the chip for an image sensor, the image sensor and the imaging device provided by the present invention, please refer to the relevant description of the beneficial effects of the column memory circuit provided by the present invention above, and will not be elaborated herein one by one. Description of the Drawings

[0024] Figure 1 It is a schematic diagram of the data signal flow direction during the imaging process;

[0025] Figure 2 It is a schematic diagram of the data signal flow direction in the column memory circuit of the image sensor;

[0026] Figure 3 It is a schematic diagram of the topological structure of the column memory circuit of the image sensor in the prior art;

[0027] Figure 4 It is a schematic block diagram of the column memory circuit provided by the present invention;

[0028] Figure 5 It is a schematic diagram of the topological structure of the column memory circuit provided by the first embodiment of the present invention;

[0029] Figure 6 It is a schematic diagram of the topological structure of the column memory circuit provided by the second embodiment of the present invention;

[0030] Figure 7 It is a schematic block diagram of the imaging device provided by the present invention;

[0031] Among them, the reference numerals are as follows:

[0032] Image sensor - 100, pixel array - 110, pixel unit - 111, analog-to-digital converter - 120, column memory circuits - 130, 140, image processor - 150, interface circuit - 160;

[0033] Bank modules - Bank0, Bank1, Bank2, Bank3, 130A, 141, 141A, 141B, readout modules - R01, R23, 130B, 142, 142A, 142B, 142C, 142D, data transmission module - 170;

[0034] First latches - 131, 141A1, 141B1, transcoding modules - 132, 141A2, 142B1, second latches - 133, 142A1, 142B2, correlated double sampling modules - 134, 143, buffer modules - 135, 141A3, 141B2, flip-flops - 136, 142A2, 142B3, multiplexers - 137, 142A3, 142B4;

[0035] Gray code data - GC, comparator data - CMP, black level signal - BLK_EN, adjacent readout module output signal terminal - GBL;

[0036] First data signal - D1, second data signal - D2, third data signal - D3, fourth data signal - D4, fifth data signal - D5;

[0037] First control signal - T1, second control signal - T2, third control signal - T3, fourth control signal - T4;

[0038] Application program - 200. Detailed implementation

[0039] The following further elaborates on a column memory circuit, a chip, an image sensor, and an imaging device proposed by the present invention in conjunction with the accompanying drawings. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention. In order to make the objectives, features, and advantages of the present invention more obvious and understandable, please refer to the accompanying drawings. It should be noted that the structures, scales, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Any modification of the structure, change in the proportional relationship, or adjustment of the size, in the case of being the same or similar to the effects that the present invention can produce and the objectives that can be achieved, should still fall within the scope covered by the technical content disclosed by the present invention. The specific design features of the present invention disclosed herein, including, for example, specific dimensions, directions, positions, and shapes, will be partially determined by the specific application and usage environment. Also, in the embodiments described below, sometimes the same reference numerals are used between different drawings to represent the same part or parts having the same function, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings. Additionally, if the methods described herein include a series of steps, and the order of these steps presented herein is not necessarily the only order in which these steps can be executed, and some of the described steps can be omitted and / or some other steps not described herein can be added to the method.

[0040] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variation thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element. The singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", and in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features.

[0041] It should be understood that when an element is referred to as being "connected", "connected to", "coupled to" another element, it can be directly connected to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly connected to" another element, there are no intervening elements.

[0042] To facilitate a better understanding and elaboration of the present invention, before describing the specific embodiments of the column memory circuit, image sensor and imaging device provided by the present invention, the main research process of the present invention will be described first.

[0043] First, please refer to Figure 2 , which schematically shows the flow diagram of the data signal in the column memory circuit of the image sensor. As Figure 2 shown, Figure 2 taking the column memory circuit including four bank modules Bank0, Bank1, Bank2 and Bank3, two readout modules R01 and R23, and a data io module 170 as an example, and the bank modules Bank0 and Bank1 share the readout module R01, and the bank modules Bank2 and Bank3 share the readout module R23, that is, every two bank modules share a readout module. The processing flow of the column memory circuit for the data signal is roughly as follows: from the analog-to-digital converter 120 ( Figure 2 not shown in Figure 1The Gray code data GC (understood) and the comparator data CMP from the timing control circuit ( Figure 2 not shown in the figure) enter the memory bank modules Bank0, Bank1, Bank2, and Bank3 from the outside. The memory bank modules Bank0 and Bank1 send the processed data to the corresponding readout modules R01 and then transmit it to the data transmission module 170. The memory bank modules Bank2 and Bank3 first send the processed data to the corresponding readout modules R23 and then send it to the data transmission module 170 through the readout module R01. All the readout modules R01 and R23 together form the shift readout function. The data transmission module 170 receives the data processed by the readout modules R01 and R23 and outputs the data from the column memory circuit 130.

[0044] Please refer to Figure 3 , Figure 3 which is a schematic diagram of the topology of the column memory circuit of the image processor in the prior art. As Figure 3 shown, in this example, the column memory circuit 130 includes M×N memory bank modules ( Figure 3 schematically shown as the i-th memory bank module 130A, 1 ≤ i ≤ (M×N)), N readout modules ( Figure 3 schematically shown as the j-th readout module 130B, 1 ≤ j ≤ N) and 1 data transmission module 170. The processing process of the data signal is roughly as follows: At the falling edge of the comparator data CMP signal, the Gray code data GC is latched in the first latch 131. The transcoding module 132 converts the latched Gray code data GC into binary data BC. The second latch 133 stores the black level signal BLK_EN of the image sensor and, together with the correlated double sampling module (CDS) 134, implements the CDS function. The buffer module 135 sends the data signal BIT_OUT that has completed CDS from the memory bank module 130A to the corresponding readout module 130B. As mentioned above, the N readout modules together form the shift register function. Further, the readout module 130A first sends out the data in the memory bank module 130A and the memory bank module ( Figure 3 not shown in the figure) that shares the readout module 130A with the memory bank module 130A ( Figure 2 such as the memory bank modules bank0 and bank1 that share the readout module R01 in the figure) through the flip-flop 136 (such as a D-type flip-flop, DFF) and the multiplexer 137. Immediately afterwards, the multiplexer 137 is switched to the output signal terminal GBL of the adjacent readout module, and the readout module 130B sends the data of other memory bank modules through the multiplexer 137 (such as Figure 2The data of memory bank modules bank2 and bank3 of the shared read module R23 are first sent to the read module R23, and then transmitted to the read module R01 for output, and then output from the column memory circuit 130 through the data transmission module 170.

[0045] It should be noted that only the parts of the column memory circuit related to the present invention are described in this article. For more detailed content of the column memory circuit not mentioned in this article, please refer to the relevant technologies well-known to those skilled in the art for adaptive understanding.

[0046] From Figure 3 It can be seen that the column memory circuit in the prior art generally includes a data transmission module 170, N read modules 130B, and M×N memory bank modules 130A (the specific values of M and N are related to the resolution of the image sensor), and most functions are implemented in the memory bank module 130A. After a large amount of research, the inventor found that the transcoding module 132 and complex function circuits such as the related double sampling module 134 are usually composed of a large number of transistors. The complex functions and a large number of memory bank modules 130A lead to a large circuit area occupied by the column memory circuit 130, and it is difficult to be applied to low-cost image sensor products.

[0047] Based on the above research, the core idea of the present invention is to provide a column memory circuit, an image sensor, and an imaging device. The present invention can significantly reduce the area of the column memory circuit and well ensure the circuit performance. By using the column memory circuit provided by the present invention, the cost of the image sensor can be significantly reduced.

[0048] It should be noted that the column memory circuit and chip for the image sensor provided by the present invention can be applied to the image sensor and imaging device provided by the present invention. The image sensor provided by the present invention can be applied to the imaging device provided by the present invention. It should be understood that the term "imaging device" or "of the imaging device" or other similar terms used herein include general imaging devices, such as, for example, but not limited to, cameras, video cameras, mobile phones, tablet computers, learning machines, and medical imaging devices having image sensors.

[0049] To achieve the above idea, the present invention provides a column memory circuit. Exemplarily, please refer to Figure 4 , which schematically shows the block structure diagram of the column memory circuit provided by the present invention. From Figure 4It can be seen that the column memory circuit 140 provided by the present invention includes M×N memory bank modules 141, N readout modules 142, and a data transmission module 170. The correlated double sampling module 143 of the column memory circuit 140 is disposed in the readout module 142. The first end of the memory bank module 141 is configured to receive a first data signal D1. The second end of the memory bank module 141 is coupled to the first end of the corresponding readout module 142. The second end of the readout module 142 is coupled to the data transmission module 170, where M≥2. Further, the memory bank module 141 is configured to convert the received first data signal D1 into a second data signal D2. The readout module 142 is configured to perform correlated double sampling processing on the second data signal D2 through the correlated double sampling module 143 to obtain a third data signal D3. The data transmission module 170 is configured to output the third data signal D3.

[0050] Thus, for the column memory circuit provided by the present invention, the design method of disposing the correlated double sampling module in the memory bank module in the prior art is abandoned. Instead, the design method of disposing the correlated double sampling module 143 in the readout module 142 is adopted. By making full use of the objective fact that the number of the readout modules 142 is much smaller than the number of the memory bank modules 141, the number of the correlated double sampling modules 143 can be significantly reduced, which not only saves costs but also reduces the circuit area occupied by the correlated double sampling module 143. Furthermore, the area of the column memory circuit can be significantly reduced, and the circuit performance can be well guaranteed. By using the column memory circuit provided by the present invention, the cost of the image sensor can be significantly reduced, and the column memory circuit provided by the present invention can be well applied to low-cost image sensors.

[0051] Specifically, compared with the design method of disposing the correlated double sampling module in the memory bank module in the prior art, for the column memory circuit provided by the present invention, by disposing the correlated double sampling module 143 in the readout module 142, (M - 1)×N correlated double sampling modules 143 can be saved.

[0052] Preferably, in some exemplary embodiments, the correlated double sampling module 143 includes a plurality of first transistors ( Figure 4(not shown in the figure). Thus, the design method of implementing the relevant double sampling module 143 with a plurality of first transistors is not only easy to implement, but also the transistors are inexpensive and easy to obtain. It should be noted that those skilled in the art should be able to understand that the above implementation of the relevant double sampling module 143 with the first transistor is only an exemplary illustration of the preferred implementation manner, rather than a limitation of the present invention. The present invention does not make any limitation on the specific implementation manner of the relevant double sampling module 143. For more detailed content about the relevant double sampling module 143, please refer to the relevant technologies well-known to those skilled in the art. Due to space limitations, this will not be elaborated in detail herein.

[0053] Exemplarily, taking the relevant double sampling module 143 including P first transistors as an example, the total number of first transistors required for the design method of arranging the relevant double sampling module in the memory bank module in the prior art is M×N×P, while only N×P first transistors are required for the column memory circuit provided by the present invention. Thus, it can be seen that compared with the prior art, the present invention can save (M - 1)×N×P transistors.

[0054] Exemplarily, please refer to Figure 5 , which schematically shows the topological structure diagram of the column memory circuit provided by the first embodiment of the present invention. Figure 5 In the figure, the i-th memory bank module 141A and the j-th readout module 142A are taken as examples. From Figure 5It can be seen that in the column memory circuit provided by the first embodiment of the present invention, each memory bank module 141A includes a first latch 141A1, a transcoding module 141A2, and a buffer module 141A3 that are sequentially coupled. Each read module 142A further includes a second latch 142A1, a flip-flop 142A2, and a multiplexer 142A3, and the second latch 142A1, the correlated double sampling module 143, the flip-flop 142A2, and the multiplexer 142A3 are sequentially coupled. Further, the first latch 141A1 is configured to latch the first data signal D1 (such as a voltage signal in Gray code format, which represents the output voltage value of a pixel) when receiving the first control signal T1 (such as comparator data CMP) of the image sensor, and send the latched first data signal D1 to the transcoding module 141A2; the transcoding module 141A2 is configured to transcode the first data signal D1 to obtain a fourth data signal D4 (such as a voltage signal in binary format); the buffer module 135 is configured to buffer the fourth data signal D4 to obtain a first set of the second data signals D21 (voltage signals in binary format, which represent the voltage value of the black level signal) for sending to the second latch, and buffer a second set of the second data signals D22 (voltage signals in binary format, which represent the voltage value of an image pixel) for sending to the correlated double sampling module 143 after obtaining the first set of the second data signals D21; the second latch 142A1 is configured to latch the first set of the second data signals D21 when receiving a second control signal T2 (such as a black level storage signal); the correlated double sampling module 143 is configured to perform correlated double sampling processing based on the first set of the second data signals D21 and the second set of the second data signals D22 to obtain the third data signal D3 (voltage signals in binary format), the flip-flop 142A2 sends the third data signal D3 to the multiplexer 142A3 when receiving the third control signal T3 (such as a read clock signal) of the image sensor, and the multiplexer 142A3 is configured to select the corresponding third data signal D3 according to the fourth control signal T4 (such as a memory bank module selection signal) of the image sensor and send it to the data transmission module 170.

[0055] The column memory circuit provided by the first embodiment of the present invention, wherein the memory bank module 141A includes a first latch 141A1, a transcoding module 141A2, and a buffer module 141A3. Thus, the stability of the first data signal D1 can be ensured by the first latch 141A1. The first data signal D1 is converted into the fourth data signal D4 by the transcoding module 141A2, which lays a solid foundation for the efficient processing of the data signal by the readout module 142A. The fourth data signal D4 is buffered by the buffer module 141A3 to ensure that the fourth data signal D4 of multiple memory bank modules connected to the readout module 142A is stably transmitted to the second latch 142A2. Further, the readout module 142A of the column memory circuit includes a second latch 142A1, a correlated double sampling module 143, a flip-flop 142A2, and a multiplexer 142A3 that are sequentially coupled. Thus, the second latch 142A1 lays a good foundation for the correlated double sampling module 143 to suppress the fixed pattern noise and reset noise in the second data signal D2, thereby laying a good foundation for improving the image quality. The switching of the multiplexer 142A3 and the readout timing between the readout modules 142 can be well coordinated and synchronized by the flip-flop 142A2 and the fourth control signal T4, so that the multiplexer 142A3 can select the third data signal D3 of the corresponding readout module 142 for output (for example, the multiplexer 142A3 can select to output the third signal data D3 of the readout module 142A or the third signal data D3 of the readout module 142C).

[0056] Preferably, still taking the readout module 142A as an example, one input end of its multiplexer 142A3 is coupled to the output end of the flip-flop 142A2 of the readout module 142A, and the other input end of its multiplexer 142A3 is coupled to the output end of the multiplexer ( Figure 5 not shown in the figure) of another readout module 142C adjacent to the readout module 142A. Further, most of the readout modules 142 are coupled to the data transmission module 170 through the multiplexers of other readout modules 142 adjacent to them. For the last readout module 142, the output end of its multiplexer is directly connected to the data transmission module 170.

[0057] Exemplarily, in some exemplary embodiments, the first data signal D1 is encoded in Gray code, and the fourth data signal D4 is encoded in binary code. Thus, encoding the first data signal D1 in Gray code can effectively reduce transmission errors, and encoding the fourth data signal D4 in binary code is more convenient for the subsequent efficient processing of the readout module. It should be noted that those skilled in the art should be able to understand that the present invention does not impose excessive limitations on the specific formats of the first data signal D1 and the fourth data signal D4. When implementing the present invention, it should be reasonably set according to actual needs.

[0058] Exemplarily, in some exemplary embodiments, the flip-flop 142A2 includes a D flip-flop. Thus, for the column memory circuit provided by the present invention, the flip-flop 142A2 of the readout module 142A is designed with a D flip-flop, which can well ensure the serial transmission of the third data signal D3.

[0059] It can be understood that according to the above description, setting the correlated double sampling module 134 in the readout module 142A in the column memory circuit provided by the present invention will increase the amount of data output by the memory bank module 141A. If it is necessary to further improve the performance of the column memory circuit, although the performance requirements for the buffer module 141A3 of the column memory circuit may increase, generally speaking, the column memory circuit provided by the present invention still has good cost performance.

[0060] Exemplarily, please refer to Figure 6 , Figure 6 which schematically shows the topological structure diagram of the column memory circuit provided by the second embodiment of the present invention. Similar to the column memory circuit in Figure 5 in the first embodiment, Figure 6 the i-th memory bank module 141B and the j-th readout module 142B are taken as examples. By comparing Figure 5 and Figure 6 , it can be seen that the basic principles of the column memory circuit provided by the second embodiment of the present invention and the column memory circuit provided by the first embodiment of the present invention are the same. To avoid repetition, for the same parts of the two, no further elaboration will be made. For the parts not mentioned in this article, please refer to the relevant descriptions of the first embodiment of the present invention for adaptive understanding. Only the differences from the first embodiment of the present invention will be described below.

[0061] As Figure 6As shown, in the second embodiment of the present invention, the column memory circuit provided includes, for each memory bank module 141B, a first latch 141B1 and a buffer module 141B2 connected in sequence. The readout module 142B further includes a transcoding module 142B1, a second latch 142B2, a trigger 142B3, and a multiplexer 142B4. The transcoding module 142B1, the second latch

[0062] 142B2, the correlated double sampling module 143, the trigger 142B3, and the multiplexer 142B4 are connected in sequence. Further, the first latch 141B1 is configured to latch the first data signal D1 (such as a voltage signal in Gray code format, which represents the output voltage value of a pixel) when receiving the first control signal T1 (such as comparator data CMP) of the image sensor, and send the latched first data signal D1 to the buffer module 141B2. The buffer module 141B2 is configured to buffer the first data signal D1 to obtain the second data signal D2 (such as a voltage signal in Gray code format, which represents the output voltage value of a pixel), and send the second data signal D2 to the transcoding module 142B1. The transcoding module 142B1 is configured to transcode the second data signal D2 to obtain a first set of fifth data signals D51 (such as a voltage signal in binary format, which represents the voltage value of a black level signal) for sending to the second latch, and after obtaining the first set of fifth data signals D51, transcode the subsequent received second data signal D2 to obtain a second set of fifth data signals D52 (a voltage signal in binary format, which represents the voltage value of an image pixel) for sending to the correlated double sampling module 143. The second latch 142B2 is configured to latch the first set of fifth data signals D51 when receiving the second control signal T2 (such as a black level storage signal). The correlated double sampling module 143 is configured to perform correlated double sampling processing based on the first set of fifth data signals D51 and the second set of fifth data signals D52 to obtain the third data signal D3. The trigger 142B3 sends the third data signal D3 to the multiplexer 142B4 when receiving the third control signal T3 (such as a readout clock signal) of the image sensor. The multiplexer 142B4 is configured to select the corresponding third data signal D3 according to the fourth control signal T4 (such as a memory bank module selection signal) of the image sensor and send it to the data transmission module 170.

[0063] The column memory circuit provided by the second embodiment of the present invention has a memory bank module 141B including a first latch 141B1 and a buffer module 141B2. Thus, the stability of the first data signal D1 can be ensured by the first latch 141B1, and the first data signal D1 can be buffered by the buffer module 141B2 so that the second data signal D2 of multiple memory bank modules connected to the read module 142B can be stably transmitted to the transcoding module 142B1. Further, the read module 142B of the column memory circuit includes a transcoding module 142B1, a second latch 142B2, a correlated double sampling module 143, a trigger 142B3, and a multiplexer 142B4 that are sequentially coupled. Thus, the second data signal D2 is converted into the fifth data signal D5 by the transcoding module 142B1, which can lay a solid foundation for the second latch 142B2 to efficiently process the data signal. The second latch 142B4 can lay a good foundation for the correlated double sampling module 143 to suppress the fixed pattern noise and reset noise in the fifth data signal D5, thereby improving the image quality. The trigger 142B3 can synchronize the switching of the multiplexer 142B4 between read modules 142 and the read timing, so that the multiplexer 142B4 can select the third data signal D3 of the corresponding read module 142 for output (for example, the multiplexer 142B4 can select to output the third signal data D3 of the read module 142B or the third signal data D3 of the read module 142D).

[0064] Preferably, in some exemplary embodiments, the transcoding module 142B1 includes a plurality of second transistors ( Figure 6 not shown in the figure). Thus, the transcoding module 142B1 is designed with a plurality of second transistors, which has a simple logic and is easy to implement. It should be noted that those skilled in the art should be able to understand that using the second transistors to implement the transcoding module 142B1 is only an exemplary illustration of a preferred embodiment, rather than a limitation of the present invention. The present invention does not make any limitation on the specific implementation manner of the transcoding module 142B1. For more detailed content about the transcoding module 142B1, please refer to the related technologies known to those skilled in the art. Due to space limitations, this will not be elaborated further in this article.

[0065] Exemplarily, taking the example that the relevant double sampling module includes P first transistors and the transcoding module includes Q second transistors, in the prior art, the design method of arranging both the transcoding module and the relevant double sampling module in the memory bank module requires a total of M×N×P first transistors and M×N×Q second transistors for these two modules. However, when using the column memory circuit provided in the second embodiment of the present invention, these two modules require a total of N×P first transistors and N×Q second transistors. Thus, it can be seen that compared with the prior art, the present invention can save (M - 1)×N×(P + Q) transistors.

[0066] It can be understood that according to the above description, in the column memory circuit provided in the second embodiment of the present invention, arranging the transcoding module 142B1 and the relevant double sampling module 143 in the readout module 142B will cause an increase in the data volume output by the memory bank module 141B. If it is necessary to further improve the performance of the column memory circuit, although the performance requirements for the buffer module 141B2 of the column memory circuit may increase and a larger data bit width needs to be supported, generally speaking, the column memory circuit provided by the present invention still has a good cost performance.

[0067] It should be noted that as can be understood by those skilled in the art, the present invention does not overly limit the specific type of the image sensor. For example, the image sensor can be, but is not limited to, a CMOS image sensor. Further, the present invention does not overly limit the specific values of M, N, P, and Q. Preferably, the values of M and N are preferably related to the resolution of the image sensor, and should be reasonably set according to actual needs when implementing the present invention.

[0068] The third embodiment of the present invention provides a chip for an image sensor, and the column memory circuit as described in any of the above embodiments is integrated on the chip. Thus, by using a chip integrated with the column memory circuit provided by the present invention, not only can the cost of the image sensor be reduced, but also the integration degree of the image sensor can be further improved.

[0069] The fourth embodiment of the present invention provides an image sensor, and the image sensor includes the column memory circuit as described in any of the above embodiments or the chip as described in the above embodiments. Since the image sensor provided by the present invention and the column memory circuit provided by the present invention belong to the same inventive concept, therefore, the image sensor provided by the present invention has at least all the advantages of the column memory circuit provided by the present invention. For the detailed content of the beneficial effects of the image sensor provided by the present invention, please refer to the relevant description of the beneficial effects of the column memory circuit provided by the present invention above, and will not be elaborated here one by one.

[0070] The fifth embodiment of the present invention provides an imaging device. The imaging device provided in this embodiment includes the column memory circuit provided in any of the above embodiments, or the chip provided in the embodiments herein, or the image sensor provided by the present invention. Exemplarily, please refer to Figure 7 , Figure 7 which is the structural block diagram of the imaging device provided in this embodiment. As Figure 7 shown, the image sensor 100 of the imaging device provided in this embodiment includes the column memory circuit 140 described in any of the above embodiments. Since the imaging device provided in this embodiment and the image sensor provided by the present invention belong to the same inventive concept, and the image sensor provided by the present invention and the column memory circuit provided by the present invention belong to the same inventive concept, therefore, the imaging device provided in this embodiment has at least all the advantages of the column memory circuit provided by the present invention. For the detailed content, please refer to the relevant description of the beneficial effects of the column memory circuit above. Here, it will not be elaborated one by one for the time being.

[0071] Furthermore, as Figure 7 shown, the imaging device provided in this embodiment further includes an Application (APP) 200. The image sensor 100 further includes a pixel array 110, an analog-to-digital converter 120, an image processor 150, and an interface circuit 160. For more detailed content about the image processor 150 and the application 200 of the imaging device, please refer to the related technologies well-known to those skilled in the art. Due to space limitations, it will not be elaborated herein. However, it can be understood that, as described above, the present invention does not impose too many limitations on the imaging device. For example, the imaging device includes, but is not limited to, cameras, cameras, and mobile phones with camera functions.

[0072] Compared with the prior art, a column memory circuit, a chip, an image sensor, and an imaging device provided by the present invention have the following beneficial effects:

[0073] The column memory circuit provided by the present invention abandons the design method of setting the relevant double sampling module in the storage body module in the prior art, and adopts the design method of setting the relevant double sampling module in the readout module. Based on the objective fact that the number of the readout modules is much smaller than the number of the storage body modules, the number of the relevant double sampling modules can be greatly reduced, which not only saves costs, but also reduces the circuit area occupied by the relevant double sampling modules. Furthermore, the area of the column memory circuit can be significantly reduced, and the circuit performance can be well guaranteed. By using the column memory circuit provided by the present invention, the cost of the image sensor can be significantly reduced. The column memory circuit provided by the present invention can be well applied to low-cost image sensors.

[0074] In addition, each functional module in the various embodiments of this document may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.

[0075] The above description is only a description of the preferred embodiments of the column memory circuit, chip, image sensor, and imaging device provided by the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure belong to the protection scope of the present invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations fall within the scope of the present invention and its equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A column memory circuit for an image sensor, characterized in that, It includes M×N memory bank modules, N readout modules, and a data transmission module. The correlated double sampling module of the column memory circuit is disposed in the readout module. The first end of the memory bank module is configured to receive a first data signal. The second end of the memory bank module is coupled to the first end of the corresponding readout module. The second end of the readout module is coupled to the data transmission module, where M≥2. The memory bank module is configured to convert the received first data signal into a second data signal. The readout module is configured to perform correlated double sampling processing on the second data signal through the correlated double sampling module to obtain a third data signal. The data transmission module is configured to output the third data signal.

2. The column memory circuit according to claim 1, wherein The correlated double sampling module includes a plurality of first transistors.

3. The column memory circuit according to claim 1, wherein Each of the memory bank modules includes a first latch, a transcoding module, and a buffer module that are sequentially coupled. The readout module further includes a second latch, a trigger, and a multiplexer. The second latch, the correlated double sampling module, the trigger, and the multiplexer are sequentially coupled. The first latch is configured to latch the first data signal when receiving the first control signal of the image sensor and send the latched first data signal to the transcoding module. The transcoding module is configured to transcode the first data signal to obtain a fourth data signal. The buffer module is configured to buffer the fourth data signal to obtain a first set of the second data signals for sending to the second latch and buffer a second set of the second data signals for sending to the correlated double sampling module after obtaining the first set of the second data signals. The second latch is configured to latch the first set of the second data signals when receiving a second control signal. The correlated double sampling module is configured to perform correlated double sampling processing based on the first set of the second data signals and the second set of the second data signals to obtain the third data signal. The trigger sends the third data signal to the multiplexer when receiving the third control signal of the image sensor. The multiplexer is configured to select the corresponding third data signal according to the fourth control signal of the image sensor and send it to the data transmission module.

4. The column memory circuit according to claim 3, wherein The first data signal uses a Gray code encoding method, and the fourth data signal uses a binary encoding method.

5. The column memory circuit according to claim 3, characterized in that, The trigger includes a D flip-flop.

6. The column memory circuit according to claim 1, characterized in that, Each of the memory bank modules includes a first latch and a buffer module that are sequentially coupled. The readout module further includes a transcoding module, a second latch, a trigger, and a multiplexer. The transcoding module, the second latch, the correlated double sampling module, the trigger, and the multiplexer are sequentially coupled. The first latch is configured to latch the first data signal when receiving the first control signal of the image sensor and send the latched first data signal to the buffer module. The buffer module is configured to buffer the first data signal to obtain the second data signal and send the second data signal to the transcoding module. The transcoding module is configured to transcode the second data signal to obtain a first set of fifth data signals for transmission to the second latch, and after obtaining the first set of fifth data signals, transcode the subsequently received second data signals to obtain a second set of fifth data signals for transmission to the correlated double sampling module; the second latch is configured to latch the first set of fifth data signals when receiving a second control signal; the correlated double sampling module is configured to perform correlated double sampling processing according to the first set of fifth data signals and the second set of fifth data signals to obtain the third data signal, the flip-flop sends the third data signal to the multiplexer when receiving a third control signal of the image sensor, and the multiplexer is configured to select a corresponding third data signal according to a fourth control signal of the image sensor and send it to the data transmission module.

7. The column memory circuit according to claim 6, characterized in that, The transcoding module includes a plurality of second transistors.

8. A chip for an image sensor, characterized in that, The chip integrates the column memory circuit according to any one of claims 1 to 7.

9. An image sensor, characterized in that, Includes the column memory circuit according to any one of claims 1 to 7 or the chip according to claim 8.

10. An imaging device, characterized in that, Includes the column memory circuit according to any one of claims 1 to 7, the chip according to claim 8, or the image sensor according to claim 9.

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