Garbage collection method in flash memory device, computer readable storage medium and device

Abstract

The invention relates to a garbage collection method in a flash memory device, a computer readable storage medium and a device. The method is executed by a processing unit and comprises the following steps of: finding out a source block corresponding to the first accumulated effective page count which is greater than the total number of physical pages of a target block according to the accumulated effective page counts of a plurality of sorted source blocks; marking the found source block and the subsequent source block as a first type of source block; marking the source blocks except the first type of source blocks as second type of source blocks; obtaining one or more host-flash memory contrast sub-tables associated with valid pages stored in the second type of source block; detecting a plurality of valid pages stored in the first type source block and the second type source block according to the sequence of the logic addresses in the host-flash memory contrast sub-table during scanning of each host-flash memory contrast sub-table, and newly adding a plurality of records to the garbage collection data table for the plurality of valid pages; and writing the user data of the specific physical page in the specific first type source block or the specific second type source block into the specific physical page in the target block according to each record in the garbage collection data table.

Description

Technical Field

[0001] The present invention relates to a storage device, and in particular to a garbage collection method in a flash memory device, a computer-readable storage medium and a device. Background Art

[0002] Flash memory is generally divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processing unit (CPU) can provide any address to access the NOR flash memory on the address pin and promptly obtain the data stored at that address from the data pin of the NOR flash memory. In contrast, NAND flash memory is not random access, but serial access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the CPU needs to write serial byte values to the NAND flash memory to define the type of request command (such as read, write, erase, etc.) and the address used for this command. The address can point to a page (the smallest data block for write operations in flash memory) or a block (the smallest data block for erase operations in flash memory).

[0003] After multiple accesses, a physical block may contain valid and invalid pages (also known as expired pages). Valid pages store valid user data, while invalid pages store invalid (old) user data. When the flash memory controller detects that the available space in the flash memory module is below a threshold, it can issue a read command instructing the flash memory module to read and collect user data from valid pages in several physical blocks (referred to as source blocks). Then, it can issue a write command instructing the flash memory module to rewrite the collected valid user data to an empty block (referred to as a destination block). The source blocks containing only invalid pages can then be erased to provide new data storage space. This process is called garbage collection (GC). However, a poorly designed garbage collection process can affect the overall performance of the flash memory device. Summary of the Invention

[0004] In view of this, how to alleviate or eliminate the defects in the above-mentioned related fields is indeed a problem to be solved.

[0005] The present invention relates to a garbage collection method in a flash memory device, which is executed by a processing unit and includes: sorting data blocks according to valid page counts of multiple data blocks, and selecting a default number of data blocks as multiple source blocks starting from the data block with the least valid page count; finding a source block corresponding to the first cumulative valid page count that is greater than the total number of physical pages of a destination block according to the cumulative valid page counts of the sorted source blocks; marking the found source block and subsequent source blocks as first-type source blocks; marking source blocks other than the first-type source blocks as second-type source blocks; obtaining one or more host-flash comparison sub-tables associated with valid pages stored in the second-type source blocks; in scanning each host-flash comparison sub-table, detecting multiple valid pages stored in the first-type source blocks and the second-type source blocks according to the order of logical addresses in the host-flash comparison sub-table, and adding multiple records for the multiple valid pages to a garbage collection data table; and writing user data of a specific physical page in a specific first-type source block or a specific second-type source block to a specific physical page in the destination block according to each record in the garbage collection data table.

[0006] The present invention also relates to a computer-readable storage medium for storing program code that can be loaded and executed by a processing unit of a flash memory controller, and the program code implements the garbage collection method in the flash memory device as described above when executed by the processing unit.

[0007] The present invention also relates to a garbage collection device in a flash memory device, comprising: a flash memory interface coupled to a flash memory module; and a processing unit coupled to the flash memory interface. The processing unit is configured to sort data blocks according to valid page counts of multiple data blocks in a flash memory module, and select a default number of data blocks as multiple source blocks starting from the data block with the least valid page count; find the source block corresponding to the first cumulative valid page count that is greater than the total number of physical pages of a destination block based on the cumulative valid page counts of the sorted source blocks; mark the found source block and subsequent source blocks as first-type source blocks; mark source blocks other than the first-type source blocks as second-type source blocks; obtain one or more host-flash comparison sub-tables associated with valid pages stored in the second-type source blocks; in scanning each host-flash comparison sub-table, detect multiple valid pages stored in the first-type source blocks and the second-type source blocks based on the order of logical addresses in the host-flash comparison sub-table, and add multiple records for the multiple valid pages to a garbage collection data table; and drive the flash memory interface based on each record in the garbage collection data table to write user data of a specific physical page in a specific first-type source block or a specific second-type source block to a specific physical page in the destination block.

[0008] The total number of records associated with the first type source blocks in the garbage collection data table is less than or equal to the difference between the total number of physical pages of a destination block and the total number of valid page counts of the second type source blocks.

[0009] One of the advantages of the above embodiment is that, through the above method and operation, it is ensured that after the garbage collection process is completed, the storage space of the second type source block can be released in the future for use by new user data.

[0010] Other advantages of the present invention will be explained in more detail with reference to the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0012] Figure 1 FIG. 4 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

[0013] Figure 2 FIG. 1 is a schematic diagram of a flash memory module according to an embodiment of the present invention.

[0014] Figure 3 FIG. 4 is a partial hardware architecture diagram of a NAND flash memory unit according to an embodiment of the present invention.

[0015] Figure 4 FIG. 4 is a schematic diagram illustrating the association between a high-level lookup table and a host-flash memory lookup sub-table according to an embodiment of the present invention.

[0016] Figure 5 FIG. 1 is a schematic diagram illustrating the association between a host-flash memory reference subtable and a physical page according to an embodiment of the present invention.

[0017] Figure 6 FIG. 1 is a schematic diagram of releasing a source block, forcibly cleaning a source block, and a destination block according to an embodiment of the present invention.

[0018] Figure 7 FIG. 1 is a flow chart of a method for selecting and arranging source blocks in a first stage according to an embodiment of the present invention.

[0019] Figure 8A and Figure 8B FIG. 4 is a flowchart of a method for arranging valid user data in a destination block in the second stage according to an embodiment of the present invention.

[0020] Figure 9 Schematic diagram of determining valid pages based on the contents of the host-flash memory comparison subtable and the flash memory-host comparison table according to an embodiment of the present invention.

[0021] The following are the descriptions of the reference numerals:

[0022] 10 Electronic devices

[0023] 110 Host side

[0024] 130 Flash Memory Controller

[0025] 131 Host Interface

[0026] 132 bus architecture

[0027] 134 processing units

[0028] 136 Random Access Memory

[0029] 139 Flash memory interface

[0030] 150 Flash Memory Module

[0031] 151 Interface

[0032] 153#0~153#15 NAND flash memory unit

[0033] CH#0~CH#3 channels

[0034] CE#0~CE#3 start signal

[0035] 300 storage blocks

[0036] 310 floating-gate transistor

[0037] BL1~BL3 bit lines

[0038] WL0~WL5 word lines

[0039] 410 Advanced Comparison Table

[0040] 430#0~430#15 Host-Flash Comparison Subtable

[0041] 500#1 Super Block

[0042] 510 physical pages

[0043] 530 Physical address information

[0044] 530-0 Superblock number

[0045] 530-1 physical page number

[0046] 610#0~610#n release source block

[0047] 610#n+1~610#MaxNum SBLK -1 Force cleanup of source blocks

[0048] 650 destination block

[0049] 655 remaining pages

[0050] S710~S790 Method Steps

[0051] S812~S874 Method Steps

[0052] 910, 930 Flash Drive-Host Comparison Table

[0053] SBLK#0, SBLK#5 source block DETAILED DESCRIPTION

[0054] The embodiments of the present invention will be described below with reference to the accompanying drawings. In these drawings, the same reference numerals represent the same or similar components or method flows.

[0055] The following provides various aspects and embodiments of the present invention. Some embodiments can be implemented independently, while others can be combined and implemented as readily apparent to one skilled in the art. The following description is for illustrative purposes only, with specific details provided to provide a complete understanding of the various aspects of the present invention. However, it will be apparent that these embodiments do not necessarily require such exhaustive implementation. The drawings and description are not intended to limit the present invention.

[0056] The following descriptions are merely examples of various aspects and are not intended to limit the scope, applicability, or configuration of this specification. Instead, the various examples are intended to provide a description that one of ordinary skill in the art can implement. It should be understood that the functions and arrangements of the components herein may be modified without violating the scope and spirit of the claims.

[0057] refer to Figure 1. The electronic device 10 includes a host side (Host Side) 110, a flash memory controller 130 and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 can be collectively referred to as the device side (Device Side). The electronic device 10 can be implemented in electronic products such as peripheral storage devices, personal computers, laptop computers (Laptop PCs), tablet computers, mobile phones, digital cameras, digital video cameras, smart TVs, smart refrigerators, and automotive electronic systems. The host side 110 and the host interface (Host Interface) 131 of the flash memory controller 130 can communicate with each other using communication protocols such as Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E), Universal Flash Storage (UFS), and Embedded Multi-Media Card (eMMC). The flash memory controller 130's flash interface 139 and the flash memory module 150 can communicate with each other using a double data rate (DDR) communication protocol, such as the Open NAND Flash Interface (ONFI), a double data rate switch (DDR Toggle), or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in a variety of ways, such as using general-purpose hardware (e.g., a microcontroller unit, a single processor, a multi-processor with parallel processing capabilities, a graphics processor, or other processor with computing capabilities), and provides the functions described below when executing software and / or firmware instructions. The processing unit 134 receives host commands, such as read commands, write commands, discard commands, erase commands, etc., through the host interface 131, and schedules and executes these commands.Flash controller 130 also includes random access memory (RAM) 136, which can be implemented as dynamic random access memory (DRAM), static random access memory (SRAM), or a combination of the two. This RAM 136 is used to configure space as a data buffer for storing user data (also referred to as host data) read from host 110 and to be written to flash memory module 150, as well as user data read from flash memory module 150 and to be output to host 110. RAM 136 can also store data required during execution, such as variables, data tables, data structures, host-to-flash (H2F) tables, flash-to-host (F2HTable) tables, and queues. The flash memory interface 139 includes a NAND flash controller (NFC), which provides functions required for accessing the flash memory module 150, such as a command serializer (CSerializer) and a low-density parity check (LDPC).

[0058] Flash memory controller 130 may be configured with a bus architecture 132 for coupling components to each other for transmitting data, addresses, and control signals. These components include, but are not limited to, host interface 131, processing unit 134, RAM 136, and flash memory interface 139. Direct memory access (DMA) circuits within these components can transfer data between components via bus architecture 132 based on instructions or control signals. For example, a DMA circuit within host interface 131 or flash memory interface 139 can move data from a specific data buffer therein to a specific address within RAM 136, or vice versa.

[0059] Flash memory module 150 provides a large amount of storage space, typically hundreds of gigabytes (GB) or even multiple terabytes (TB), for storing large amounts of user data, such as high-resolution images and videos. Flash memory module 150 includes control circuitry and a memory array. The memory cells in the memory array can be configured as single-level cells (SLCs), multiple-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), or any combination thereof. Processing unit 134 writes user data to a specified address (destination address) in flash memory module 150 and reads user data from a specified address (source address) in flash memory module 150 via flash memory interface 139. Flash memory interface 139 coordinates the transfer of data and commands between flash memory controller 130 and flash memory module 150 using multiple electronic signals, including data lines, clock signals, and control signals. The data lines can be used to transmit commands, addresses, read and write data; the control signal lines can be used to transmit control signals such as chip enable (CE), address latch enable (ALE), command latch enable (CLE), and write enable (WE).

[0060] refer to Figure 2 The interface 151 in the flash memory module 150 may include four input / output channels (I / O channels, hereinafter referred to as channels) CH#0 to CH#3, each of which connects to four NAND flash memory cells. For example, channel CH#0 connects to NAND flash memory cells 153#0, 153#4, 153#8, and 153#12. Each NAND flash memory cell may be packaged as an independent chip (die). The flash memory interface 139 may activate NAND flash memory cells 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15 by issuing one of the activation signals CE#0 to CE#3 via the interface 151, and then read user data from or write user data to the activated NAND flash memory cells in parallel.

[0061] refer to Figure 3The local hardware architecture of a NAND flash memory cell. Each NAND flash memory cell may include a memory block 300, which includes multiple memory cells, such as floating gate transistors 310 or other charge trap devices. The structure of the memory block 300 includes multiple bit lines and multiple word lines. For simplicity, Figure 3 Only bit lines BL1 to BL3 and word lines WL0 to WL5 are shown. For example, floating gate transistors on word lines WL0 to WL2 and WL3 to WL5 form different pages for storing data of two pages.

[0062] Each NAND flash memory cell may contain multiple data planes, and each data plane may contain multiple physical blocks. To improve the efficiency of data writing and reading, designated physical blocks in the data planes of multiple NAND flash memory cells may be organized into a super block (SB), and each super block may contain multiple physical pages. Super blocks and physical pages may be identified using super-block numbers and page numbers, respectively. The combination of these numbers may be referred to as the physical address of the flash memory module 150.

[0063] Each superblock can be classified as a data block or a current block based on its function. Processing unit 134 can select an empty superblock as the current block to prepare for writing user data received from host 110. To improve data writing efficiency, user data provided by host 110 can be written in parallel to specific physical pages in a superblock spanning multiple NAND flash memory cells. Processing unit 134 can maintain a Flash-to-Host (F2H) table for each current block in RAM 136. The table contains multiple records that store, in page number order, information about the logical address to which the user data for each physical page in the current block is associated (or mapped). Logical addresses can be represented using logical block addresses (LBAs), host page numbers, or other methods and are managed by host 110. For example, each logical block address or host page is associated with 4KB of user data. After all physical pages in a current block are filled with user data, or after the remaining pages in a current block are filled with false values, the processing unit 134 can drive the flash memory interface 139 to write the corresponding F2H table in the RAM 136 to the data portion of a specified physical page (e.g., the last physical page) of the current block. After the corresponding F2H table has been written to the flash memory module 150, the current block is converted into a data block, and the user data stored in the data block will no longer be changed. Because user data at the same logical address may be written to different physical pages in a current block, some physical pages containing invalid data may appear in the current block. The processing unit 134 can calculate the valid page count (VPC) in the current block. Then, the processing unit 134 can select another empty super block as the new current block.

[0064] In some embodiments, in addition to the corresponding F2H table, the processing unit 134 may also drive the flash memory interface 139 to write the initial VPC into the metadata of a specified physical page (e.g., the last physical page) of the current block. In other embodiments, the processing unit 134 may maintain a VPC table in the RAM 136 to store the VPCs of all data blocks. Each time a data block is generated, the processing unit 134 may update the contents of the VPC table to include information about the new data block and its VPC. After updating the VPC table for a predetermined number of data blocks, the processing unit 134 may drive the flash memory interface 139 to write the latest VPC table to a specified physical address in the flash memory module 150.

[0065] In addition to writing the F2H table to the specified physical page in the current block, the processing unit 134 also needs to update the H2F table based on the content of the F2H table of the current block, so that when executing a host read command in the future, it can quickly find out from the H2F table which physical address the user data associated with a specific logical address is actually stored. The H2F table contains multiple records, which store information about which logical address the user data of each logical address is actually stored in the order of the logical addresses. However, since the RAM 136 cannot provide enough space to store the entire H2F table for the processing unit 134 to quickly find it during future data read operations, the H2F table can be divided into multiple H2F sub-tables and stored in the flash memory module 150, so that the corresponding H2F sub-table can be read from the flash memory module 150 to the RAM 136 during future data read operations. Reference Figure 4 , the entire H2F table can be divided into H2F sub-tables 430#0 to 430#15. The processing unit 134 also maintains a high-order comparison table 410, which includes multiple records and stores the physical address information of the H2F sub-table associated with each logical address segment in the order of the logical address. For example, the H2F sub-table 430#0 associated with the 0th to 4095th LBA is stored in the 0th physical page in a specific super block (the letter "Z" can represent the number of the super block), the H2F sub-table 430#1 associated with the 4096th to 8191th LBA is stored in the 1st physical page in the specific super block, and so on. Although Figure 4 The 16 H2F sub-tables are included, but those skilled in the art may set more or fewer H2F sub-tables according to the capacity of the flash memory module 150, and the present invention is not limited thereto.

[0066] The space required for each H2F subtable can be 1KB, 2KB, 4KB, 8KB, etc. Figure 5. For example, H2F subtable 430#0 stores the physical address information mapped to each logical address in the order of multiple logical addresses in a logical address range. Logical addresses can be represented by LBA numbers, and each LBA number corresponds to a fixed-size physical storage space, such as 4KB. Those skilled in the art can also use main page numbers to represent logical addresses, and the present invention is not limited to this. For example, H2F subtable 430#0 stores physical address information from LBA#0 to LBA#4095 in sequence. Physical address information 530 can be represented by four bytes: the first two bytes 530-0 record the super block number (Super Block Number); the last two bytes 530-1 record the physical page number (Physical Page Number). For example, the physical address information 530 corresponding to LBA#2 can point to physical page 510 in super block 500#1. Byte 530-0 records the number of super block 500#1, and byte 530-1 records the number of physical page 510.

[0067] To ensure that more data blocks are released after GC processing, embodiments of the present invention prioritize the selection of source blocks (SBLKs) and then consider LBA concentration when selecting valid pages. The entire GC process consists of three phases: source block selection and sequencing; placement of valid user data in destination blocks (DBLKs); and migration of valid user data and release of source blocks.

[0068] In the first stage, the flash controller 130 sorts the data blocks in ascending order according to their VPCs and selects a default number MaxNum starting from the data block with the least VPC. SBLK The data block is used as the source block. MaxNum SBLK is a constant representing the maximum number of source blocks, for example, 16. The flash controller 130 also finds the source block corresponding to the first cumulative VPC that is greater than the number of physical pages of a destination block based on the cumulative VPCs of the sorted source blocks, and marks the found source block and subsequent source blocks as Force Clean Source BLocK (FCSBLK), while the other source blocks can be called Released Source BLock (RSBLK). Figure 6 The flash controller 130 may select a default number MaxNum starting from the data block 610#0 of the least VPCs. SBLK Data blocks 610#0 to 610#MaxNum SBLK-1 as the source block. The cumulative valid page count in data blocks 610#0 to 610#n is less than or equal to the maximum number of pages MaxP that can be written to a destination block 650. DBLK , but the cumulative valid page count in data blocks 610#0 to 610#n+1 is higher than the maximum number of pages MaxP that can be written to a destination block 650 DBLK , where n can be 0 to MaxNum SBLK Any positive integer between -1. Data block 610#n+1 to 610#MaxNum SBLK -1 is marked as FCSBLK, and data blocks 610#0 to 610#n can be called RSBLK. Destination block 650 is a new current block for writing data blocks 610#0 to 610#MaxNum SBLK -1. The user data of all valid pages in the released blocks 610#0 to 610#n can be rewritten into the destination block 650. After the user data of all valid pages in the released blocks 610#0 to 610#n are rewritten into the destination block 650, there are no valid pages in the released blocks 610#0 to 610#n, so that new user data can be rewritten in the released blocks 610#0 to 610#n after being erased. The remaining pages 655 in the destination block 650 can be provided to the data blocks 610#n+1 to 610#MaxNum SBLK -1, which contains limited user data for valid pages. Data blocks 610#n+1 to 610#MaxNum SBLK The logical address associated with the valid page selected in -1 is close to the logical address associated with the valid pages in the released blocks 610 # 0 to 610 # n.

[0069] refer to Figure 7 The method for selecting and sequencing source blocks in the first stage is shown. When loading and executing the program code of the Firmware Translation Layer (FTL), the processing unit 134 selects source blocks from the data blocks and labels each source block as RSBLK or FCSBLK, as detailed below:

[0070] Step S710: Sort the data blocks in ascending order according to their VPCs, and select the default number MaxNum starting from the data block with the least VPC SBLK(e.g., 16) data blocks are used as source blocks. In some embodiments, processing unit 134 may drive flash memory interface 139 to locally read the VPC of each data block from the metadata of a specified physical page (e.g., the last physical page) in flash memory module 150. In other embodiments, processing unit 134 may drive flash memory interface 139 to read a VPC table from a specified physical address in flash memory module 150 and obtain the VPCs of all data blocks from the VPC table. Processing unit 134 then sorts all data blocks in ascending order according to the obtained VPCs.

[0071] Step S720: Set variables i and VPC temp and VPC total The processing unit 134 uses the variable i to record the number of the source block currently being processed, and uses VPC temp and VPC total Record the VPCs of the current accumulated source blocks. During the entire process, the processing unit 134 ensures that the VPC total No more than the maximum number of pages MaxP that can be written to a destination block 650 DBLK .

[0072] Step S730: Determine whether the variable i is greater than the default number MaxNum SBLK If yes, it means that the user data of all valid pages of the source block can be written to the destination block 650, and the process ends. Otherwise, the process continues to process step S740.

[0073] Step S740: Calculate VPC temp =VPC temp +VPC i , where VPC i Represents the VPC of the i-th source block.

[0074] Step S750: Determine the variable VPC temp Is it greater than the maximum number of pages MaxP that can be written to a destination block 650? DBLK If yes, it means that the VPCs accumulated to the i-th source block have exceeded the maximum number of pages MaxP that can be written to a destination block 650. DBLK , the process continues to process step S780. Otherwise, the process continues to process step S760.

[0075] Step S760: Calculate VPC total =VPC total +VPC i , where VPC i Represents the VPC of the i-th source block.

[0076] Step S770: Add 1 to the variable i.

[0077] Step S780: Calculate DIFF=MaxP DBLK -VPC total The variable DIFF represents the total number of remaining pages 655 in the destination block 650.

[0078] Step S790: Set the i-th to MaxNum-th SBLK -1 source blocks are marked as FCSBLK, and the 0th to i-1th source blocks are marked as RSBLK. The processing unit 134 can store the marking information of the source blocks in the RAM 136 for reference in subsequent stages. For example, assuming MaxNum SBLK If set to 8, the processing unit 134 may store the example source block data table shown in Table 1 in the RAM 136:

[0079] Table 1

[0080] Superblock number Tag information 100 RSBLK 99 RSBLK 200 RSBLK 18 RSBLK 74 RSBLK 3 FCSBLK 25 FCSBLK 310 FCSBLK

[0081] The source block data table contains eight records, storing the superblock numbers and tag information for source blocks 0 through 7. Records 0 through 7 store the superblocks corresponding to the eight source blocks, SB#100, SB#99, SB#200, SB#18, SB#74, SB#3, SB#25, and SB#310, in ascending order. These superblocks are sorted by their VPCs, with superblocks SB#100, SB#99, SB#200, SB#18, and SB#74 marked as RSBLK, and superblocks SB#3, SB#25, and SB#310 marked as FCSBLK.

[0082] In the second phase, flash controller 130 retrieves one or more H2F sub-tables associated with valid pages stored in RSBLK and scans each of the retrieved H2F sub-tables. During each scan, flash controller 130 detects valid pages stored in RSBLK and FCSBLK based on the order of the logical addresses in the H2F sub-tables and adds new records to the GC data table. Each record stores information about user data from a specific physical page in a specific RSBLK or FCSBLK stored in a specific physical page in DBLK. The total number of records in the GC data table for valid FCSBLK pages does not exceed DIFF.

[0083] refer to Figure 8A and 8BThe method for arranging valid user data in the destination block in the second stage is shown. When the processing unit 134 loads and executes the FTL program code, it generates a GC data table based on the contents of the F2H table of the source block and the contents of the H2F subtable associated with the RSBLK. The details are as follows:

[0084] Step S812: Set the variable i to 0. The processing unit 134 uses the variable i to record the number of the source block currently being processed.

[0085] Step S814: Determine whether the variable i is greater than the default number MaxNum SBLK If yes, it means all source blocks have been processed and this process ends. Otherwise, the process continues to step S816.

[0086] Step S816: Obtain the F2H table of the i-th source block.

[0087] Step S822: Set the variable j to 0. The processing unit 134 uses the variable j to record the record number currently being processed in the F2H table (ie, the physical page number of the source block).

[0088] Step S824: Determine whether the H2F sub-table corresponding to the j-th record in the F2H table has been scanned. If yes, the process continues to process at step S826. Otherwise, the process continues to process at step S832. The processing unit 134 can maintain information on whether each H2F sub-table has been scanned in a known data structure in the RAM 136, such as a data table, a bitmap, etc. Initially, the bitmap stores information that each H2F sub-table has not been scanned. For example, referring to Figure 4 When the jth record in the F2H table is LBA #8200, this record corresponds to H2F subtable 430 #2. Processing unit 134 can query the value of the second bit in the bitmap to determine whether H2F subtable 430 #2 has been scanned. If the value of the second bit is "1," H2F subtable 430 #2 has been scanned. If the value of the second bit is "0," H2F subtable 430 #2 has not been scanned.

[0089] Step S826: Add 1 to the variable j.

[0090] Step S828: Determine whether the variable j is greater than MaxP SBLK -1, where MaxP SBLK is a constant representing the maximum number of physical pages that a source block (or data block) can store. If yes, it means that all physical pages in this source block have been processed, and the process continues to step S830. Otherwise, the process continues to step S822.

[0091] Step S830: Add 1 to the variable i.

[0092] Step S832: Get the H2F sub-table corresponding to the j-th physical page in the source block (ie, the i-th source block). Figure 4 , when the jth record in the F2H table is LBA#300, this record corresponds to the H2F subtable 430#0.

[0093] Step S834: Set the variable k to 0. The processing unit 134 uses the variable k to record the record number currently being processed in the H2F subtable, and the record number k can be calculated to obtain a logical address. For example: LBA k =H2FStart+k, where LBA k Represents the LBA number of the kth record in this H2F subtable; H2FStart is a default constant, representing the starting LBA number of this H2F subtable. Figure 4 , the starting LBA number of H2F sub-table 430#0 is LBA#0, the starting LBA number of H2F sub-table 430#1 is LBA#4096, and so on.

[0094] Step S836: Determine whether the variable k is greater than MaxLA H2F -1, where MaxLA H2F Is a constant representing the maximum number of records that an H2F subtable can store. If yes, it means that all records in this H2F subtable have been processed, and the process continues to step S846. Otherwise, the process continues to step S842.

[0095] Step S842: Determine whether the physical address of the k-th record in the H2F subtable is associated with a source block. If so, the process proceeds to step S852. Otherwise, the GC process intends to exclude the data block associated with the physical address of the k-th record in the H2F subtable, and the process proceeds to step S844.

[0096] Step S844: Add 1 to the variable k.

[0097] Step S846: Store the information that has been scanned by this H2F sub-table. For example, refer to Figure 4 When the H2F sub-table 430#2 has been scanned, the processing unit 134 may update the value of the second bit in the bitmap to "1".

[0098] Step S852: Determine whether the physical address of the kth record in the H2F subtable is associated with RSBLK or FCSBLK. If it is RSBLK, the process continues with step S872. If it is FCSBLK, the process continues with step S862.

[0099] Step S862: Determine whether DIFF is equal to or less than 0. If so, it indicates that no more valid pages can be collected from FCSBLK, and the process continues with step S844. Otherwise, the process continues with step S864. The initial calculation of DIFF can be found in the description of step S780.

[0100] Step S864: Determine whether the physical address mapped by the kth record in the H2F subtable matches the logical address mapped by the corresponding record in the F2H table of this FCSBLK. If so, the process continues with step S866. Otherwise, the process continues with step S844.

[0101] Step S866: Add a new record to the GC data table, indicating that the user data of the logical address mapped by the corresponding record in the F2H table of this FCSBLK is rewritten to the 0th (or next) physical page of the DBLK.

[0102] Step S868: Subtract 1 from the variable DIFF.

[0103] Step S872: Determine whether the physical address mapped by the kth record in the H2F subtable matches the logical address mapped by the corresponding record in the F2H table of this RSBLK. If so, the process continues with step S874. Otherwise, the process continues with step S844.

[0104] Step S874: Add a new record to the GC data table, indicating that the user data of the logical address mapped by the corresponding record in the F2H table of the RSBLK is rewritten to the 0th (or next) physical page of the DBLK.

[0105] Regarding steps S864 and S872, for example, refer to Figure 9The 0th source block SBLK#0 (i.e., the 1st super block "F1") includes multiple physical pages "P0," "P1," "P2," and so on. The 5th source block SBLK#5 (i.e., the 8th super block "F8") includes multiple physical pages "P0," "P1," "P2," and so on. F2H table 910 stores the last physical page of source block SBLK#0, while F2H table 930 stores the last physical page of source block SBLK#5. The contents of F2H table 910 indicate that its 0th physical page stores user data for LBA#8192, its 1st physical page stores user data for LBA#8193, and its 2nd physical page stores user data for LBA#8194. The contents of F2H table 930 indicate that its 0th physical page stores user data for LBA#8194, its 1st physical page stores user data for LBA#77, and its 2nd physical page stores user data for LBA#25779. H2F subtable 430#2 contains the physical addresses mapped to LBA#8192 through LBA#12287. Specifically, user data for LBA#8192 is stored in physical page 0 "P0" of superblock "F1," user data for LBA#8193 is stored in physical page 1 "P1" of superblock "F1," and user data for LBA#8194 is stored in physical page 0 "P0" of superblock "F8." The physical address "F1:P0" stored in the 0th record of H2F subtable 430#2 (corresponding to LBA#8192) matches the logical address "LBA#8192" stored in the 0th record of F2H table 910. The physical address "F1:P1" stored in the 1st record of H2F subtable 430#2 (corresponding to LBA#8193) matches the logical address "LBA#8193" stored in the 1st record of F2H table 910. The physical address "F8:P0" stored in the second record (corresponding to LBA#8194) of H2F sub-table 430#2 matches the logical address "LBA#8194" stored in the 0th record of F2H table 930. However, the logical address "LBA#8194" stored in the second record of F2H table 930 does not match the physical address "F8:P0" stored in the second record (corresponding to LBA#8194) of H2F sub-table 430#2.

[0106] For example, based on Figure 9 For example, the processing unit 134 may store an example GC data table as shown in Table 2:

[0107] Table 2

[0108] Source Location Destination F1:P0 DBLK:P0 F1:P1 DBLK:P1 F8:P0 DBLK:P2

[0109] The GC data table includes three records, each of which stores information about rewriting user data of a specific physical page of a specific data block to a specific physical page of a DBLK.

[0110] It should be noted that the total number of records associated with FCSBLK in the GC data table is less than or equal to the DIFF calculated in step S780.

[0111] In the third phase, flash controller 130 rewrites the user data from a specific physical page of a specific data block in flash memory module 150 to a specific physical page of a destination block in flash memory module 150, based on each record in the GC data table. After the rewriting is complete, flash controller 130 updates the corresponding records in all H2F subtables retrieved in step S832 to reflect the result of the user data move at the specific logical address. Furthermore, after the move is complete, flash controller 130 may, when appropriate, erase the RSBLK in flash memory module 150 to store the new user data.

[0112] In some embodiments, after rewriting, the processing unit 134 may update the VPC table, set the VPC of each RSBLK to 0, and subtract the number of moved physical pages in each FCSBLK from the VPC of the FCSBLK to reflect the result of the GC process.

[0113] In some embodiments of user data migration, the processing unit 134 may drive the flash memory interface 139 to read user data from a specific physical page of a specific data block of the flash memory module 150 based on each record of the GC data table, and drive the flash memory interface 139 to write the read user data to a specific physical page of the DBLK in the flash memory module 150.

[0114] In other embodiments of user data migration, the processing unit 134 may drive the flash memory interface 139 to send appropriate commands to the flash memory module 150 based on each record in the GC data table, so as to allow the flash memory module 150 to write the user data of a specific physical page of a specific data block to a specific physical page of the DBLK by internal copying.

[0115] Although the present invention is illustrated and described herein with reference to specific embodiments, the present invention is not intended to be limited to the details shown. On the contrary, various modifications may be made to the details within the scope and equivalents of the claims without departing from the present invention. It should be understood that the above description is an illustration of the present invention and should not be construed as limiting the present invention. Various modifications, applications, and / or combinations of the embodiments may be envisioned by those of ordinary skill in the art without departing from the scope of the present invention as defined by the claims.

[0116] Those skilled in the art will readily appreciate that the present invention discussed above may be implemented using different configurations of hardware components than those disclosed. Thus, while the present invention has been described based on these preferred embodiments, certain modifications, variations, and alternative configurations will be apparent to those skilled in the art and are within the scope of the present invention.

[0117] It must be understood that the words "comprise", "include", etc. used in this specification are used to indicate the existence of specific technical features, values, method steps, operation processes, parts and / or components, but do not exclude the addition of more technical features, values, method steps, operation processes, components, parts, or any combination of the above.

[0118] The terms "first", "second", "third", etc. used in the present invention are used to modify the components in the claims and are not used to indicate a priority order or a precedence relationship between them, or that one component precedes another, or the temporal order of executing method steps. They are only used to distinguish components with the same name.

[0119] It should be understood that when a component is described as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, and intervening components may be present. Conversely, when a component is described as being "directly connected" or "directly coupled" to another component, there are no intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner, for example, "between" versus "directly between," or "adjacent" versus "directly adjacent," etc.

[0120] The word "device" or "module" is not limited to one or a specific number of physical objects (e.g., a smart mobile phone, a controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more components that can implement at least some of the functions of the present invention in this disclosure. Although the description and examples use the word "device" or "module" to describe various aspects of the present disclosure, the word "device" or "module" is not limited to a specific configuration, type, or number of objects. In addition, the word "system" or "module" is not limited to multiple components or a specific direction. For example, a system can be implemented on one or more printed circuit boards or other substrates and can have movable or static components. Although the description and examples use the word "system" to describe various aspects of the present invention in this disclosure, the word "system" is not limited to a specific configuration, type, or number of objects.

[0121] Specific details are provided in the above description to assist in a thorough understanding of various inventive aspects. However, it will be understood by those skilled in the art that these aspects may be practiced in the absence of these specific details. To enable clarity of explanation, in some instances, the present technology may be presented as comprising separate functional blocks comprising devices, device components, steps or subroutines embodied in methods of software, or a combination of hardware and software. Other additional components other than those shown in the figures and / or described herein may also be used. For example, circuits, systems, networks, processes, and other components may be displayed as components in block diagram form to avoid obscuring these aspects with unnecessary details. In other instances, to avoid obscuring these aspects with unnecessary details, known circuits, processes, algorithms, structures, and techniques may be displayed without unnecessary details.

[0122] Some aspects may be described herein as processes or methods, which may be shown as flow charts, data flow diagrams, structure diagrams, or block diagrams. Although a flow chart may describe operations as sequential processes, multiple operations may be performed in parallel or simultaneously. Furthermore, the order of the operations may be rearranged. A process terminates when the operations are completed, but there may be additional steps not included in the diagram. A process may correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the function returning to the calling function or the main function.

[0123] All or part of the steps in the method described in the present invention can be implemented by a computer program, such as a firmware translation layer (FTL) in the device end, a driver for specific hardware, etc. In addition, it can also be implemented in other types of programs as shown above. Those skilled in the art can write the method of the embodiment of the present invention into program code, which will not be described again for the sake of simplicity. The computer program implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer-readable storage medium, or it can be placed on a network server that can be accessed through a network (e.g., the Internet, or other appropriate media).

[0124] Computer-readable storage media include volatile and non-volatile, removable and non-removable media that implement the storage of information, such as computer-readable instructions, data structures, program modules, or other data, using any method or technology. Computer-readable storage media include but are not limited to RAM, ROM, EEPROM, flash memory or other memory, CD-ROM, DVD, Blu-ray disc or other optical storage media, magnetic cards, magnetic tape, hard disk or other magnetic storage media, or other carriers that can be used to store information required and accessed by the instruction execution system. It should be noted that the computer-readable storage medium can be paper or other suitable media for printing program code so that the program code can be obtained electronically, such as by optically scanning the paper or other media, and then, if necessary, compiled, interpreted or processed in other suitable ways, and then stored in the memory of the electronic device.

[0125] The program code may be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits, field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Such a processor may be configured to perform any of the techniques described in the disclosure. A general-purpose processor may be a microprocessor; however, in an alternative embodiment, the processor may be any conventional processor, controller, microprocessor, or state machine. The processor may be implemented as a combination of multiple computing devices, such as a DSP and a microprocessor, multiple microprocessors, one or more microprocessors with a DSP core, or any other similar configuration. Accordingly, the term "processor" as used herein may represent any of the foregoing structures, any combination of the foregoing structures, or any other structure or device suitable for implementing the counting described herein.

[0126] The various illustrative logic blocks, modules, engines, circuits, and algorithmic steps described in conjunction with the inventive aspects disclosed herein may be implemented as electronic hardware, computer software, firmware, or any combination thereof. In order to clearly represent the interchangeability of hardware and software, various illustrative components, blocks, modules, engines, circuits, and steps have been generally described above in terms of their functions. Whether these functions are to be implemented in hardware or software depends on the specific application scenario and the design constraints imposed on the entire system. Those of ordinary skill in the art may implement the described functions in different ways for each specific application scenario, but such implementation decisions should not be interpreted as departing from the scope of this application.

[0127] Although Figures 1 to 3The components described above are included in the invention, but it does not exclude the use of more additional components to achieve better technical effects without violating the spirit of the invention. Figure 7 、 Figure 8A and Figure 8B The flowchart is executed in the specified order. However, those skilled in the art may modify the order of these steps without violating the spirit of the invention, provided that the same effect is achieved. Therefore, the present invention is not limited to the above-described order. In addition, those skilled in the art may also combine several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention should not be limited thereby.

[0128] The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Those skilled in the art may make further improvements and changes on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the content defined in the claims of this application.

Claims

1. A garbage collection method in a flash memory device, executed by a processing unit, characterized in that: The garbage collection method in the flash memory device includes: sorting the plurality of data blocks according to valid page counts of the plurality of data blocks, and selecting a default number of sorted data blocks starting from the data block with the smallest valid page count as a plurality of source blocks; Finding a source block corresponding to a first cumulative valid page count that is greater than the total number of physical pages of a destination block according to the sorted cumulative valid page counts of the plurality of source blocks; marking the found source block and subsequent source blocks as first type source blocks; marking source blocks other than the first type source blocks as second type source blocks; Obtaining one or more host-flash mapping sub-tables associated with the first valid page stored in the second-type source block; In each scan of the host-flash memory reference sub-table, a plurality of second valid pages stored in the first type source block and the second type source block are detected in the order of the logical addresses in the host-flash memory reference sub-table, and a plurality of records are added to a garbage collection data table for the plurality of second valid pages, wherein each record stores information that user data from a specific physical page in a specific first type source block or a specific second type source block is written to a specific physical page in the destination block, and the total number of the records associated with the first type source block in the garbage collection data table is less than or equal to the difference between the total number of physical pages of the one destination block and the total number of valid page counts of the second type source blocks; and The user data of the specific physical page in the specific first type source block or the specific second type source block is written to the specific physical page in the destination block according to each record in the garbage collection data table, so that the second type source block can be erased in the future to store new user data.

2. The garbage collection method in a flash memory device according to claim 1, wherein: include: The valid page count of each data block is locally read from metadata of a designated physical page of the data block in the flash memory module.

3. The garbage collection method in a flash memory device according to claim 1, wherein: include: The valid page count of each data block is locally read from metadata of the last physical page of this data block in the flash memory module.

4. The garbage collection method in a flash memory device according to claim 1, wherein: include: Read the valid page count table from the specified physical address in the flash memory module; as well as The valid page counts of the plurality of data blocks are obtained from the valid page count table.

5. The garbage collection method in a flash memory device according to claim 1, wherein: The default number of sorted data blocks is 16 data blocks.

6. The garbage collection method in a flash memory device according to claim 1, wherein: Each of the host-flash mapping sub-tables stores the physical address information mapped by each of the logical addresses in the order of multiple logical addresses in a logical address range.

7. The garbage collection method in a flash memory device according to claim 6, wherein: Each of the logical addresses is a logical block address number.

8. A computer-readable storage medium for storing program code that can be executed by a processing unit, characterized in that: When the program code is executed by the processing unit, the garbage collection method in the flash memory device according to any one of claims 1 to 7 is implemented.

9. A garbage collection device in a flash memory device, characterized in that: include: A flash memory interface, coupled to the flash memory module; as well as a processing unit coupled to the flash memory interface and configured to sort the plurality of data blocks in the flash memory module according to valid page counts of the plurality of data blocks, and select a default number of sorted data blocks starting from the data block with the smallest valid page count as a plurality of source blocks; According to the accumulated valid page counts of the sorted plurality of source blocks, a source block corresponding to the first accumulated valid page count that is greater than the total number of physical pages of a destination block is found; the found source block and subsequent source blocks are marked as first type source blocks; source blocks other than the first type source block are marked as second type source blocks; one or more host-flash memory comparison sub-tables associated with the first valid page stored in the second type source block are obtained; in a scan of each of the host-flash memory comparison sub-tables, a plurality of second valid pages stored in the first type source block and the second type source block are detected in the order of the logical addresses in the host-flash memory comparison sub-table, and a plurality of records are added to the garbage collection data table for the plurality of second valid pages, wherein each of the records stores a specific first type source block in the flash memory module Or information on the user data of a specific physical page in a specific second type source block is rewritten to the specific physical page in the destination block in the flash memory module, and the total number of the records associated with the first type source block in the garbage collection data table is less than or equal to the difference between the total number of physical pages of the one destination block and the total number of valid page counts of the second type source block; and driving the flash memory interface according to each record in the garbage collection data table to rewrite the user data of the specific first type source block or the specific physical page in the specific second type source block in the flash memory module to the specific physical page in the destination block in the flash memory module, so that the second type source block can be erased in the future to store new user data.

10. The garbage collection device in the flash memory device according to claim 9, wherein: The processing unit is configured to drive the flash memory interface to locally read the valid page count of each data block in the flash memory module from metadata of a designated physical page of the data block.

11. The garbage collection device in the flash memory device according to claim 9, wherein: The processing unit is configured to drive the flash memory interface to locally read the valid page count of each data block in the flash memory module from metadata of the last physical page of the data block.

12. The garbage collection device in the flash memory device according to claim 9, wherein: The processing unit is configured to drive the flash memory interface to read a valid page count table from a designated physical address in the flash memory module; and obtain the valid page counts of the plurality of data blocks from the valid page count table.

13. The garbage collection device in the flash memory device according to claim 9, wherein: The default number of sorted data blocks is 16 data blocks.

14. The garbage collection device in the flash memory device according to claim 9, wherein: Each of the host-flash mapping sub-tables stores the physical address information mapped by each of the logical addresses in the order of multiple logical addresses in a logical address range.

15. The garbage collection device in the flash memory device according to claim 14, wherein: Each of the logical addresses is a logical block address number.

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