Matrix dimension reduction circuit and system based on singular value decomposition

Abstract

The invention discloses a matrix dimension reduction circuit and system based on singular value decomposition, and relates to the technical field of singular value decomposition. The circuit comprises a first on-chip cache unit used for obtaining and caching a matrix to be subjected to dimension reduction; the matrix decomposition calculation unit is connected with the first on-chip cache unit and is used for performing singular value decomposition on the matrix to be subjected to dimension reduction to obtain a first singular value matrix and a first right singular matrix; the matrix dimension reduction unit is connected with the matrix decomposition calculation unit, and is used for performing dimension reduction processing on the first singular value matrix and the first right singular matrix to obtain a second singular value matrix and a second right singular matrix, and obtaining a left singular matrix according to the matrix to be subjected to dimension reduction and the second right singular matrix; obtaining a dimension reduction matrix according to the second singular value matrix, the left singular matrix and the second right singular matrix; and the second on-chip cache unit is connected with the matrix dimension reduction unit and is used for caching and outputting the dimension reduction matrix.

Description

Technical Field

[0001] The present invention relates to the technical field of singular value decomposition, and in particular to a matrix dimension reduction circuit and system based on singular value decomposition. Background Art

[0002] Singular value decomposition plays an important role in artificial intelligence algorithms, especially in tasks such as dimensionality reduction and feature extraction. Matrices can be decomposed into corresponding singular values and eigenvectors through singular value decomposition. The singular values of a matrix are usually used to describe the characteristics and properties of the matrix. However, the mainstream solutions for performing singular value decomposition in related technologies mainly rely on CPUs (Central Processing Units) and GPUs (Graphics Processing Units). When using the CPU for singular value decomposition operations, a large number of multiplication and addition operations are involved. Such operations usually require hundreds or even thousands of clock cycles to complete, which greatly reduces the CPU's computing efficiency, especially when facing large-scale sparse matrices. When using GPUs for singular value decomposition operations, due to the high power consumption of GPUs, especially when performing singular value decomposition of sparse matrices, due to a large number of ineffective calculations, its energy efficiency is further reduced, making it difficult for GPUs to be used in power-sensitive scenarios (such as IoT devices and edge computing) for a long time. Summary of the Invention

[0003] The present invention aims to at least partially solve one of the technical problems in the related art. To this end, a first object of the present invention is to provide a matrix dimensionality reduction circuit based on singular value decomposition to avoid reducing CPU efficiency and to be usable in power-sensitive scenarios.

[0004] The second object of the present invention is to propose a matrix dimensionality reduction system based on singular value decomposition.

[0005] To achieve the above-mentioned objectives, an embodiment of the first aspect of the present invention proposes a matrix dimensionality reduction circuit based on singular value decomposition, the circuit comprising: a first on-chip cache unit, for acquiring and caching the matrix to be reduced in dimension; a matrix decomposition calculation unit, connected to the first on-chip cache unit, for performing singular value decomposition on the matrix to be reduced in dimension to obtain a first singular value matrix and a first right singular matrix; a matrix dimensionality reduction unit, connected to the matrix decomposition calculation unit, for performing dimensionality reduction processing on the first singular value matrix and the first right singular matrix to obtain a second singular value matrix and a second right singular matrix, and obtaining a left singular matrix based on the matrix to be reduced in dimension and the second right singular matrix, and obtaining a reduced dimension matrix based on the second singular value matrix, the left singular matrix and the second right singular matrix; a second on-chip cache unit, connected to the matrix dimensionality reduction unit, for caching and outputting the reduced dimension matrix.

[0006] In addition, the matrix dimensionality reduction circuit based on singular value decomposition according to an embodiment of the present invention also has the following additional technical features:

[0007] According to one embodiment of the present invention, the matrix to be reduced in dimension is a sparse matrix, and the first on-chip cache unit is specifically used to: obtain a numerical array, a row index array and column offset data according to the matrix to be reduced in dimension, and cache the numerical array, the row index array and the column offset array, wherein the numerical array includes the non-zero elements in the matrix to be reduced in dimension, the row index array includes the row index corresponding to each non-zero element in the numerical array in the matrix to be reduced in dimension, and the column offset array includes the position of the first non-zero element of each column in the matrix to be reduced in dimension in the numerical array.

[0008] According to one embodiment of the present invention, the matrix decomposition calculation unit includes: a decomposition module, which is used to obtain the matrix to be reduced in dimension, obtain the matrix to be decomposed based on the matrix to be reduced in dimension, and decompose the matrix to be decomposed into the form of an orthogonal matrix multiplied by an upper triangular matrix, and send the orthogonal matrix and the upper triangular matrix to a singular value update and extraction module; the singular value update and extraction module, which is used to calculate the upper triangular matrix multiplied by the orthogonal matrix, use the multiplication result as the new matrix to be decomposed, and output the new matrix to be decomposed to the decomposition module, and after the singular value update and extraction module performs a preset number of multiplication calculations, obtain the singular values of the matrix to be reduced in dimension according to the latest multiplication results, and obtain the first singular value matrix and the first right singular matrix according to the singular values and all the obtained orthogonal matrices.

[0009] According to one embodiment of the present invention, the decomposition module includes: a vector calculation submodule, which is used to calculate the sum of the squares of all elements in each column of the matrix to be reduced in dimension to obtain a first binary norm, and perform square root processing on the first binary norm, determine the positive or negative of the first binary norm after the square root according to the positive or negative of the first row element in the column to obtain a second binary norm, and add the second binary norm to each element in the column to obtain a reflection vector according to the addition result; a normalization submodule, which is connected to the vector calculation submodule, and is used to calculate the sum of the squares of all elements in the reflection vector for each of the reflection vectors. The third quadratic norm is obtained by summing the squares of the elements, and each element in the reflection vector is divided by the third quadratic norm to obtain a normalized vector; a reflection submodule is connected to the normalization submodule, and is used to obtain the transposed vector of the normalized vector for each normalized vector, and obtain the product of the normalized vector and the transposed vector, construct an initial matrix according to the product, and generate a reflection matrix according to the initial matrix and a preset unit matrix; a decomposition submodule is connected to the reflection submodule, and is used to obtain the orthogonal matrix and the upper triangular matrix according to the reflection matrix and the matrix to be reduced in dimensionality.

[0010] According to one embodiment of the present invention, the vector calculation submodule includes: a first multiplier, the input end of the first multiplier is designed as the first input end of the vector calculation submodule, used to obtain the matrix to be reduced in dimension and calculate the square of each element in the matrix to be reduced in dimension; a first accumulator, the input end of the first accumulator is connected to the output end of the first multiplier, used to obtain the sum of squares according to the squares of all elements in the column for each column in the matrix to be reduced in dimension; a square rooter, the input end of the square rooter is connected to the output end of the first accumulator, used to perform square root processing on the sum of squares corresponding to each column in the matrix to be reduced in dimension to obtain the first bi-norm corresponding to the column; a comparator, the input end of the comparator is designed as the second input end of the vector calculation submodule, used to obtain the matrix to be reduced in dimension and calculate the square of each element in the matrix to be reduced in dimension. Obtain the comparator output result corresponding to the column, wherein when the non-zero element with the smallest number of rows in the column is greater than zero, the comparator output result corresponding to the column is 1, and when the non-zero element with the smallest number of rows in the column is less than zero, the comparator output result corresponding to the column is -1; a second multiplier, wherein the first input end of the second multiplier is connected to the output end of the square root generator, and the second input end of the second multiplier is connected to the output end of the comparator, for multiplying each of the first second norms with the corresponding comparator output result to obtain a second second norm; an adder, wherein the first input end of the adder is connected to the input end of the first multiplier, and the second input end of the adder is connected to the output end of the multiplier, for adding each element in each column of the matrix to be reduced in dimension with the second second norm corresponding to the column, and obtaining a reflection vector according to the addition result.

[0011] According to one embodiment of the present invention, the normalization submodule includes: a third multiplier, the input end of the third multiplier is designed as the input end of the normalization submodule, used to obtain the reflection vector and calculate the square of each element in the reflection vector; a second accumulator, the input end of the second accumulator is connected to the output end of the third multiplier, used to obtain the sum of squares according to the squares of all elements in the reflection vector to obtain the third second norm; a divider, the first input end of the divider is connected to the output end of the second accumulator, the second input end of the divider is connected to the input end of the third multiplier, and the output end of the divider is designed as the output end of the normalization submodule, used to divide each element in the reflection vector by the third second norm to obtain the normalized vector.

[0012] According to one embodiment of the present invention, the reflection submodule includes: a transposer, wherein the input end of the transposer is set as the first input end of the reflection submodule, for obtaining the transposed vector of the normalized vector; a fourth multiplier, wherein the first input end of the fourth multiplier is connected to the output end of the transposer, and the second input end of the fourth multiplier is designed as the second input end of the reflection submodule, and the fourth multiplier is used to obtain the normalized vector and the transposed vector, and multiply the normalized vector and the transposed vector to obtain a first initial matrix; a third accumulator, wherein the input end of the third accumulator is connected to the output end of the fourth multiplier, and is used to add the first initial matrix to itself to obtain a second initial matrix; a subtractor, wherein the first input end of the subtractor is connected to the output end of the third accumulator, and the second input end of the subtractor is designed as the third input end of the reflection submodule, for obtaining the second initial matrix and the preset unit matrix, and subtracting the second initial matrix from the preset unit matrix to obtain the reflection matrix.

[0013] According to one embodiment of the present invention, the circuit also includes: a controller, connected to the first on-chip cache unit, the matrix decomposition calculation unit, the matrix dimensionality reduction unit and the second on-chip cache unit, used to control the first on-chip cache unit to obtain and cache the matrix to be reduced in dimension, control the matrix decomposition unit to perform singular value decomposition on the matrix to be reduced in dimension to obtain a first singular value matrix and a first right singular matrix, control the matrix dimensionality reduction unit to obtain the reduced dimensionality matrix based on the first singular value matrix and the first right singular matrix, and control the second on-chip cache unit to cache and output the reduced dimensionality matrix.

[0014] According to one embodiment of the present invention, the circuit also includes: a general computing unit, connected to the matrix decomposition computing unit and the matrix dimensionality reduction unit, the general computing unit includes multiple computing sub-units, so that the matrix decomposition computing unit and the matrix dimensionality reduction unit call the computing sub-units to perform corresponding calculations, wherein the multiple computing sub-units include a multiplication sub-unit, a square root sub-unit, and a division sub-unit.

[0015] To achieve the above-mentioned purpose, a second embodiment of the present invention proposes a matrix dimensionality reduction system based on singular value decomposition, including the above-mentioned matrix dimensionality reduction circuit based on singular value decomposition.

[0016] According to an embodiment of the present invention, a matrix dimensionality reduction circuit and system based on singular value decomposition includes a first on-chip cache unit for acquiring and caching a matrix to be reduced; a matrix decomposition calculation unit, connected to the first on-chip cache unit, for performing singular value decomposition on the matrix to be reduced to obtain a first singular value matrix and a first right singular matrix; a matrix dimensionality reduction unit, connected to the matrix decomposition calculation unit, for performing dimensionality reduction processing on the first singular value matrix and the first right singular matrix to obtain a second singular value matrix and a second right singular matrix, and obtaining a left singular matrix based on the matrix to be reduced and the second right singular matrix, and obtaining a reduced dimensionality matrix based on the second singular value matrix, the left singular matrix, and the second right singular matrix; and a second on-chip cache unit, connected to the matrix dimensionality reduction unit, for caching and outputting the reduced dimensionality matrix. This configuration enables singular value decomposition to be performed using a separate matrix decomposition calculation unit, eliminating the need for CPU, GPU, or other devices, freeing up resources for other tasks. This significantly improves the overall efficiency of the system, avoids reducing CPU efficiency, and can also be used in power-sensitive scenarios.

[0017] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 1 is a structural block diagram of a matrix dimensionality reduction circuit based on singular value decomposition according to an embodiment of the present invention;

[0019] Figure 2 This is a flowchart of a matrix dimensionality reduction circuit based on singular value decomposition according to an example of the present invention;

[0020] Figure 3 1 is a schematic structural diagram of a matrix dimensionality reduction circuit based on singular value decomposition according to an embodiment of the present invention;

[0021] Figure 4 1 is a schematic structural diagram of a vector calculation submodule according to an embodiment of the present invention;

[0022] Figure 5 1 is a schematic structural diagram of a normalization submodule according to an embodiment of the present invention;

[0023] Figure 6 is a schematic structural diagram of a reflection submodule according to an embodiment of the present invention;

[0024] Figure 7 It is a structural block diagram of a matrix dimensionality reduction system based on singular value decomposition according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following describes a circuit and system for matrix dimensionality reduction based on singular value decomposition according to an embodiment of the present invention with reference to the accompanying drawings. The same or similar reference numerals throughout the description represent the same or similar elements or elements having the same or similar functions. The embodiments described with reference to the accompanying drawings are exemplary only and are not to be construed as limiting the present invention.

[0026] Figure 1 It is a structural block diagram of a matrix dimensionality reduction circuit based on singular value decomposition according to an embodiment of the present invention.

[0027] like Figure 1 As shown, the matrix dimensionality reduction circuit 100 based on singular value decomposition includes: a first on-chip cache unit 101, used to obtain and cache the matrix to be reduced in dimension; a matrix decomposition calculation unit 102, connected to the first on-chip cache unit 101, used to perform singular value decomposition on the matrix to be reduced in dimension to obtain a first singular value matrix and a first right singular matrix; a matrix dimensionality reduction unit 103, connected to the matrix decomposition calculation unit 102, used to perform dimensionality reduction processing on the first singular value matrix and the first right singular matrix to obtain a second singular value matrix and a second right singular matrix, and obtain a left singular matrix according to the matrix to be reduced in dimension and the second right singular matrix, and obtain a reduced dimension matrix according to the second singular value matrix, the left singular matrix and the second right singular matrix; a second on-chip cache unit 104, connected to the matrix dimensionality reduction unit 103, used to cache and output the reduced dimension matrix.

[0028] Specifically, a matrix dimensionality reduction circuit 100 based on singular value decomposition is provided, including a first on-chip cache unit 101, a matrix decomposition calculation unit 102, a matrix dimensionality reduction unit 103, and a second on-chip cache unit 104. When matrix dimensionality reduction is required, an external device sends the matrix to be reduced to the first on-chip cache unit 101, and the first on-chip cache unit 101 obtains and caches the matrix to be reduced.

[0029] After caching the matrix to be reduced in dimension, the first on-chip cache unit 101 needs to send the matrix to be reduced in dimension to the matrix decomposition calculation unit 102. The matrix decomposition calculation unit 102 performs singular value decomposition on the matrix to be reduced in dimension to obtain a first singular value matrix, a first left singular matrix and a first right singular matrix.

[0030] That is to say, the above-mentioned matrix dimensionality reduction circuit 100 based on singular value decomposition uses a separately set matrix decomposition calculation unit 102 to perform singular value decomposition, without the participation of devices such as CPU and GPU, which can free up resources to process other tasks and significantly improve the overall efficiency of the system.

[0031] After obtaining the singular value matrix, the first left singular matrix, and the first right singular matrix, the singular value matrix, the first left singular matrix, and the first right singular matrix are sent to the matrix dimensionality reduction unit 103 .

[0032] The matrix dimensionality reduction unit 103 performs dimensionality reduction processing on the singular value matrix, the first left singular matrix, and the first right singular matrix to obtain a second singular value matrix, a left singular matrix, and a second right singular matrix. Then, based on the second singular value matrix, the left singular matrix, and the second right singular matrix, a reduced dimensionality matrix can be obtained after reducing the dimensionality of the above-mentioned matrix to be reduced. The second on-chip cache unit 104 caches and outputs the reduced dimensionality matrix.

[0033] Thus, a matrix dimensionality reduction circuit 100 based on singular value decomposition is provided, comprising a first on-chip cache unit 101 for acquiring and caching a matrix to be reduced; a matrix decomposition calculation unit 102, connected to the first on-chip cache unit 101, for performing singular value decomposition on the matrix to be reduced to obtain a first singular value matrix and a first right singular matrix; a matrix dimensionality reduction unit 103, connected to the matrix decomposition calculation unit 102, for performing dimensionality reduction processing on the first singular value matrix and the first right singular matrix to obtain a second singular value matrix and a second right singular matrix, and obtaining a left singular matrix based on the matrix to be reduced and the second right singular matrix, and obtaining a reduced dimensionality matrix based on the second singular value matrix, the left singular matrix, and the second right singular matrix; and a second on-chip cache unit 104, connected to the matrix dimensionality reduction unit 103, for caching and outputting the reduced dimensionality matrix. This configuration enables singular value decomposition to be performed using a separate matrix decomposition calculation unit 102, eliminating the need for CPU, GPU, and other devices, freeing up resources for processing other tasks and significantly improving the overall efficiency of the system.

[0034] In some embodiments of the present invention, the matrix to be reduced in dimensionality is a sparse matrix, and the first on-chip cache unit 101 is specifically used to: obtain a numerical array, a row index array, and column offset data according to the matrix to be reduced in dimensionality, and cache the numerical array, the row index array, and the column offset array, wherein the numerical array includes the non-zero elements in the matrix to be reduced in dimensionality, the row index array includes the row index corresponding to each non-zero element in the numerical array in the matrix to be reduced in dimensionality, and the column offset array includes the position of the first non-zero element of each column in the matrix to be reduced in the numerical array.

[0035] That is to say, in order to cache the sparse matrix, the first on-chip cache unit 101 is configured to divide the sparse matrix into three arrays for storage after obtaining the sparse matrix: 1. Numerical array: stores all non-zero elements in the matrix to be reduced in dimension, arranged in row priority order. This array records all meaningful numerical values in the sparse matrix, thereby avoiding the storage of zero elements. 2. Row index array: stores the row index corresponding to each non-zero element in the matrix to be reduced in dimension. For each non-zero element, its row index will be recorded in the array, which is used to accurately locate the row position in the matrix during calculation. 3. Column offset array: used to identify the position of the first non-zero element of each column of the matrix to be reduced in dimension in the numerical array. The value of the corresponding bit of the column offset array represents the position of the first non-zero element of the column in the numerical array, and the last value of the column offset represents the total number of non-zero elements in the matrix.

[0036] In some embodiments of the present invention, the matrix decomposition calculation unit 102 includes: a decomposition module, which is used to obtain the matrix to be reduced in dimension, obtain the matrix to be decomposed based on the matrix to be reduced in dimension, and decompose the matrix to be decomposed into the form of an orthogonal matrix multiplied by an upper triangular matrix, and send the orthogonal matrix and the upper triangular matrix to the singular value update and extraction module; a singular value update and extraction module, which is used to calculate the upper triangular matrix multiplied by the orthogonal matrix, use the multiplication result as the new matrix to be decomposed, and output the new matrix to be decomposed to the decomposition module, and after the singular value update and extraction module performs a preset number of multiplication calculations, obtain the singular values of the matrix to be reduced in dimension based on the latest multiplication results, and obtain the first singular value matrix and the first right singular matrix based on the singular values and all the orthogonal matrices obtained.

[0037] The following describes the process in conjunction with a specific embodiment.

[0038] Specifically, in order to implement singular value decomposition of the matrix A to be reduced in dimension, the matrix decomposition calculation unit 102 is configured to include a decomposition module and a singular value updating and extraction module.

[0039] After the first on-chip cache unit 101 sends the matrix A to be reduced in dimension to the matrix decomposition calculation unit 102 , the decomposition module in the matrix decomposition calculation unit 102 obtains the matrix A to be reduced in dimension, and obtains the matrix B to be decomposed based on the matrix A to be reduced in dimension.

[0040] In order to obtain the matrix B to be decomposed based on the matrix A to be reduced in dimension, the following method can be used:

[0041] B=A T A=R T Q T QR=R T R,

[0042] Wherein, Q is the second orthogonal matrix, and R is the second upper triangular matrix.

[0043] That is to say, after the decomposition module obtains the matrix A to be reduced in dimension, it decomposes the matrix A to be reduced in dimension into the form of an orthogonal matrix multiplied by an upper triangular matrix, and then obtains the matrix B to be decomposed by referring to the above. In this way, it is possible to avoid running A T A is a computation that takes up a lot of space, especially when the matrix A to be reduced is a sparse matrix. T A will take up a lot of space.

[0044] After obtaining the matrix B to be decomposed, the decomposition module decomposes the matrix B to be decomposed to obtain the orthogonal matrix Q B and the upper triangular matrix R B , B=Q B ×R B , and the orthogonal matrix Q B and the upper triangular matrix R B Sent to the singular value update and extraction module.

[0045] The singular value update and extraction module receives the orthogonal matrix Q B and the upper triangular matrix R B Then, the upper triangular matrix R B Multiply by the orthogonal matrix Q B , the multiplication result B1 is used as the new matrix to be decomposed, that is, B1 = R B ×Q B The new matrix to be decomposed B1 is sent to the decomposition module, and the decomposition module decomposes the matrix to be decomposed B1 to obtain a new orthogonal matrix Q B1 and the new upper triangular matrix R B1 , B1=Q B1 ×R B1 , and the orthogonal matrix Q B1 and the upper triangular matrix R B1 Send it to the singular value update and extraction module, which updates the upper triangular matrix R B1 Multiply by the orthogonal matrix Q B1 , the multiplication result B2 is used as the new matrix to be decomposed, that is, B2 = R B1 ×Q B1 The new matrix to be decomposed B2 is sent to the decomposition module. This is repeated until the iteration requirement is met. The iteration requirement is that the singular value update and extraction module performs a preset number of multiplication calculations to obtain the latest multiplication result B n , n is the preset number of times. The latest multiplication result B n is an approximately diagonal matrix.

[0046] After getting the latest multiplication result B n After that, because the B n is an approximately diagonal matrix, so we can get the B nThe eigenvalue of , the number of eigenvalues can be more than one, and the eigenvalue is AA T , and then take the square root of the eigenvalue to get σ, which is the singular value of the matrix A to be reduced in dimension.

[0047] After the singular values are obtained, the first singular value matrix, the first left singular matrix, and the first right singular matrix can be obtained according to the singular values and all the obtained orthogonal matrices.

[0048] For example, in order to obtain the first singular value matrix, the diagonal elements of the first singular value matrix can be set as singular values, and the other elements can be set to zero, and the diagonal elements of the first singular value matrix decrease continuously as the number of rows and columns increases.

[0049] In order to obtain the first right singular matrix, all orthogonal matrices Q obtained in the above iterative process of the decomposed matrix B can be obtained B , Q B1 , Q B2 ..., multiply all orthogonal matrices to obtain the eigenvector matrix Q n , and the eigenvector matrix Q n as the first right singular matrix.

[0050] After obtaining the first singular value matrix and the first right singular matrix, since the singular value decomposition follows the following rules: A=UΣV T , where U is the first left singular matrix, Σ is the first singular value matrix, and V is the first right singular matrix. Therefore, the first left singular matrix can be directly calculated.

[0051] See also Figure 2 After obtaining the input matrix A, first perform QR decomposition on A to obtain the second orthogonal matrix and the second upper triangular matrix. Perform matrix multiplication based on the second upper triangular matrix to obtain the matrix to be decomposed B. Perform QR iteration on the matrix to be decomposed B to determine whether the iteration requirements are met. If the iteration requirements are not met, perform QR decomposition on the matrix to be decomposed B to obtain an orthogonal matrix and an upper triangular matrix. Then perform matrix multiplication based on the orthogonal matrix and the upper triangular matrix to obtain a new matrix to be decomposed B, that is, the matrix to be decomposed B1. Then determine whether the iteration requirements are met. If the iteration requirements are not met, perform QR decomposition on the matrix to be decomposed B1 to obtain an orthogonal matrix and an upper triangular matrix. Then perform matrix multiplication based on the orthogonal matrix and the upper triangular matrix to obtain a new matrix to be decomposed B, that is, the matrix to be decomposed B2. This process is repeated until the iteration requirements are met and the approximate diagonal matrix B is obtained. n and the eigenvector matrix Q n .

[0052] In some embodiments of the present invention, the decomposition module includes: a vector calculation submodule, which is used to calculate the sum of the squares of all elements in each column of the matrix to be reduced in dimension to obtain a first and second norm, and perform square root processing on the first and second norms, determine the positive and negative of the first and second norms after the square root according to the positive and negative of the first row elements in the column, and obtain a second and second norm, and add the second and second norms to each element in the column to obtain a reflection vector according to the addition result; a normalization submodule, which is connected to the vector calculation submodule, and is used to calculate the sum of the squares of all elements in the column for each reflection vector. The square sum of all elements in the reflection vector is obtained to obtain the third quadratic norm, and each element in the reflection vector is divided by the third quadratic norm to obtain a normalized vector; the reflection submodule is connected to the normalization submodule, and is used to obtain the transposed vector of the normalized vector for each normalized vector, and obtain the product of the normalized vector and the transposed vector, construct an initial matrix based on the product, and generate a reflection matrix based on the initial matrix and a preset unit matrix; the decomposition submodule is connected to the reflection submodule, and is used to obtain an orthogonal matrix and an upper triangular matrix based on the reflection matrix and the matrix to be reduced in dimensionality.

[0053] In some embodiments of the present invention, the above-mentioned vector calculation submodule includes: a first multiplier, the input end of the first multiplier is designed as the first input end of the vector calculation submodule, used to obtain the matrix to be reduced in dimension and calculate the square of each element in the matrix to be reduced in dimension; a first accumulator, the input end of the first accumulator is connected to the output end of the first multiplier, used to obtain the sum of squares according to the squares of all elements in each column in the matrix to be reduced in dimension; a square rooter, the input end of the square rooter is connected to the output end of the first accumulator, used to perform square root processing on the sum of squares corresponding to each column in the matrix to be reduced in dimension, and obtain the first and second norms corresponding to the column; a comparator, the input end of the comparator is designed as the second input end of the vector calculation submodule, used to obtain the matrix to be reduced in dimension and obtain the first and second norms corresponding to the column for each column in the matrix to be reduced in dimension. to the comparator output result corresponding to the column, wherein when the non-zero element with the smallest number of rows in the column is greater than zero, the comparator output result corresponding to the column is 1, and when the non-zero element with the smallest number of rows in the column is less than zero, the comparator output result corresponding to the column is -1; a second multiplier, a first input end of the second multiplier is connected to the output end of the square root, a second input end of the second multiplier is connected to the output end of the comparator, for multiplying each first second norm by the corresponding comparator output result to obtain a second second norm; an adder, a first input end of the adder is connected to the input end of the first multiplier, a second input end of the adder is connected to the output end of the multiplier, for adding each element in each column of the matrix to be reduced in dimension with the second second norm corresponding to the column, and obtaining a reflected vector according to the addition result.

[0054] Take the jth column of the matrix to be reduced as an example. The jth column of the matrix to be reduced can be regarded as a column vector Aj .

[0055] Specifically, a first multiplier is used to square each element in the j-th column, and then a first accumulator is used to sum all the square results to obtain a first square sum corresponding to the j-th column, and then a square root operation is performed on the first square sum through a square rooter to obtain a first quadratic norm.

[0056] Furthermore, a comparator is provided to obtain the non-zero element with the smallest number of rows in the j-th column of the matrix to be reduced, compare the element with zero, and output 1 if the element is greater than 0, and -1 if the element is less than 0. In this way, sign judgment can be achieved.

[0057] The second multiplier multiplies the first second norm by the value output by the comparator to obtain a second second norm.

[0058] The adder adds each element in the j-th column of the matrix to be reduced to the second quadratic norm. Since the j-th column of the matrix to be reduced can be regarded as an n-dimensional column vector, n is the number of rows of the matrix to be reduced. Therefore, after adding the second quadratic norm to each element in the j-th column of the matrix to be reduced, it can be regarded as adding each element of an n-dimensional column vector to a fixed value, and the addition result is an n-dimensional column vector. The n-dimensional column vector obtained by the addition can then be used as a reflection vector.

[0059] The above operation is performed on each column of the matrix to be reduced in dimensionality, and a plurality of reflection vectors can be obtained. The number of the reflection vectors is the same as the number of columns of the matrix to be reduced in dimensionality.

[0060] In some embodiments of the present invention, the above-mentioned normalization submodule includes: a third multiplier, the input end of the third multiplier is designed as the input end of the normalization submodule, used to obtain the reflection vector and calculate the square of each element in the reflection vector; a second accumulator, the input end of the second accumulator is connected to the output end of the third multiplier, used to obtain the sum of squares based on the squares of all elements in the reflection vector, and obtain a third second norm; a divider, the first input end of the divider is connected to the output end of the second accumulator, the second input end of the divider is connected to the input end of the third multiplier, and the output end of the divider is designed as the output end of the normalization submodule, used to divide each element in the reflection vector by the third second norm to obtain a normalized vector.

[0061] Specifically, after the reflected vector is sent into the normalization module, for each reflected vector, each element in the reflected vector is squared through the third multiplier, and then the square of each element in the reflected vector is summed through the second accumulator to obtain the vector norm, which is the third second norm, and each element in the reflected vector is divided by the third second norm using a divider to obtain a normalized vector.

[0062] In some embodiments of the present invention, the above-mentioned reflection submodule includes: a transposer, the input end of the transposer is set to the first input end of the reflection submodule, for obtaining the transposed vector of the normalized vector; a fourth multiplier, the first input end of the fourth multiplier is connected to the output end of the transposer, the second input end of the fourth multiplier is designed as the second input end of the reflection submodule, the fourth multiplier is used to multiply the normalized vector and the transposed vector to obtain a first initial matrix; a third accumulator, the input end of the third accumulator is connected to the output end of the fourth multiplier, for adding the first initial matrix to itself to obtain a second initial matrix; a subtractor, the first input end of the subtractor is connected to the output end of the third accumulator, the second input end of the subtractor is designed as the third input end of the reflection submodule, for obtaining the second initial matrix and a preset unit matrix, and subtracting the second initial matrix from the preset unit matrix to obtain a reflection matrix.

[0063] Specifically, a transposer is provided to perform device processing on the normalized vector after receiving the normalized vector to obtain a transposed vector of the normalized vector.

[0064] After obtaining the transposed vector, for each normalized vector, the normalized vector is multiplied by the corresponding transposed vector to obtain a first initial matrix.

[0065] It should be noted that, since the above-mentioned normalized vector is a vector obtained by dividing each element of the reflected vector by the third quadratic norm, and the reflected vector is a vector obtained by treating a column in the matrix to be reduced as a column vector and adding the column vector to the second quadratic norm, that is, the above-mentioned normalized vector is a column vector, therefore, the multiplication result of the normalized vector and the reflected vector is a matrix, that is, the first initial matrix, and the number of rows and columns of the first initial matrix are both the number of rows of the above-mentioned matrix to be reduced.

[0066] After obtaining the first initial matrix, the first initial matrix is input into the third accumulator, added to itself, and then input into the subtractor to obtain the reflection matrix H. j , H j =I-2uu T . Among them, u is the normalized vector, u T is the transposed vector of the normalized vector, and I is the preset identity matrix.

[0067] In some embodiments of the present invention, the submodules are decomposed and H j The matrix A to be reduced is sent to the multiplier and accumulator to obtain the reflected new matrix A ′ . Perform similar operations on each column of matrix A until the upper triangular matrix R is obtained. Then send the R matrix and the H matrix into the multiplier and accumulator to obtain the diagonal matrix Q.

[0068] Among them, in order to obtain the new matrix A after the above reflection′ , set H in the multiplier and accumulator j ×A, get the new matrix A after reflection ′ , through the reflection operation, the new matrix A can be ′ Set all elements below the diagonal of column j to 0.

[0069] In order to achieve the above similar operation on each column of matrix A, taking column j+1 as an example, the above household transformation is performed on column j+1 of the new matrix A' to obtain H j+1 , H j+1 With A ′ Multiply them to obtain a further iterative matrix A″, in which the elements below the diagonal of the j+1 column of the matrix are 0, and repeat this operation until A becomes an upper triangular matrix R. Therefore, A can be gradually converted into an upper triangular form through reflection operations.

[0070] In order to achieve the above, the R matrix and the H matrix are sent to the multiplier and accumulator to obtain the diagonal matrix Q. Initially, Q is set to the unit matrix I. Each time a household transformation is performed, Q is updated to Q' = Q × H j , and finally obtain the diagonal matrix Q.

[0071] Among them, the above-mentioned household transformation is the transformation implemented by the above-mentioned vector calculation sub-module.

[0072] In some embodiments of the present invention, the matrix dimensionality reduction circuit 100 based on singular value decomposition further includes: a controller, connected to the first on-chip cache unit 101, the matrix decomposition calculation unit 102, the matrix dimensionality reduction unit 103 and the second on-chip cache unit 104, used to control the first on-chip cache unit 101 to obtain and cache the matrix to be reduced, control the matrix decomposition unit to perform singular value decomposition on the matrix to be reduced to obtain a first singular value matrix and a first right singular matrix, control the matrix dimensionality reduction unit 103 to obtain a reduced dimensionality matrix based on the first singular value matrix and the first right singular matrix, and control the second on-chip cache unit 104 to cache and output the reduced dimensionality matrix.

[0073] In some embodiments of the present invention, the singular value decomposition-based matrix dimensionality reduction circuit 100 further includes: a general computing unit connected to the matrix decomposition computing unit 102 and the matrix dimensionality reduction unit 103. The general computing unit includes multiple computing subunits, so that the matrix decomposition computing unit 102 and the matrix dimensionality reduction unit 103 call the computing subunits to perform corresponding calculations, wherein the multiple computing subunits include a multiplication subunit, a square root subunit, and a division subunit. In this way, resource waste can be avoided. In each step, the controller uniformly calls the basic operation unit to perform numerical calculations, which can greatly improve resource utilization and save area.

[0074] In some embodiments of the present invention, the matrix dimensionality reduction unit 103 includes a singular value screening module and a feature vector extraction module.

[0075] In order to reduce the dimensionality of the first singular value matrix, the first singular value matrix is screened and the first k largest singular values in the first singular value matrix are retained. That is, the remaining rows and columns in the first singular value matrix except the rows and columns where the first k largest singular values are located are deleted to obtain a second singular value matrix.

[0076] In order to perform dimensionality reduction processing on the first right singular matrix, after obtaining the above-mentioned first k largest singular values, the columns related to the first k largest singular values in the first right singular matrix are retained, and the remaining columns are deleted to obtain the second right singular matrix.

[0077] In order to obtain the left singular matrix, we can use A i v i =σ i u i Implement dimensionality reduction processing on the first left singular matrix, where A i is the i-th column of the matrix A to be reduced in dimension, v i is the i-th column of the second right singular matrix above, σ i is the singular value corresponding to the i-th column, u i is the i-th column of the left singular matrix.

[0078] After obtaining the left singular matrix, the second singular value matrix, and the second right singular matrix, calculate A reduced =U1Σ1V1 T .

[0079] Among them, A reduced is the dimensionality reduction matrix, U1 is the left singular matrix, Σ1 is the second singular value matrix, and V1 is the second right singular matrix.

[0080] The following describes the process in conjunction with a specific embodiment.

[0081] See also Figure 3 In this embodiment, the matrix dimensionality reduction circuit 100 based on singular value decomposition includes a first on-chip cache unit 101, a matrix decomposition calculation unit 102, a matrix dimensionality reduction unit 103, a second on-chip cache unit 104, a controller 105, and a general computing unit. The general computing unit includes units required by the matrix decomposition calculation unit 102 and the matrix dimensionality reduction unit 103, such as a multiplication subunit 1061, a square root subunit 1062, and a division subunit 1063. The controller 105, the first on-chip cache unit 101, and the second on-chip cache unit 104 communicate with the central processing unit 200 and the memory 300 through a bus interface.

[0082] Specifically, under the control of the central processing unit 200 , the matrix to be reduced in dimension is read from the memory 300 through the bus interface. The matrix to be reduced in dimension is a sparse matrix, and the first on-chip cache unit 101 caches the sparse matrix.

[0083] In AI data processing, sparse matrices with high feature dimensions—large matrices with a majority of zero elements—often exist. Singular value decomposition (SVD) can be used to map such high-dimensional data into a low-dimensional space by retaining the largest singular values, compressing it into a smaller matrix while preserving the data's core features. This method is widely used in fields such as image processing, natural language processing, recommender systems, and data compression. For example, feature extraction and data denoising in image recognition often rely on SVD, improving computational and storage efficiency through dimensionality reduction. In natural language processing, matrix decomposition is used to compress sparse, high-dimensional original matrices into a low-dimensional space, thereby capturing the semantic information of vocabulary. SVD is also widely used in recommender systems, which typically use a user-item interaction matrix (such as a user-item rating matrix) to collect key information. This matrix has a high number of rows and columns, but most of the elements are empty, making it a sparse matrix. SVD can be used to map users and items into a low-dimensional feature space, capturing user interests and item characteristics. These low-dimensional features are then used for matching to predict items that users are likely to like.

[0084] Since singular value decomposition and matrix dimensionality reduction of sparse matrices are of great significance, they are explained based on sparse matrices.

[0085] The input sparse matrix is stored in CSC format, consisting of a numeric array (values[]), a row index array (row_idx[]), and a column offset array (col_ptr[]. By storing only the nonzero elements in the sparse matrix, the CSC format significantly reduces memory usage and data transmission bandwidth. The singular value decomposition-based matrix dimensionality reduction circuit 100 directly reads CSC format data without converting the sparse matrix into a dense matrix, thereby reducing storage overhead and computational redundancy.

[0086] The matrix decomposition calculation unit 102 is responsible for performing singular value decomposition on the sparse matrix and outputting a first singular value matrix, a first left singular matrix, and a first right singular matrix. The matrix decomposition calculation unit 102 uses a specially designed hardware unit, including a decomposition module and a singular value update and extraction module. The decomposition module uses a pipeline to accelerate the decomposition process.

[0087] After matrix decomposition calculation unit 102 completes the decomposition, matrix dimensionality reduction unit 103 extracts the first k largest singular values and their corresponding column vectors from the first singular value matrix according to the dimensionality reduction dimension k set by the user, thereby generating a reduced-dimensional matrix. By reducing the dimensionality of the first singular value matrix and eigenvectors, the main features of the sparse matrix are retained, the matrix volume is significantly compressed, and storage requirements are reduced.

[0088] The general computing unit includes a multiplication subunit 1061, an addition subunit, a division subunit 1063, a square root subunit 1062, an accumulation subunit, and a transposition subunit. The multiplication subunit 1061 includes a multiplier, the addition subunit includes an adder, the division subunit 1063 includes a divider, the square root subunit 1062 includes a square root, the accumulation subunit includes an accumulator, and the transposition subunit includes a transposer. The transposer can be implemented, for example, by an electronic device including an electronic program. The matrix decomposition computing unit 102 and the matrix dimensionality reduction unit 103 call the general computing unit for data processing, saving area and improving circuit reuse through sharing.

[0089] Second on-chip cache unit 104 is an output cache, which is used to cache the matrix data of the reduced-dimensional matrix and transmit it back to memory 300, central processing unit 200, or for use by other processor modules. The reduced-dimensional matrix data is significantly smaller in size, and the output cache can effectively store these reduced-dimensional matrices, reducing bandwidth requirements during data transmission and improving storage and transmission efficiency.

[0090] The controller 105 is responsible for coordinating the work between the modules, managing data flow, task scheduling, and communication between the matrix decomposition calculation unit 102 and the central processing unit 200. Through the scheduling of the controller 105, the matrix dimensionality reduction circuit 100 based on singular value decomposition can offload the matrix decomposition task from the CPU, allowing the CPU to handle other tasks simultaneously, thereby increasing the throughput of the system. During the operation of each unit, the controller 105 regulates the operation control of each unit. For example, when performing singular value calculation, the controller 105 is responsible for regulating the task allocation of the multiplication subunit 1061 and the square root subunit 1062, and controlling the number of QR iterations.

[0091] The above vector calculation submodule can be found in Figure 4 , the above normalization submodule can be found in Figure 5 The above reflection submodule can be found in Figure 6. It can be seen that the above-mentioned first multiplier, second multiplier, third multiplier and fourth multiplier are all implemented by multipliers in a general-purpose computing unit, and the above-mentioned first accumulator, second accumulator and third accumulator are all implemented by accumulators in a general-purpose computing unit. Moreover, through this circuit, the singular value decomposition algorithm is optimized at the hardware level, especially a sparse matrix multiplication accelerator and a dedicated hardware acceleration unit are designed according to the characteristics of sparse matrices. The sparse matrix multiplication accelerator and the dedicated hardware acceleration unit are mainly a QR decomposition unit, and the QR decomposition unit includes the above-mentioned vector calculation submodule, normalization submodule and reflection submodule, forming a three-stage pipeline. The three-stage pipeline of the QR decomposition unit performs household vector calculation, normalization and reflection operations respectively, thereby hardwareizing the household algorithm. Compared with the traditional CPU, the singular value decomposition is faster, the decomposition efficiency is significantly improved, and the calculation time is reduced.

[0092] Through Figure 4 The vector calculation submodule shown can realize the calculation based on the non-zero element x1 (that is, the non-zero element with the smallest number of rows) and the column vector A j Get the reflection vector v corresponding to the jth column of the sparse matrix. Figure 5 The normalization submodule shown in FIG can obtain the normalized vector u according to the reflection vector v. Figure 6 The reflection submodule shown can obtain the reflection matrix H according to the normalized vector u, the normalized vector transpose uT (ie, the transpose vector of the normalized vector u), and the unit matrix I (ie, the above-mentioned preset unit matrix).

[0093] In summary, the matrix dimensionality reduction circuit based on singular value decomposition in an embodiment of the present invention includes a first on-chip cache unit for acquiring and caching the matrix to be reduced; a matrix decomposition calculation unit, connected to the first on-chip cache unit, for performing singular value decomposition on the matrix to be reduced to obtain a first singular value matrix and a first right singular matrix; a matrix dimensionality reduction unit, connected to the matrix decomposition calculation unit, for performing dimensionality reduction processing on the first singular value matrix and the first right singular matrix to obtain a second singular value matrix and a second right singular matrix, and obtaining a left singular matrix based on the matrix to be reduced and the second right singular matrix, and obtaining a reduced dimensionality matrix based on the second singular value matrix, the left singular matrix, and the second right singular matrix; and a second on-chip cache unit, connected to the matrix dimensionality reduction unit, for caching and outputting the reduced dimensionality matrix. This configuration enables singular value decomposition to be performed using a separately provided matrix decomposition calculation unit, without the need for the CPU, GPU, or other devices to participate, freeing up resources for processing other tasks and significantly improving the overall efficiency of the system. Furthermore, the matrix dimensionality reduction unit extracts the top k largest singular values and their corresponding eigenvectors to generate a reduced matrix, effectively compressing the original data. This dimensionality reduction operation significantly reduces the storage requirements of the output matrix and optimizes data transmission efficiency. While retaining the key features of the original matrix, the reduced matrix significantly reduces data storage and transmission overhead, making it particularly suitable for applications such as large-scale data analysis, image processing, and recommendation systems.

[0094] Furthermore, the present invention proposes a matrix dimensionality reduction system based on singular value decomposition.

[0095] Figure 7 It is a structural block diagram of a matrix dimensionality reduction system based on singular value decomposition according to an embodiment of the present invention.

[0096] like Figure 7 As shown, the matrix dimensionality reduction system 10 based on singular value decomposition includes the above-mentioned matrix dimensionality reduction circuit 100 based on singular value decomposition.

[0097] According to the matrix dimensionality reduction system based on singular value decomposition according to the embodiment of the present invention, according to the above-mentioned matrix dimensionality reduction circuit based on singular value decomposition, singular value decomposition is performed using a separately set matrix decomposition calculation unit, without the participation of devices such as CPU and GPU, which can free up resources to process other tasks, significantly improving the overall efficiency of the system. Moreover, the matrix dimensionality reduction unit extracts the first k largest singular values and their corresponding eigenvectors to generate a reduced-dimensional matrix. This process effectively compresses the volume of the original data. Through the dimensionality reduction operation, the storage requirements of the output matrix can be significantly reduced, and the data transmission efficiency can be optimized. While retaining the main features of the original matrix, the reduced-dimensional matrix greatly reduces the overhead of data storage and transmission, and is particularly suitable for application scenarios such as large-scale data analysis, image processing, and recommendation systems.

[0098] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device), or in conjunction with such an instruction execution system, apparatus, or device. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transmit a program for use by an instruction execution system, apparatus, or device, or in conjunction with such an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion having one or more wires (electronic device), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0099] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0100] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0101] In the description of this specification, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be understood as a limitation on the present invention.

[0102] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0103] In the description of this specification, unless otherwise specified, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. For those skilled in the art, the specific meanings of the above terms in this invention can be understood according to specific circumstances.

[0104] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0105] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A matrix dimensionality reduction circuit based on singular value decomposition, characterized in that: The circuit comprises: A first on-chip cache unit, used for acquiring and caching the matrix to be reduced in dimension; a matrix decomposition calculation unit, connected to the first on-chip cache unit, and configured to perform singular value decomposition on the matrix to be reduced in dimension to obtain a first singular value matrix and a first right singular matrix; a matrix dimensionality reduction unit, connected to the matrix decomposition calculation unit, configured to perform dimensionality reduction processing on the first singular value matrix and the first right singular matrix to obtain a second singular value matrix and a second right singular matrix, obtain a left singular matrix based on the matrix to be reduced in dimension and the second right singular matrix, and obtain a reduced dimensionality matrix based on the second singular value matrix, the left singular matrix, and the second right singular matrix; The second on-chip cache unit is connected to the matrix dimension reduction unit and is used for caching and outputting the dimension reduction matrix.

2. The matrix dimensionality reduction circuit based on singular value decomposition according to claim 1, characterized in that: The matrix to be reduced in dimension is a sparse matrix, and the first on-chip cache unit is specifically configured to: A numerical array, a row index array and a column offset data are obtained according to the matrix to be reduced in dimensionality, and the numerical array, the row index array and the column offset array are cached, wherein the numerical array includes the non-zero elements in the matrix to be reduced in dimensionality, the row index array includes the row index corresponding to each non-zero element in the numerical array in the matrix to be reduced in dimensionality, and the column offset array includes the position of the first non-zero element of each column in the matrix to be reduced in dimensionality in the numerical array.

3. The matrix dimensionality reduction circuit based on singular value decomposition according to claim 1, characterized in that: The matrix decomposition calculation unit includes: a decomposition module, configured to obtain the matrix to be decomposed, obtain a matrix to be decomposed according to the matrix to be decomposed, decompose the matrix to be decomposed into a form of an orthogonal matrix multiplied by an upper triangular matrix, and send the orthogonal matrix and the upper triangular matrix to a singular value updating and extraction module; The singular value update and extraction module is used to calculate the multiplication of the upper triangular matrix and the orthogonal matrix, use the multiplication result as the new matrix to be decomposed, and output the new matrix to be decomposed to the decomposition module, and after the singular value update and extraction module performs a preset number of multiplication calculations, obtain the singular values of the matrix to be reduced in dimension according to the latest multiplication results, and obtain the first singular value matrix and the first right singular matrix according to the singular values and all the orthogonal matrices obtained.

4. The matrix dimensionality reduction circuit based on singular value decomposition according to claim 3, characterized in that: The decomposition module includes: a vector calculation submodule, configured to calculate, for each column of the matrix to be reduced in dimensionality, the sum of the squares of all elements in the column to obtain a first binary norm, perform a square root on the first binary norm, determine the sign of the first binary norm after the square root based on the sign of the first row of elements in the column to obtain a second binary norm, and add the second binary norm to each element in the column to obtain a reflected vector based on the addition result; a normalization submodule connected to the vector calculation submodule, configured to calculate, for each of the reflection vectors, the sum of the squares of all elements in the reflection vector to obtain a third second norm, and divide each element in the reflection vector by the third second norm to obtain a normalized vector; a reflection submodule connected to the normalization submodule, configured to obtain, for each normalized vector, a transposed vector of the normalized vector, obtain a product of the normalized vector and the transposed vector, construct an initial matrix based on the product, and generate a reflection matrix based on the initial matrix and a preset unit matrix; A decomposition submodule is connected to the reflection submodule and is used to obtain the orthogonal matrix and the upper triangular matrix according to the reflection matrix and the matrix to be reduced in dimension.

5. The matrix dimensionality reduction circuit based on singular value decomposition according to claim 4, characterized in that: The vector calculation submodule includes: a first multiplier, wherein an input terminal of the first multiplier is designed as a first input terminal of the vector calculation submodule, and is used to obtain the matrix to be reduced in dimension and calculate the square of each element in the matrix to be reduced in dimension; a first accumulator, wherein an input end of the first accumulator is connected to an output end of the first multiplier, and is configured to obtain, for each column of the matrix to be reduced in dimension, a square sum based on the squares of all elements in the column; a square root device, the input end of the square root device being connected to the output end of the first accumulator, for performing a square root process on the square sum corresponding to each column in the matrix to be reduced in dimension, to obtain a first and second norm corresponding to the column; A comparator, wherein the input end of the comparator is designed to be the second input end of the vector calculation submodule, and is used to obtain the matrix to be reduced in dimension, and for each column in the matrix to be reduced in dimension, obtain a comparator output result corresponding to the column, wherein when the non-zero element with the smallest number of rows in the column is greater than zero, the comparator output result corresponding to the column is 1; when the non-zero element with the smallest number of rows in the column is less than zero, the comparator output result corresponding to the column is -1; a second multiplier, wherein a first input terminal of the second multiplier is connected to the output terminal of the square root generator, and a second input terminal of the second multiplier is connected to the output terminal of the comparator, and is configured to multiply each of the first second norms by the corresponding output result of the comparator to obtain a second second norm; An adder, wherein a first input end of the adder is connected to an input end of the first multiplier, and a second input end of the adder is connected to an output end of the multiplier, and is used to add, for each column of the matrix to be reduced in dimension, each element in the column with the second second norm corresponding to the column, and obtain a reflected vector according to the addition result.

6. The matrix dimensionality reduction circuit based on singular value decomposition according to claim 4, characterized in that: The normalization submodule includes: a third multiplier, wherein an input end of the third multiplier is designed to be an input end of the normalization submodule, and is used to obtain the reflection vector and calculate the square of each element in the reflection vector; a second accumulator, wherein an input terminal of the second accumulator is connected to an output terminal of the third multiplier, and is configured to obtain a square sum according to the squares of all elements in the reflected vector to obtain the third second norm; A divider, wherein a first input end of the divider is connected to the output end of the second accumulator, a second input end of the divider is connected to the input end of the third multiplier, and an output end of the divider is designed as an output end of the normalization submodule, for dividing each element in the reflected vector by the third second norm to obtain the normalized vector.

7. The matrix dimensionality reduction circuit based on singular value decomposition according to claim 4, characterized in that: The reflection submodule includes: a transposer, wherein an input terminal of the transposer is set to the first input terminal of the reflection submodule, and is used to obtain a transposed vector of the normalized vector; a fourth multiplier, wherein a first input terminal of the fourth multiplier is connected to the output terminal of the transposer, a second input terminal of the fourth multiplier is designed to be the second input terminal of the reflection submodule, and the fourth multiplier is used to obtain the normalized vector and the transposed vector, and multiply the normalized vector and the transposed vector to obtain a first initial matrix; a third accumulator, wherein an input terminal of the third accumulator is connected to an output terminal of the fourth multiplier, and is configured to add the first initial matrix to itself to obtain a second initial matrix; A subtractor, wherein the first input end of the subtractor is connected to the output end of the third accumulator, and the second input end of the subtractor is designed as the third input end of the reflection submodule, for obtaining the second initial matrix and the preset unit matrix, and subtracting the second initial matrix from the preset unit matrix to obtain the reflection matrix.

8. The matrix dimensionality reduction circuit based on singular value decomposition according to claim 1, characterized in that: The circuit further comprises: A controller is connected to the first on-chip cache unit, the matrix decomposition calculation unit, the matrix dimensionality reduction unit and the second on-chip cache unit, and is used to control the first on-chip cache unit to obtain and cache the matrix to be reduced in dimension, control the matrix decomposition unit to perform singular value decomposition on the matrix to be reduced in dimension to obtain a first singular value matrix and a first right singular matrix, control the matrix dimensionality reduction unit to obtain the reduced dimension matrix based on the first singular value matrix and the first right singular matrix, and control the second on-chip cache unit to cache and output the reduced dimension matrix.

9. The matrix dimensionality reduction circuit based on singular value decomposition according to claim 1, characterized in that: The circuit further comprises: A general computing unit is connected to the matrix decomposition computing unit and the matrix dimensionality reduction unit. The general computing unit includes multiple computing sub-units, so that the matrix decomposition computing unit and the matrix dimensionality reduction unit call the computing sub-units to perform corresponding calculations, wherein the multiple computing sub-units include multiplication sub-units, square root sub-units, and division sub-units.

10. A matrix dimensionality reduction system based on singular value decomposition, characterized in that: The method comprises a matrix dimension reduction circuit based on singular value decomposition according to any one of claims 1 to 9.

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