Enhanced gallium nitride power semiconductor device packaging method

Abstract

The invention provides a packaging method of an enhanced gallium nitride power semiconductor device, which belongs to the technical field of chip manufacturing, and comprises the following steps of: firstly, simulating and optimizing an electrode distance and a dielectric layer parameter through three-dimensional electric field distribution, and then realizing efficient thermal connection between a chip and a heat dissipation substrate by using a silver sintering process; and a multi-layer field plate structure is designed to disperse a high electric field region. Then a high-dielectric-constant resin layer and low-ion-content epoxy molding compound are applied for insulation and packaging, and then a siloxane modified polyimide protection layer is coated. The reliability is verified through an electric field tolerance test, a highly accelerated life test and a thermal cycle test, a micro-nano channel structure is formed by using a focused ion beam technology to relieve a local high electric field area, and finally the performance and life of the device are evaluated based on an electric field distribution and reliability prediction model of a deep learning framework. The reliability problem of the gallium nitride power semiconductor device in a high-voltage working environment is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip manufacturing, and in particular relates to a packaging method for an enhanced gallium nitride power semiconductor device. Background Art

[0002] Gallium nitride (GaN) power semiconductor devices are widely used in high-frequency, high-power density power electronics systems due to their superior properties, including high breakdown electric field, high electron mobility, and low on-resistance. Traditional GaN device packaging technologies rely primarily on simple metal leadframe structures and epoxy molding compound packaging, using conventional die bonding and wire bonding processes to provide electrical connections and physical protection. These traditional technologies can meet basic requirements in low-voltage applications, but as the operating voltage of GaN devices continues to increase, the electric field distribution within and on the surface of the devices becomes increasingly prominent.

[0003] However, traditional packaging methods have significant drawbacks. First, conventional epoxy materials lack dielectric properties and thermal stability, prone to localized breakdown in high-electric-field regions. Second, the electrode structure design lacks optimization for high-electric-field regions, resulting in uneven electric-field intensity distribution. Third, the high thermal resistance of the bonding process limits the device's power density and heat dissipation capabilities. These deficiencies significantly reduce the reliability of traditionally packaged GaN devices in high-voltage operating environments, making the mean time between failures (MTBF) difficult to meet practical application requirements.

[0004] The core problem that existing technologies struggle to address is the uneven electric field distribution within and on the surface of GaN devices under high-voltage operating conditions, resulting in localized areas of excessively high electric field intensity peaks. This leads to premature aging of the dielectric layer, increased surface charge accumulation, and ultimately device insulation failure and performance degradation. In other words, existing technologies present a technical problem in GaN power semiconductor devices operating under high-voltage conditions: excessively high local electric field intensity peaks, caused by uneven electric field distribution, lead to reduced device reliability. Summary of the Invention

[0005] In view of this, the present invention provides a packaging method for an enhancement-mode gallium nitride power semiconductor device, which can solve the technical problem in the prior art that the local electric field intensity peak is too high due to the uneven electric field distribution of gallium nitride power semiconductor devices in a high-voltage operating environment, resulting in reduced device reliability.

[0006] The present invention is implemented as follows: The present invention provides a packaging method for an enhancement-mode gallium nitride power semiconductor device, comprising: performing a three-dimensional electric field distribution simulation on a gallium nitride chip, and optimizing the electrode spacing and dielectric layer thickness based on the simulation data; fixing the gallium nitride chip on a heat dissipation substrate to form a heat conduction path; designing the surface electrodes of the gallium nitride chip using a multi-layer field plate structure; applying a high dielectric constant resin layer between the gallium nitride chip and a lead frame; using a low-ion content epoxy molding compound for primary packaging; performing an electric field tolerance test on the packaged gallium nitride chip; coating the outer layer of the gallium nitride chip with a siloxane-modified polyimide insulating coating; performing a highly accelerated life test and a thermal cycle test; using a focused ion beam technology to form a micro-nano channel structure in a high electric field region, constructing a local electric field buffer zone to complete the packaging, and using an electric field distribution and reliability prediction model to calculate the expected service life and failure probability curve of the packaged gallium nitride chip.

[0007] The three-dimensional electric field distribution simulation includes the following steps: 6 The areas with a volt / cm are marked, and the electrode spacing is optimized to be 20 to 30 μm and the dielectric layer thickness is optimized to be 3 to 5 μm based on the three-dimensional electric field distribution simulation data.

[0008] The method of fixing the gallium nitride chip on the heat dissipation substrate includes fixing the gallium nitride chip on a heat dissipation substrate made of aluminum nitride ceramic material, and using a silver sintering process to bond the chip at a temperature of 250 to 300°C to form a heat conduction path with a thermal resistance value of less than 0.1 square cm·degrees Celsius / watt.

[0009] The multilayer field plate structure is formed by sequentially depositing titanium, aluminum, nickel, and gold. The total thickness of the multilayer field plate structure is 0.8 to 1.2 μm, and the extension length of the multilayer field plate structure is 25% to 40% of the distance from the source to the drain.

[0010] The high dielectric constant resin layer has a breakdown strength of not less than 500 KV / mm, a thickness of 50 to 100 μm, and covers the entire high electric field region.

[0011] The primary packaging using low-ion content epoxy molding compound includes a vacuum injection molding process at 120 to 150° C. and a pressure of 5 to 8 MPa to ensure that there are no bubbles or delamination.

[0012] The electric field tolerance test of the packaged gallium nitride chip includes applying a voltage 20% higher than the rated operating voltage for 168 hours, and measuring the surface leakage current change within 5% of the original value.

[0013] The thickness of the siloxane-modified polyimide insulating coating is 15 to 25 μm, the curing temperature is 180 to 220° C., and the curing time is 60 to 90 minutes.

[0014] The electric field distribution and reliability prediction model performs calculations based on the acquired geometric parameters, material parameters, electric field distribution data, and surface leakage current data of the gallium nitride chip, and outputs the expected service life and failure probability curve of the gallium nitride chip.

[0015] Among them, the structure of the electric field distribution and reliability prediction model is a hierarchical deep learning framework consisting of an upper-level electric field distribution model and a lower-level material reliability model; the upper-level electric field distribution model uses a geometric structure perception module based on a graph neural network to extract the physical structure characteristics of the gallium nitride chip, and the lower-level material reliability model uses a long short-term memory network with a hybrid attention mechanism to predict the life evolution curve of the gallium nitride chip under different stress conditions.

[0016] The coupling between the upper-level electric field distribution model and the lower-level material reliability model is reflected in the fact that the local electric field intensity peak, electric field gradient and surface charge distribution output by the upper-level electric field distribution model directly affect the material interface aging rate parameters in the lower-level material reliability model.

[0017] The number of head parameters of the multi-head attention mechanism in the upper-level electric field distribution model and the lower-level material reliability model are dynamically adjusted according to three key parameters: the extension length of the multi-layer field plate structure, the breakdown strength of the high dielectric constant resin layer, and the rated working voltage.

[0018] This invention combines key technologies, including multi-layer field plate structure design, high-dielectric-constant resin layer application, silver sintering, and surface micro-nanochannel structuring, to form a complete, high-reliability packaging technology system. This approach first optimizes the electrode structure and dielectric layer parameters based on three-dimensional electric field distribution simulation results. High-performance materials and precise processes are then used to achieve packaging. Finally, device reliability is verified through rigorous testing and model evaluation.

[0019] This invention addresses the shortcomings of conventional technologies, particularly by effectively dispersing and homogenizing the electric field intensity in high-field regions. The multilayer field plate structure and micro-nanochannel design significantly reduce local electric field peaks; the high-dielectric-constant resin layer and siloxane-modified polyimide coating provide excellent insulation protection; and the silver sintering process significantly improves thermal conductivity. Through the synergistic effect of these technical approaches, this invention significantly improves the electric field distribution of gallium nitride devices operating in high-voltage environments.

[0020] This invention optimizes the key structures of GaN devices using electric field engineering principles, achieving uniform electric field distribution and peak intensity control. Furthermore, an electric field distribution and reliability prediction model based on a deep learning framework provides precise guidance for device design, enabling quality control throughout the entire process, from simulation optimization to field verification. This addresses the existing technical issue of GaN power semiconductor devices operating in high-voltage environments, where uneven electric field distribution causes excessively high local electric field intensity peaks, leading to reduced device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a flow chart of the method of the present invention.

[0022] Figure 2 Schematic diagram of the overall structure of the enhancement-mode gallium nitride power semiconductor device in Example 2.

[0023] Figure 3 This is the internal structure of the gallium nitride chip in Example 2.

[0024] Figure 4 Schematic diagram of the multi-layer field plate structure in Example 2.

[0025] Figure 5 Schematic diagram of the micro-nano channel structure in Example 2.

[0026] Figure 6 Schematic diagram of the chip heat dissipation direction in Example 2. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0028] like Figure 1 FIG. 1 is a flow chart of a packaging method for an enhancement-mode gallium nitride power semiconductor device provided by the present invention. The method comprises the following steps:

[0029] S01. Three-dimensional electric field distribution simulation: Perform three-dimensional electric field distribution simulation on the GaN chip. If the electric field intensity exceeds 3×10 6 volt / cm area is marked, and based on the three-dimensional electric field distribution simulation data, the electrode spacing is optimized to be 20 to 30 μm and the dielectric layer thickness is 3 to 5 μm;

[0030] S02. Substantially fixing: fixing the gallium nitride chip on a heat dissipation substrate made of aluminum nitride ceramic material, and performing chip bonding at a temperature of 250 to 300° C. using a silver sintering process to form a heat conduction path with a thermal resistance value of less than 0.1 square cm·° C. / W;

[0031] S03. Electrode Design: A multi-layer field plate structure is used to design the surface electrode of the gallium nitride chip. The multi-layer field plate structure is formed by sequentially depositing titanium, aluminum, nickel, and gold. The total thickness of the multi-layer field plate structure is 0.8 to 1.2 μm, and the extension length of the multi-layer field plate structure is 25% to 40% of the distance from the source to the drain.

[0032] S04. Applying a resin layer: applying a high dielectric constant resin layer between the gallium nitride chip and the lead frame, wherein the high dielectric constant resin layer has a breakdown strength of not less than 500 kV / mm, a thickness of 50 to 100 μm, and covers the entire high electric field area;

[0033] S05. Primary packaging: Use low-ion content epoxy molding compound for primary packaging, and use vacuum injection molding process at 120 to 150 ° C and pressure of 5 to 8 MPa to ensure there are no bubbles or delamination.

[0034] S06. Electric field tolerance test: The packaged GaN chip is subjected to an electric field tolerance test by applying a voltage 20% higher than the rated operating voltage for 168 hours, and the change in the measured surface leakage current does not exceed 5% of the original value;

[0035] S07, performing an insulating coating: coating the outer layer of the gallium nitride chip with a siloxane-modified polyimide insulating coating, wherein the siloxane-modified polyimide insulating coating has a thickness of 15 to 25 μm, a curing temperature of 180 to 220° C., and a curing time of 60 to 90 minutes;

[0036] S08. Life test: Perform a highly accelerated life test on the finished GaN chip, applying 80% of the rated voltage at an ambient temperature of 125° C. and a relative humidity of 85%. The highly accelerated life test lasts for 1000 hours, and the leakage current variation curve is recorded.

[0037] S09. Package reliability test: A thermal cycle test is performed to test the package reliability of the GaN chip. The temperature range is -40 to 150°C, the heating rate is 15°C per minute, and the cooling rate is 10°C per minute. The thermal cycle test is performed for 500 cycles.

[0038] S10. Surface electric field distribution analysis: Analyze the surface electric field distribution of the gallium nitride chip based on a high electric field stress model, and use focused ion beam technology to form a micro-nano channel structure in the high electric field area. The micro-nano channel structure has a depth of 1 to 2 μm, a width of 0.5 to 1 μm, and a spacing of 5 to 10 μm, thereby constructing a local electric field buffer zone.

[0039] S11. Optionally, the method further includes a performance evaluation: performing a performance evaluation on the gallium nitride chip using an electric field distribution and reliability prediction model, wherein the electric field distribution and reliability prediction model performs calculations based on the geometric parameters, material parameters, electric field distribution data, and surface leakage current data of the gallium nitride chip obtained in steps S01 to S10, and outputs an expected service life and failure probability curve of the gallium nitride chip.

[0040] Among them, the three-dimensional electric field distribution simulation is specifically a process of using finite element analysis software to construct a geometric model of the gallium nitride chip, input the dielectric parameters of each material, and calculate the electric field distribution inside and at each point on the surface of the entire gallium nitride chip structure under different operating voltages.

[0041] Among them, the multi-layer field plate structure is specifically a metal electrode extending near the drain or gate of the gallium nitride chip. By increasing the curvature radius of the electrode edge, the high electric field area is expanded and dispersed, thereby reducing the local electric field intensity peak structural design.

[0042] Among them, the silver sintering process specifically uses nano-silver paste to form a dense connection at a certain temperature. Compared with traditional solder, it has a chip connection method with higher thermal conductivity and lower resistivity.

[0043] Among them, the highly accelerated life test is an evaluation method that accelerates the aging process of the gallium nitride chip by applying environmental stress beyond normal usage conditions, and predicts the long-term reliability of the gallium nitride chip in a short period of time.

[0044] Among them, low-ion content epoxy molding compound is specifically a high-purity epoxy resin composite material with impurity content such as chloride ions and sodium ions less than 10ppm, which can effectively prevent metal migration and electrochemical corrosion.

[0045] Among them, the siloxane-modified polyimide insulating coating specifically introduces siloxane bonds into the polyimide molecular structure, creating a high-performance composite insulating material that combines the heat resistance of polyimide and the hydrophobicity of siloxane.

[0046] Among them, the high electric field stress model equation is used to predict the physical deformation and microstructural changes caused by high electric fields at the material interface. The input includes the dielectric constant of the high dielectric constant resin layer in step S04, the polarization intensity generated by the electrode geometric structure obtained in step S03, the local electric field intensity distribution function obtained in step S01, the interface binding energy between the high dielectric constant resin layer used in step S04 and the gallium nitride chip, and the elastic modulus of the high dielectric constant resin layer material used in step S04. The output is the stress tensor and critical breakdown electric field intensity at the interface between the high dielectric constant resin layer and the gallium nitride chip in step S04. The high electric field stress model is based on the balance relationship between the electrostatic force caused by the accumulation of polarized charges at the material interface and the interface stress. By solving the coupled equations between the Maxwell stress tensor and the material deformation response, the stress distribution at the interface under different electric field intensities is predicted, and then the reliability limit and failure mechanism of the gallium nitride chip under high voltage working conditions are evaluated. The high electric field stress model can accurately capture the electric stress concentration phenomenon and provide a theoretical basis for the design and optimization of multi-layer field plate structures.

[0047] Among them, the micro-nano channel structure is specifically a microscopic groove array formed by etching on the surface of the gallium nitride chip through focused ion beam technology. It is used to regulate the electric field distribution and reduce the structural design of the surface electric field peak intensity.

[0048] Among them, the specific structure of the electric field distribution and reliability prediction model is a hierarchical deep learning framework consisting of an electric field distribution upper model and a material reliability lower model. The electric field distribution upper model uses a geometric structure perception module based on a graph neural network to extract the physical structure characteristics of the gallium nitride chip, and the material reliability lower model uses a long short-term memory network with a hybrid attention mechanism to predict the life evolution curve of the gallium nitride chip under different stress conditions; the input of the electric field distribution upper model includes the gallium nitride chip geometric model obtained in step S01, the electrode shape parameters designed in step S03, and the dielectric material distribution and electrical properties used in step S04. The objective function of the electric field distribution upper model is to minimize the mean square error between the simulated electric field distribution and the measured distribution. The constraint conditions of the electric field distribution upper model are that the electric field distribution satisfies the Poisson equation and the potential is continuous; the input of the material reliability lower model is the electric field distribution result output by the electric field distribution upper model and the external condition parameters such as temperature, humidity, and working voltage in steps S08 and S09. The target function is to minimize the log-likelihood loss between the predicted failure time and the measured failure time. The constraint condition of the lower-level material reliability model is that the failure probability increases monotonically with time and satisfies the basic characteristics of the Weibull distribution. The coupling between the upper-level electric field distribution model and the lower-level material reliability model is reflected in the fact that the local electric field intensity peak, electric field gradient and surface charge distribution output by the upper-level electric field distribution model directly affect the material interface aging rate parameters in the lower-level material reliability model, and the failure probability distribution fed back by the lower-level material reliability model guides the upper-level electric field distribution model to optimize the electrode structure design and material selection. The number of heads of the multi-head attention mechanism in the upper-level electric field distribution model and the lower-level material reliability model is dynamically adjusted according to three key parameters: the extension length of the multi-layer field plate structure in step S03, the breakdown strength of the high dielectric constant resin layer in step S04 and the rated working voltage in step S06. The number of heads of the multi-head attention mechanism is calculated using an adaptive algorithm. When the voltage level of the gallium nitride chip is higher, more attention heads are allocated to capture more complex electric field distribution characteristics.

[0049] Among them, the steps for establishing the training data set in the training process of the electric field distribution and reliability prediction model include collecting a total of 5,000 groups of gallium nitride power device samples with different structural parameters. Each group of samples contains complete gallium nitride chip geometric structure parameters, material property parameters, operating voltage parameters and measured failure data; using finite element software to generate corresponding high-precision electric field distribution simulation results as annotation data; performing data enhancement processing on the samples, and expanding the number of samples to 15,000 groups by randomly perturbing the geometric parameters and material parameters; dividing the training set, validation set and test set in a ratio of 8:1:1; standardizing the data so that all eigenvalues are evenly distributed within the range of zero mean and unit variance; constructing a multi-level labeling system, including electric field distribution tensor, key point electric field strength values, expected service life, failure probability curve and other multi-dimensional label information; cleaning and consistency testing of the data set based on physical knowledge to ensure that the data conforms to basic electromagnetic principles and materials laws.

[0050] Among them, the steps of training the electric field distribution and reliability prediction model specifically include first using an unsupervised learning method to train the upper layer model of the electric field distribution, and using the finite element simulation data obtained in step S01 to establish a mapping relationship between the geometric structure and the electric field distribution; then using a supervised learning method to train the lower layer model of the material reliability, and using the actual failure data obtained in step S08 as a label to train the network; then performing a joint training of the electric field distribution and reliability prediction model as a whole, and optimizing the parameters of the upper layer model of the electric field distribution and the lower layer model of the material reliability through end-to-end gradient back propagation; adopting a learning rate annealing strategy during the training process, with the initial learning rate set to 0.001 and the decay rate every 20 cycles. The weight of the electric field distribution and reliability prediction model is reduced to 0.9 times of the original; a regularization term is added to prevent overfitting, and the weight attenuation coefficient is set to 0.0005; the gradient clipping technology is used to prevent the gradient explosion problem, and the maximum gradient norm is set to 5.0; an early stopping strategy is used to terminate the training when the loss function on the validation set no longer decreases for 10 consecutive cycles; after training, the performance of the electric field distribution and reliability prediction model is evaluated on the test set, requiring the relative error of the electric field distribution prediction to be less than 5%, and the relative error of the failure time prediction to be less than 15%; finally, the trained weights of the electric field distribution and reliability prediction model are saved as a lightweight version, and the complexity of the electric field distribution and reliability prediction model is reduced through knowledge distillation technology to ensure that it can run efficiently on the embedded system.

[0051] The specific implementation methods of the above steps are described in detail below. The specific implementation method of step S01 is to construct a three-dimensional geometric model of the gallium nitride chip through finite element analysis software. The model includes all structures such as gallium nitride epitaxial layer, channel layer, field plate electrode, source, drain and gate. First, input the dielectric constant of each material, such as 9.0 for gallium nitride, 3.9 for silicon dioxide, and 7.5 for silicon nitride, and set the grid density to no less than 10 grid points per μm in the high electric field area and no less than 3 grid points per μm in the low electric field area. Then, under different voltage conditions, the potential distribution is solved using the Poisson equation, and the three-dimensional electric field distribution is obtained by calculating the potential gradient. For electric field strengths exceeding 3×10 6 The system uses an adaptive marking algorithm to identify regions with high volts / cm, typically located at the gate edge and field plate terminations. Based on this electric field distribution data, a parameter sweep optimizes the electrode spacing, setting it within the 20 to 30 μm range. The dielectric thickness is also optimized to 3 to 5 μm, ensuring sufficient dielectric strength without excessively increasing thermal resistance. These parameters are determined by comparing the maximum electric field strength under different geometries. The ultimate optimization goal is to reduce the maximum electric field strength to below the critical breakdown field while maintaining good device conduction characteristics.

[0052] The specific implementation of step S02 is to use a high thermal conductivity aluminum nitride ceramic material as a heat dissipation substrate. The thermal conductivity of this material is between 170 and 220 watts per meter Kelvin, which is much higher than that of traditional alumina ceramics. The back of the gallium nitride chip is plated with three layers of titanium, nickel, and silver, with thicknesses of 50 nanometers, 200 nanometers, and 1000 nanometers, respectively, to enhance the bonding strength with the nano-silver paste. The particle size of the nano-silver paste is controlled to be within the range of 20 to 50 nanometers, and the solid content is 85% to 90%. Under vacuum conditions, the temperature is raised to 250 to 300°C at a heating rate of 2 to 5°C per minute and kept at this temperature for 30 to 45 minutes, so that the nano-silver particles are sintered to form a dense silver interconnect layer. The connection interface formed by this silver sintering process has a thickness of about 10 to 20 μm and a thermal conductivity of up to 200 to 250 watts per meter Kelvin, which is much better than the thermal conductivity of traditional solder (about 50 to 70 watts per meter Kelvin). After implementing this process, the thermal resistance of the heat conduction path formed between the chip and the substrate is less than 0.1 square cm·degrees Celsius / watt, which can effectively dissipate the heat generated by the device under high-frequency and high-power operating conditions, preventing device performance degradation and reliability reduction caused by heat accumulation.

[0053] The specific implementation of step S03 is to use photolithography and metal deposition technology to realize the production of a multi-layer field plate structure. First, a silicon dioxide or silicon nitride dielectric layer with a thickness of 200 to 300 nanometers is deposited on the surface of the gallium nitride chip by plasma enhanced chemical vapor deposition process. A pattern is formed by photoresist coating, exposure and development, and then a step-like structure is formed on the dielectric layer by reactive ion etching process, with the thickness of the dielectric layer decreasing successively at different steps. Subsequently, a titanium layer (thickness of 50 to 80 nanometers), an aluminum layer (thickness of 400 to 600 nanometers), a nickel layer (thickness of 50 to 100 nanometers) and a gold layer (thickness of 200 to 300 nanometers) are deposited in sequence by electron beam evaporation or magnetron sputtering technology to form a multi-layer field plate electrode structure with a total thickness of 0.8 to 1.2 μm. The titanium layer provides good interfacial bonding energy as an adhesion layer, the aluminum layer provides the main conductive channel, the nickel layer acts as a diffusion barrier to prevent the mutual diffusion of gold and aluminum, and the gold layer provides oxidation resistance and good welding properties. The multilayer field plate structure extends from the source to the drain, with an extension length of 25% to 40% of the source-to-drain distance. This multilayer field plate structure effectively reduces the peak electric field intensity by increasing the curvature radius of the electrode edge. Theoretically, it can reduce the peak electric field intensity by 30% to 50%, significantly improving the breakdown voltage and reliability of the device.

[0054] The specific implementation of step S04 involves selecting a high-dielectric constant resin material, such as polyaryletherketone (PEK) or epoxy-modified polyimide (EPI), with a dielectric constant between 4.0 and 6.0 and a breakdown strength of no less than 500 kV / mm. First, the chip surface undergoes plasma treatment to improve surface wettability and adhesion. Then, a precision dispensing device precisely controls the application of a high-dielectric constant resin layer between the chip and the lead frame. The dispensing head temperature is controlled between 30 and 40°C, the dispensing pressure is between 0.2 and 0.4 MPa, and the dispensing speed is 5 to 10 mm / second. After the resin is applied, it is pre-cured at 60 to 80°C for 1 to 2 hours, followed by a final cure at 150 to 180°C for 2 to 3 hours. The cured high-dielectric constant resin layer is controlled to have a thickness of 50 to 100 μm, with a thickness uniformity deviation within ±5%. This high-dielectric constant resin layer completely covers the high electric field areas identified in step S01, ensuring that the electric field strength in these areas is reduced to a safe level. In addition, adding nano-alumina particles (content of 2% to 5%) to the resin can further improve the thermal conductivity and mechanical strength of the resin, reduce the thermal expansion coefficient, and reduce the risk of failure caused by thermal stress.

[0055] The specific implementation of step S05 is to select an epoxy molding compound with an ion content of less than 10 parts per million, a temperature cycling reliability rating meeting JEDEC standard J-STD-020D Level 3, and a glass transition temperature exceeding 150°C. The mold is first vacuum preheated at 80 to 100°C for 60 to 90 minutes to completely remove moisture and gas from the mold. The epoxy molding compound is then preheated to 90 to 110°C to reduce viscosity, and then infused using a vacuum injection molding process at 120 to 150°C and a pressure of 5 to 8 MPa. During the injection molding process, a vacuum of at least 10 Pascals is maintained, and the injection speed is controlled at 5 to 10 cubic centimeters per second. After injection molding, the mold is cured in stages, initially at 150 to 170°C for 1 to 2 hours, then at 180 to 200°C for 2 to 3 hours, and finally slowly cooled to room temperature at a cooling rate not exceeding 2°C per minute. This multi-stage curing process effectively reduces internal stress and prevents bubbles and delamination during the packaging process. After curing, the package quality is assessed using ultrasonic scanning and X-ray inspection technology to ensure that there are no voids, cracks, or delamination inside the package, and that the contact interfaces are well bonded.

[0056] The specific implementation of step S06 involves constructing a high-voltage electric field tolerance test platform, which includes a high-precision voltage source (accuracy better than 0.1%), a microcurrent measurement system (nanoampere-level accuracy), and a constant temperature control system (temperature fluctuations are controlled within ±0.5°C). First, the packaged GaN chip is stabilized at an ambient temperature of 25±2°C. A voltage is gradually applied to 120% of the rated operating voltage, with a voltage ramp rate controlled at 1% of the rated voltage per second. After reaching the target voltage, the constant voltage is maintained for 168 hours (7 days), during which the surface leakage current is recorded every 6 hours. During the test, relative humidity is maintained between 40% and 60% to eliminate humidity effects. After the test is completed, the leakage current is analyzed over time to ensure that the change does not exceed 5% of the original value. If the leakage current changes beyond a threshold, the electrode structure and dielectric layer quality in the high electric field area are inspected, and steps S03 and S04 are optimized and adjusted. This test is designed to verify the stability of the package structure under long-term high electric field stress and evaluate the electric field distribution at the electrode edge and the performance of the dielectric material.

[0057] The specific implementation of step S07 is to prepare a siloxane-modified polyimide solution consisting of a polyimide precursor, a siloxane modifier (content of 10% to 15%), and an N-methylpyrrolidone solvent, with a solid content adjusted to 15% to 20%. This solution is evenly applied to the outer layer of the gallium nitride chip using a spin coating process at a speed of 1000 to 1500 rpm for 30 to 45 seconds. After coating, the solution is pre-cured at 60 to 80°C for 30 to 45 minutes to remove most of the solvent. The solution is then cured using a multi-stage heat treatment process: first, maintaining the temperature at 100 to 120°C for 30 minutes, then increasing the temperature to 150 to 170°C for 30 minutes, and finally increasing the temperature to 180 to 220°C for 60 to 90 minutes. After curing, the thickness of the siloxane-modified polyimide insulating coating is 15 to 25 μm, with thickness uniformity controlled within ±10%. This coating combines the high heat resistance of polyimide (glass transition temperature > 250°C) and the excellent hydrophobicity of siloxane (contact angle > 100 degrees). Its dielectric strength reaches 200 to 250 kV / mm, effectively protecting against moisture, ionic contaminants, and mechanical damage in the external environment, thereby improving the environmental tolerance and long-term reliability of gallium nitride chips.

[0058] Step S08 is specifically implemented using a highly accelerated life test system compliant with JEDEC standard JESD22-A110, which features a temperature control accuracy of ±0.5°C and a humidity control accuracy of ±2%. The packaged GaN chip is placed in a test chamber set to an ambient temperature of 125°C and a relative humidity of 85%. Before testing, the chip is preconditioned and baked at 60°C for 24 hours to remove adsorbed moisture. After the test begins, 80% of the rated voltage is applied between the chip's drain and source, with the gate voltage set to the off state below the threshold voltage. The test lasts for 1000 hours, with leakage current recorded hourly using a high-precision source meter (SRM) with a current measurement resolution better than 10 nanoamperes. After the test, a leakage current variation over time is plotted, and the slope and breakpoints of the curve are analyzed to identify potential failure mechanisms such as electrode migration, dielectric breakdown, or interface degradation. Scanning electron microscopy and energy spectrum analysis are also used to examine the chip's surface morphology and compositional changes to verify the stability of the package structure under the triple stress of high temperature, high humidity, and high voltage.

[0059] The specific implementation of step S09 involves placing the packaged GaN chip in a programmable temperature-controlled thermal cycle test chamber with a temperature range of -65 to 200°C, with a temperature fluctuation accuracy controlled within ±1°C. The chip is first pre-conditioned by baking it at 60°C for 12 hours to remove moisture. A thermal cycle test is then performed: the temperature is lowered from 25°C to -40°C, held for 15 minutes; then raised to 150°C at a rate of 15°C / minute and held for 15 minutes; then lowered to -40°C at a rate of 10°C / minute, repeating this cycle for a total of 500 cycles. At the end of the 1st, 100th, 200th, 300th, 400th, and 500th cycles, samples are removed for intermediate inspection, including visual inspection, ultrasonic scanning, and electrical parameter testing (leakage current, breakdown voltage, and dynamic on-resistance). The parameter changes before and after the test are compared, and the drift rate is calculated. The requirement is that the leakage current does not increase by more than 20%, the breakdown voltage does not decrease by more than 10%, and the dynamic on-resistance does not increase by more than 15%. This test evaluates the mechanical stability and material interface bonding reliability of the package structure under extreme temperature changes, with particular attention paid to the welding interface, lead connection, and the interface bonding between the molding compound and the chip.

[0060] The specific implementation of step S10 is to construct a high electric field stress model based on the three-dimensional electric field distribution simulation results of step S01. This model integrates Maxwell stress tensor theory and finite element analysis method to calculate the mechanical stress distribution caused by the electric field. First, the electric field strength exceeds 2.5×10 6 Regions with a voltage of 30 kiloelectron volts / cm are identified as areas of high electric field stress. A focused ion beam system is then used, equipped with a gallium ion source, an accelerating voltage of 30 keV, and an adjustable beam current range of 10 picoamperes to 10 nanoamperes. In the high electric field region, an automated pattern generation algorithm is employed to design the micro-nano channel structure layout, using the gate spacing as a reference. The focused ion beam forms parallel channel structures in the high electric field region, with a channel depth controlled between 1 and 2 μm, a width between 0.5 and 1 μm, and a spacing between adjacent channels of 5 to 10 μm. During the etching process, the ion beam current density is controlled between 0.1 and 0.5 picoamperes / μm², and the etching rate is approximately 0.1 μm / minute to ensure etching quality and dimensional accuracy. These micro-nano channels reduce the peak electric field intensity by changing the surface electric field distribution. Theoretical calculations show that the peak electric field intensity can be reduced by 15% to 25%. At the same time, the channel structure increases the surface area, improves heat dissipation, and acts as a charge trap to capture surface free charges, forming a local electric field buffer zone, suppressing electric field concentration, and improving the stability and reliability of the device under high voltage working conditions.

[0061] Step S11 is optional. Its specific implementation involves constructing an electric field distribution and reliability prediction model based on the GaN chip's geometric parameters, material parameters, electric field distribution data, and surface leakage current data obtained in the previous steps. This model consists of an upper-level electric field distribution model and a lower-level material reliability model. The upper-level electric field distribution model uses the GaN chip's actual geometric structure as input, employs a graph neural network to extract spatial features, and simulates the propagation of the electric field in space through a message passing mechanism. The lower-level material reliability model, based on a long-short-term memory network with a hybrid attention mechanism, captures the temporal characteristics of material aging. Model training utilizes a phased strategy: first, the upper-level model is trained using finite element simulation data, then the lower-level model is trained using actual failure data, and finally, a joint optimization is performed. After training, the model inputs include the GaN chip's specific geometric parameters, material parameters, and operating conditions, and outputs expected service life and failure probability curves. This model accurately predicts device reliability performance under given operating conditions. For example, under operating conditions of 125°C and 85% of rated voltage, it can predict the device's mean time between failures, failure modes, and failure time distribution. This model guides chip structure design and packaging process optimization, effectively improving product reliability and reducing R&D costs and cycles. In terms of prediction accuracy, the relative error in electric field distribution prediction is controlled within 5%, and the relative error in failure time prediction is controlled within 15%.

[0062] The detailed structure of the upper-layer electric field distribution model is a geometric-aware framework based on a graph neural network. It consists of a node embedding layer, a graph convolution layer, a global pooling layer, and a fully connected output layer. The node embedding layer represents the discrete geometric structure of the GaN chip as a graph structure, with each node containing position coordinates and material property information. The graph convolution layer consists of three to five layers of graph convolutional networks, each containing 64 to 128 convolution kernels, and employs a residual connection structure to enhance gradient propagation. The global pooling layer uses an attention mechanism to weightedly aggregate node features, specifically focusing on node information in high electric field regions. The fully connected output layer maps the features into a three-dimensional electric field distribution tensor. The model takes as input the GaN chip geometry model, electrode shape parameters, and dielectric material distribution. It optimizes the electric field distribution by minimizing the mean squared error between the predicted electric field distribution and the finite element simulation results, while ensuring that the electric field distribution satisfies the Poisson equation and potential continuity constraints.

[0063] The detailed structure of the lower-level model for material reliability is a long short-term memory (LSTM) network with a hybrid attention mechanism, consisting of a multi-head temporal attention layer, a bidirectional LSTM layer, and an adaptive prediction layer. The multi-head temporal attention layer contains four to eight attention heads, which are dynamically adjusted according to the voltage level to focus on failure characteristics at different time scales. The bidirectional LSTM layer consists of two layers, each with 128 to 256 hidden units. Forward and backward propagation captures long-term dependencies in the time series. The adaptive prediction layer adjusts prediction parameters based on different operating conditions and outputs a time-varying curve of the failure probability. The model inputs are the electric field distribution output by the upper-level model and external condition parameters such as temperature, humidity, and operating voltage. The model is optimized by minimizing the log-likelihood loss between the predicted and measured failure times, ensuring that the failure probability increases monotonically over time and conforms to the characteristics of the Weibull distribution.

[0064] The detailed steps for establishing a training dataset for the electric field distribution and reliability prediction model begin with sample collection. 5,000 GaN power device samples with varying structural parameters were selected, covering a wide range of geometric variations, material combinations, and operating voltage levels. Each sample set includes complete geometric parameters, material property parameters, operating voltage parameters, and measured failure data. High-precision electric field distribution simulation results were then generated using finite element software as annotated data. The simulation grid accuracy was set to a minimum of 15 grid points per μm in critical regions. Data augmentation was then performed to expand the sample set to 15,000 by randomly perturbing geometric parameters (within a ±5% range) and material parameters (within a ±10% range). The samples were divided into training, validation, and test sets in an 8:1:1 ratio. Data normalization adjusted all eigenvalues to a zero-mean, unit-variance distribution. A multi-level labeling system was constructed, including the electric field distribution tensor, electric field strength values at key points, expected service life, and failure probability curves. Finally, the dataset was cleaned and consistency-checked based on electromagnetic principles and materials science to ensure data quality and physical validity.

[0065] The mathematical model or calculation process involved in the present invention is described in detail below.

[0066] The three-dimensional electric field distribution simulation in step S01 involves solving the Poisson equation, which is specifically expressed as follows:

[0067]

[0068] Where, is the gradient operator; φ is the electric potential field function, in volts; ε r is the relative dielectric constant of the material, dimensionless; ε0 is the dielectric constant of vacuum, which is 8.85×10 -12 Farad / meter; ρ is the charge density distribution function, with the unit of coulomb / cubic meter.

[0069] Under boundary conditions, the potential difference between the source and drain is expressed as:

[0070] φ DS =φ D -φ S =V DS ;

[0071] Where, φ D is the drain potential in volts; φ S is the source potential, usually set to 0 volts; V DS is the source-drain voltage in volts.

[0072] After solving the above Poisson equation to obtain the potential distribution, the electric field strength calculation formula is:

[0073]

[0074] Where, is the electric field strength vector, in volts per meter.

[0075] The scalar value of the electric field strength is calculated as:

[0076]

[0077] Where, E x 、E y 、E z are the components of the electric field strength in the x, y, and z directions, respectively, and the unit is volts per meter.

[0078] The parameter acquisition method is: relative dielectric constant ε of the material r Obtained through material handbook, such as ε of gallium nitride r is 9.0, the ε of silicon dioxide r is 3.9; the charge density distribution ρ is calculated through the device physical model and doping concentration distribution; the boundary potential is set by simulating the voltage distribution under the working state of the device.

[0079] This Poisson equation is based on electrostatic field theory and takes into account the discontinuity of dielectric constants at interfaces between different materials. It accurately reflects the electric field distribution in complex geometric structures. The gradient operator in the equation characterizes the spatial rate of change of the electric field, the dielectric constant term accounts for the influence of different materials on the electric field, and the charge density term represents the contribution of space charge to the electric field. Compared with traditional one-dimensional or two-dimensional simulations, three-dimensional solutions can more accurately capture edge and corner effects, providing a theoretical basis for optimizing field plate structures.

[0080] The thermal resistance calculation in step S02 involves the heat conduction equation, which is specifically expressed as follows:

[0081]

[0082] Where R th is the thermal resistance value, in square cm·°C / W; t is the thickness of the silver sintering layer, in μm; k is the thermal conductivity of the silver sintering layer, in W / m·Kelvin; A is the chip contact area, in square cm; R int1 is the thermal resistance between the chip and the silver sintering layer, in square cm·°C / W; R int2 is the thermal resistance of the interface between the silver sintered layer and the ceramic substrate, in square cm·°C / W; R sp is the thermal resistance coefficient of the heat dissipation path, in square cm·°C / W; n is the number of parallel heat channels, dimensionless.

[0083] Calculation formula for interface thermal resistance:

[0084]

[0085] Where R int is the interfacial thermal resistance, in square cm·degrees Celsius / W; γ is the interface roughness correlation coefficient, dimensionless, ranging from 0.5 to 2.0; P is the interfacial pressure, in MPa; k1 and k2 are the thermal conductivity of the materials on both sides, respectively, in W / m·K; ρ1 and ρ2 are the densities of the materials on both sides, respectively, in kg / m3; c1 and c2 are the specific heat capacities of the materials on both sides, respectively, in joule / kg·Kelvin.

[0086] The parameter acquisition method is as follows: the thickness of the silver sintered layer t is measured by cross-sectional scanning electron microscopy; the thermal conductivity k is measured by laser flash method. The specific steps include: (1) coating the sample surface with a graphite enhanced absorption layer; (2) irradiating the front surface of the sample with a pulsed laser; (3) measuring the temperature change curve of the rear surface with time using an infrared detector; (4) calculating the thermal conductivity according to the formula k = α·ρ·c, where α is the thermal diffusion coefficient. Interface thermal resistance R int1 and R int2 The thermal resistance coefficient R of the heat dissipation path is obtained by transient thermal resistance test method. sp It is obtained by simulation calculation using finite element thermal analysis software.

[0087] This thermal resistance calculation equation takes into account both the conduction resistance and the interface resistance in multilayer structures, conforming to the basic theory of heat conduction and using a layered accumulation approach to calculate the total thermal resistance. The ratio of thickness to thermal conductivity in the equation represents the pure conduction resistance, the interface resistance represents the contact resistance at the material interface, and the heat dissipation path coefficient takes into account the three-dimensional heat diffusion effect. The inverse relationship reflects the thermal resistance reduction effect of parallel heat channels, which is consistent with actual physical phenomena. The advantage of this equation is that it comprehensively considers both the material bulk and interface factors, enabling accurate prediction of the thermal conductivity performance of complex structures.

[0088] The calculation of the multilayer field plate effect in step S03 involves the field plate electric field modulation equation, which is specifically expressed as follows:

[0089]

[0090] Where, E peak is the peak electric field intensity after field plate modulation, in volts / cm; E0 is the peak electric field intensity without field plate, in volts / cm; β is the field plate efficiency coefficient, dimensionless, ranging from 0.3 to 0.6; L FP L is the field plate extension length, in μm; GD is the distance from source to drain, in μm; t die is the thickness of the dielectric layer, in μm; T FP is the field plate metal thickness, in μm; α is the thickness influence index, dimensionless, ranging from 0.2 to 0.5; δ is the position correction coefficient, dimensionless, ranging from 0.1 to 0.3; x is the distance from the gate edge to the measurement point, in μm.

[0091] Calculation of the effective electric field distribution of the multilayer field plate structure:

[0092]

[0093] Where, E eff (x, y, z) is the effective electric field intensity distribution function after considering the multilayer field plate structure, in volts / cm; E i (x, y, z) is the electric field intensity distribution function independently contributed by the i-th field plate, in volts / cm; w i is the weight coefficient of the i-th field plate, dimensionless, satisfying d i (x, y, z) is the shortest distance from the spatial point (x, y, z) to the i-th field plate, in μm; λ i is the electric field attenuation characteristic length of the i-th field plate, in μm; n is the number of field plate layers.

[0094] The parameter acquisition method is as follows: the peak electric field intensity E0 without field plate is obtained through finite element simulation; the field plate efficiency coefficient β is determined by combining experimental verification with theoretical calculation. The specific steps include: (1) preparing comparative samples with different field plate lengths; (2) measuring the breakdown voltage of each sample; (3) determining the β value through curve fitting. The field plate extension length L FP and source-drain distance L GD The thickness influence index α is determined by mask design. The thickness influence index α is obtained through parameter scanning simulation, and the position correction coefficient δ is obtained by comparing the measured electric field distribution with the theoretical model.

[0095] The electric field modulation equation of the field plate is constructed based on the electric field concentration effect and edge passivation theory, and takes into account the combined influence of the field plate length, thickness ratio and position factors on the electric field distribution. The fractional term in the equation characterizes the field plate extension coverage effect, the power term reflects the nonlinear influence of the thickness ratio on the modulation effect, and the sine term takes into account the special effect of the edge position of the field plate. The multi-layer field plate superposition equation takes into account the electric field shielding effect and distance attenuation characteristics of each layer of field plate, uses an exponential attenuation function to describe the far-field effect, and the weight coefficient reflects the relative importance of different layers of field plates. Compared with the traditional single-layer field plate model, this equation system can more accurately describe the electric field modulation effect of complex multi-layer field plate structures.

[0096] The design of the high dielectric constant resin layer in step S04 involves a dielectric layer breakdown model, which is specifically expressed as follows:

[0097]

[0098] Where, E br is the actual breakdown field strength of the dielectric layer, in KV / mm; E br0 is the intrinsic breakdown field strength of the dielectric layer under standard conditions, in KV / mm; t is the actual thickness of the dielectric layer, in μm; t0 is the reference thickness, which is 1 μm; γ is the thickness effect index, dimensionless, ranging from 0.2 to 0.4; T is the operating temperature, in Kelvin; T0 is the reference temperature, which is 298 Kelvin; T c is the temperature characteristic constant, in Kelvin, ranging from 50 to 100 Kelvin; η is the humidity sensitivity coefficient, dimensionless, ranging from 0.05 to 0.15; RH is the relative humidity, in percentage; RH0 is the reference relative humidity, with a value of 50%; ξ is the impurity influence coefficient, dimensionless, ranging from 0.8 to 1.2; f imp is the normalized function of impurity concentration, dimensionless, ranging from 0 to 0.5.

[0099] High dielectric constant resin layer thickness design model:

[0100]

[0101] Where, t min is the minimum safe thickness of the high dielectric constant resin layer, in μm; V max is the maximum operating voltage in volts; σ V is the voltage fluctuation coefficient, dimensionless, ranging from 0.1 to 0.2; K sf is the safety factor, dimensionless, ranging from 1.5 to 2.5; E br is the dielectric breakdown field strength, in KV / mm; σ E is the dispersion coefficient of material breakdown strength, dimensionless, ranging from 0.1 to 0.15; tadd It is the additional thickness allowance, the unit is μm, and the range is 5 to 10 μm.

[0102] The parameter acquisition method is: the intrinsic breakdown field strength E of the dielectric layer under standard conditions br0 Measured by breakdown experiment, the specific steps include: (1) preparing a sample of standard thickness; (2) placing the sample in a constant temperature and humidity environment; (3) applying a slowly increasing voltage until breakdown; (4) recording the breakdown voltage and calculating the breakdown field strength. The thickness effect index γ is obtained by comparing the breakdown field strength of samples of different thicknesses. Temperature characteristic constant T c , humidity sensitivity coefficient η and impurity influence coefficient ξ are obtained through orthogonal experimental design, that is, the breakdown strength is tested under different temperature, humidity and impurity concentration conditions, and the value of each parameter is determined by multiple regression analysis.

[0103] This dielectric breakdown model is constructed based on the physical mechanism of dielectric breakdown, taking into account multiple influencing factors such as thickness effect, temperature effect, humidity effect and impurity effect. The power term in the equation reflects the nonlinear relationship between the breakdown field strength and thickness, the exponential term describes the mechanism of temperature affecting dielectric properties, the logarithmic term characterizes the humidity effect characteristics, and the linear term reflects the influence of impurity concentration. The thickness design model is based on the worst-case analysis, comprehensively considering voltage fluctuations, material discreteness and safety margin to ensure sufficient safety margin under extreme conditions. The advantage of this system equation is that it integrates multiple environmental factors and material properties, and can guide the optimization of dielectric layer thickness in actual engineering design.

[0104] The electric field tolerance assessment in step S06 involves a leakage current evolution model, which is specifically expressed as follows:

[0105]

[0106] Where, I leak (t) is the surface leakage current at time t, in amperes; I0 is the initial leakage current, in amperes; A is the fast aging coefficient, dimensionless, ranging from 0.01 to 0.05; τ1 is the characteristic time of the fast process, in hours, ranging from 10 to 20 hours; B is the slow aging coefficient, dimensionless, ranging from 0.001 to 0.01; τ2 is the reference time of the slow process, in hours, with a value of 168 hours; n is the aging time index, dimensionless, ranging from 0.3 to 0.7; E is the actual electric field strength, in volts / cm; E th is the threshold electric field at which leakage current increases significantly, in volts / cm; E0 is the characteristic electric field constant, in volts / cm.

[0107] Electric field tolerance criteria:

[0108]

[0109] Where, ΔI max is the maximum change in leakage current, in amperes; I0 is the initial leakage current, in amperes; λ crit is the critical rate of change threshold, dimensionless, and its value is 0.05.

[0110] The parameter acquisition method is as follows: the initial leakage current I0 is measured and obtained by a device characterization tester under standard conditions. The fast aging coefficient A, the fast process characteristic time τ1, the slow aging coefficient B and the aging time index n are obtained by curve fitting the historical test data. The specific steps include: (1) collecting a large number of leakage current variation data of devices under high electric field conditions over time; (2) using the nonlinear least squares method to fit the leakage current model; (3) extracting the best fitting value of each parameter and its statistical distribution. The threshold electric field E th The electric field characteristic constant E0 is determined by a gradient electric field test, that is, the leakage current is measured under different electric field intensities and the functional relationship between the current and the electric field is analyzed.

[0111] This leakage current evolution model is constructed based on dielectric aging and charge trap theory, taking into account the dual effects of fast and slow processes. The exponential term in the equation characterizes the fast trap filling process, the power term describes the slow interface degradation process, and the electric field exponential term reflects the nonlinear dependence of the leakage current on the electric field strength. The model takes into account the accelerating effect of the electric field strength on the aging process, which is consistent with actual physical phenomena. The judgment criterion is based on the relative rate of change of the leakage current and sets a clear acceptable range to facilitate quality control in engineering practice. Compared with the traditional fixed time point detection method, this model can fully capture the dynamic evolution trend of the leakage current and more accurately evaluate the long-term reliability of the device.

[0112] The highly accelerated life test in step S08 involves a failure acceleration model, which is specifically expressed as follows:

[0113]

[0114] Where AF is the acceleration factor, dimensionless; E a is the temperature activation energy, in electron volts, ranging from 0.5 to 1.2 electron volts; k is the Boltzmann constant, with a value of 8.617×10 -5 electron volt / Kelvin; T use T is the normal operating temperature in Kelvin; test is the test temperature in Kelvin; V test is the test voltage in volts; V use is the operating voltage, in volts; γ is the voltage acceleration index, dimensionless, ranging from 2.5 to 3.5; RH testTo test relative humidity, the unit is percentage; RH use is the relative humidity, expressed in percentage; β is the humidity acceleration index, dimensionless, ranging from 2.0 to 3.0; ΔH is the humidity-temperature synergy parameter, expressed in electron volts, ranging from 0.01 to 0.05 electron volts.

[0115] Lifespan prediction model:

[0116]

[0117] Where, t life To predict the device life under actual use conditions, the unit is hours; t test is the failure time under highly accelerated life test conditions, in hours; AF is the acceleration factor, dimensionless; SF i is the reduction factor of the i-th additional stress, dimensionless; m is the number of additional stress types considered.

[0118] The parameter acquisition method is: temperature activation energy E a The life test is carried out at different temperatures. The specific steps include: (1) conducting life tests at different temperatures; (2) recording the average failure time at each temperature; (3) plotting ln(t fail ) and 1 / T; (4) Determine the slope by linear regression and calculate the activation energy. The voltage acceleration index γ and humidity acceleration index β are obtained by variable control method under the condition of fixed other parameters in a similar way. The humidity-temperature synergy parameter ΔH is determined by orthogonal experimental design and variance analysis. The additional stress reduction factor SF i Determined through historical data analysis and expert experience.

[0119] This failure acceleration model refers to a comprehensive extension of the Arrhenius equation, the inverse power law, and the Peck humidity model (temperature and humidity acceleration model), taking into account the triple stress factors of temperature, voltage, and humidity and their interactions. The exponential term in the equation reflects the Arrhenius relationship between the chemical reaction rate and temperature, the power term describes the electric field and humidity acceleration effects, and the interaction term characterizes the synergistic effect of humidity and temperature. Compared with the traditional single stress model, this model more comprehensively considers multiple stresses and synergistic effects, and can more accurately predict the device life under actual usage conditions. The life prediction model further considers other additional stress factors and improves the prediction accuracy by correcting them through reduction coefficients.

[0120] The high electric field stress model in step S10 involves an electro-mechanical coupling equation, which is specifically expressed as follows:

[0121]

[0122] Where σij (r) is the total stress tensor at spatial position r, in Pascals; is the mechanical stress tensor in Pascals; is the Maxwell stress tensor in Pascals; i, j are tensor indices with values of 1, 2, and 3, representing the x, y, and z directions, respectively.

[0123] Maxwell stress tensor calculation formula:

[0124]

[0125] Where ε0 is the dielectric constant of vacuum, which is 8.85×10 -12 Farad / meter; ε r (r) is the relative dielectric constant of the material at position r, dimensionless; E i (r) and E j (r) is the electric field strength tensor component at position r, in volts per meter; δ ij is the Kronecker delta function, which is 1 when i=j and 0 otherwise; k (r) is the polarization intensity tensor component at position r, in coulombs per square meter.

[0126] Prediction model of critical breakdown electric field strength at the interface:

[0127]

[0128] Where, is the critical breakdown electric field strength at the interface position r, in volts / cm; is the intrinsic breakdown field strength of the interface in the stress-free state, in volts / cm; α stress is the stress sensitivity coefficient, dimensionless, ranging from 0.1 to 0.3; σ nn (r) is the normal stress on the interface, in Pascals; σ crit is the critical stress, in Pascals; α curv is the curvature sensitivity coefficient, dimensionless, ranging from 0.2 to 0.4; κ(r) is the curvature at the interface position r, in units of 1 / μm; t die is the thickness of the dielectric layer, in μm; W trap (r) is the trap energy density at position r, in joules per cubic meter; W0 is the reference energy density, in joules per cubic meter.

[0129] The parameter acquisition method is: mechanical stress tensor Obtained through finite element mechanics analysis, taking into account factors such as thermal expansion coefficient mismatch and residual stress. Electric field strength tensor E i(r) Obtained through the electric field distribution simulation in step S01. Polarization intensity P k (r) Through the formula P k (r)=ε0(ε r (r)-1)E k (r) Calculation. Interface intrinsic breakdown field strength under stress-free state Obtained through special sample testing, the specific steps include: (1) preparing stress-released interface samples; (2) performing breakdown tests in a controlled environment; (3) recording the breakdown voltage and calculating the breakdown field strength. Stress sensitivity coefficient α stress and curvature sensitivity coefficient α curv The trap energy density W is determined by combining parameter sweep and experimental verification. trap (r) Obtained by deep level transient spectrometer measurement.

[0130] This electromechanical coupling model is based on Maxwell stress theory induced by electric fields and the mechanical properties of material interfaces, taking into account the combined effects of multiple factors, including electric field distribution, material polarization, interface stress, and microstructure. The stress tensor superposition term in the model reflects the independent superposition effects of mechanical stress and electric field stress. The Maxwell stress tensor formula accounts for the force exerted by the electric field on the dielectric, while the interface critical breakdown model comprehensively considers the effects of stress state, geometric curvature, and trap density on the interface breakdown strength. Compared to traditional methods that simply consider electric field strength, this model can more accurately predict the breakdown behavior at material interfaces in actual devices, providing theoretical guidance for the design of micro-nanochannel structures.

[0131] The main equations involved in the electric field distribution and reliability prediction model in step S11 include the upper-level electric field distribution model and the lower-level material reliability model. The upper-level electric field distribution model is based on a graph neural network structure, in which the key message passing equation is specifically expressed as follows:

[0132]

[0133] Where, is the feature vector of node i in the l-th layer network; is the feature vector of node i in the l+1th layer network; φ is the node feature update function, which is usually implemented using a multi-layer perceptron; is the set of neighbor nodes of node i; c ij is a normalization constant, which is usually taken as the square root of the number of neighbors; ψ is a message generation function, which is also usually implemented using a multilayer perceptron; e ij is the edge feature vector between node i and node j, which contains material interface information.

[0134] The lower-level model of material reliability is based on a long short-term memory network with a hybrid attention mechanism. Its key attention calculation equation is specifically expressed as follows:

[0135]

[0136] Where, α i，t is the weight of the i-th attention head at time step t; e i，t is the energy value of the i-th attention head at time step t; v a 、W a 、U a and b a is the learnable network parameter; s t-1 is the hidden state of the previous time step; h i，t is the feature representation of the i-th attention head at time step t.

[0137] The coupled equations of the two models are:

[0138] f coupling (G, X, t) = λ1f GNN (G, X) + λ2f LSTM (f GNN (G, X), t) + λ3f GNN (G, f LSTM (f GNN (G, X), t-1);

[0139] Where, f coupling is the output function of the coupling model; G is a graph representing the geometric structure and material distribution of the GaN chip; X is the input feature matrix, which contains the working condition parameters; t is the time step; f GNN is the graph neural network function; f LSTM is the long short-term memory network function; λ1, λ2 and λ3 are weight coefficients, satisfying λ1+λ2+λ3=1.

[0140] The parameter acquisition method involves learning the parameters of the graph neural network and long short-term memory network through a data-driven approach. First, a training dataset consisting of 5,000 samples was constructed. Each sample contained geometric and material parameters of the GaN chip, along with the corresponding electric field distribution and failure data. Data augmentation was then performed by randomly perturbing the geometric and material parameters, expanding the dataset to 15,000 samples. The training dataset was used for network parameter optimization, employing a backpropagation algorithm to minimize prediction error. The optimal values of the weight coefficients λ1, λ2, and λ3 were determined using a grid search method. This involved trying different combinations within the range [0, 1] with a step size of 0.1, and selecting the combination with the best performance on the validation set.

[0141] Compared to existing technologies, this electric field distribution and reliability prediction model combines the advantages of graph neural networks and long-short-term memory networks, capable of processing both spatial structural information and time series data. The graph neural network captures the mapping relationship between geometric structure and electric field distribution through a message-passing mechanism, while the long-short-term memory network captures the temporal characteristics of the failure process through an attention mechanism. Coupled equations enable mutual feedback and information exchange between the two sub-models. Compared to traditional purely statistical models or single neural network models, this model can more accurately predict the long-term reliability of complex GaN chips, providing theoretical guidance for design optimization.

[0142] Specifically, the present invention is based on the innovative integration of electric field engineering theory, high-performance materials science, and intelligent predictive models. Fundamentally, the reliability issues of GaN power devices at high voltages stem primarily from localized overstress caused by uneven electric field distribution. This present invention addresses this issue through a multi-dimensional, multi-layered, integrated technical solution.

[0143] First, the present invention uses the principles of electric field engineering to accurately identify high electric field areas in the device through three-dimensional electric field distribution simulation, which is the premise and basis for solving the problem. For the identified high electric field areas, a multi-layer field plate structure and a micro-nano channel structure are designed and implemented. These two structural designs change the electric field distribution characteristics from a physical mechanism. The multi-layer field plate structure expands and disperses the originally concentrated high electric field area by increasing the curvature radius of the electrode edge, effectively reducing the local electric field intensity peak; the micro-nano channel structure creates a local electric field buffer zone by forming a microscopic groove array on the surface, breaking the continuity of the electric field lines and suppressing the formation of the electric field intensity peak. These two structural designs are based on the principle of electric field interaction and achieve uniform electric field distribution through precise control of geometric shape and material interface.

[0144] Secondly, the present invention uses a high-performance material system to improve the overall performance of the packaging structure. The silver sintering process has lower thermal resistance than traditional solder, which can efficiently conduct heat generated by the chip and prevent performance degradation caused by heat accumulation; the high dielectric constant resin layer covers the high electric field area, and its high breakdown strength characteristics provide effective electrical insulation protection for the device; the siloxane-modified polyimide insulating coating is both heat-resistant and hydrophobic, preventing electrical performance degradation in hot and humid environments. The selection and application of these materials are based on material science theory, and a multi-level protection barrier is constructed to meet the special needs of gallium nitride devices in high-voltage and high-temperature working environments.

[0145] Third, the present invention innovatively constructs an electric field distribution and reliability prediction model based on deep learning, which upgrades the traditional empirical design method to a data-driven intelligent prediction method. The model adopts a hierarchical architecture. The upper model captures the mapping relationship between the geometric structure and the electric field distribution, and the lower model predicts the failure behavior of the material under different stress conditions. Through a large amount of data training and physical constraints, the model can accurately predict the expected service life and failure probability of the device, providing scientific guidance for packaging design. This method of combining data-driven and physical models breaks the limitations of traditional empirical design and realizes quantitative evaluation and accurate prediction of packaging reliability.

[0146] In summary, the present invention optimizes electric field distribution through electric field engineering design, improves packaging quality through high-performance materials, and guides design optimization through intelligent prediction models. These three elements work together to form a complete technical solution, solving the reliability problem of gallium nitride power semiconductor devices in high-voltage operating environments.

[0147] A specific embodiment 1 of the present invention is provided below. The specific implementation of each step in this embodiment 1 is described in detail as follows.

[0148] The specific implementation method of step S01 is to construct a three-dimensional geometric model of the gallium nitride chip through finite element analysis software. The model includes all structures such as the gallium nitride epitaxial layer, channel layer, field plate electrode, source, drain and gate. First, input the dielectric constant of each material, such as 9.0 for gallium nitride, 3.9 for silicon dioxide, and 7.5 for silicon nitride, and set the grid density to no less than 10 grid points per μm in the high electric field area and no less than 3 grid points per μm in the low electric field area. Then, under different voltage conditions, the potential distribution is solved using the Poisson equation, and the three-dimensional electric field distribution is obtained by calculating the potential gradient. The specific expression of the Poisson equation is as follows:

[0149]

[0150] Where, is the gradient operator; φ is the electric potential field function, in volts; ε r is the relative dielectric constant of the material, dimensionless; ε0 is the dielectric constant of vacuum, which is 8.85×10 -12 Farad / meter; ρ is the charge density distribution function, with the unit of coulomb / cubic meter.

[0151] Under boundary conditions, the potential difference between the source and drain is expressed as:

[0152] φ DS =φ D -φ S =V DS ;

[0153] Where, φ Dis the drain potential in volts; φ S is the source potential, usually set to 0 volts; V DS is the source-drain voltage in volts.

[0154] After solving the above Poisson equation to obtain the potential distribution, the electric field strength calculation formula is:

[0155]

[0156] Where, is the electric field strength vector, in volts per meter.

[0157] The scalar value of the electric field strength is calculated as:

[0158]

[0159] Where, E x 、E y 、E z are the components of the electric field strength in the x, y, and z directions, respectively, and the unit is volts per meter.

[0160] For electric field strengths exceeding 3×10 6 The system uses an adaptive marking algorithm to identify regions with high volts / cm, typically located at the gate edge and field plate terminations. Based on this electric field distribution data, a parameter sweep optimizes the electrode spacing, setting it within the 20 to 30 μm range. The dielectric thickness is also optimized to 3 to 5 μm, ensuring sufficient dielectric strength without excessively increasing thermal resistance. These parameters are determined by comparing the maximum electric field strength under different geometries. The ultimate optimization goal is to reduce the maximum electric field strength to below the critical breakdown field while maintaining good device conduction characteristics.

[0161] The specific implementation method of step S02 is to use a high thermal conductivity aluminum nitride ceramic material as a heat dissipation substrate. The thermal conductivity of this material is 170 to 220 watts / meter Kelvin, which is much higher than that of traditional alumina ceramics. The back of the gallium nitride chip is plated with three layers of titanium / nickel / silver metal with thicknesses of 50 nanometers / 200 nanometers / 1000 nanometers respectively to enhance the bonding strength with the nano-silver paste. The particle size of the nano-silver paste is controlled within the range of 20 to 50 nanometers, and the solid content is 85% to 90%. Under vacuum atmosphere conditions, the temperature is raised to 250 to 300°C at a heating rate of 2 to 5°C / minute, and the holding time is 30 to 45 minutes to sinter the nano-silver particles to form a dense silver interconnection layer. The thermal resistance calculation adopts the heat conduction equation, which is specifically expressed as follows:

[0162]

[0163] Where R this the thermal resistance value, in square cm·°C / W; t is the thickness of the silver sintering layer, in μm; k is the thermal conductivity of the silver sintering layer, in W / m·Kelvin; A is the chip contact area, in square cm; R int1 is the thermal resistance between the chip and the silver sintering layer, in square cm·°C / W; R int2 is the thermal resistance of the interface between the silver sintered layer and the ceramic substrate, in square cm·°C / W; R sp is the thermal resistance coefficient of the heat dissipation path, in square cm·°C / W; n is the number of parallel heat channels, dimensionless.

[0164] Calculation formula for interface thermal resistance:

[0165]

[0166] Where R int is the interfacial thermal resistance, in square cm·degrees Celsius / W; γ is the interface roughness correlation coefficient, dimensionless, ranging from 0.5 to 2.0; P is the interfacial pressure, in MPa; k1 and k2 are the thermal conductivity of the materials on both sides, respectively, in W / m·K; ρ1 and ρ2 are the densities of the materials on both sides, respectively, in kg / m3; c1 and c2 are the specific heat capacities of the materials on both sides, respectively, in joule / kg·Kelvin.

[0167] After implementing this process, the thermal resistance of the heat conduction path formed between the chip and the substrate is less than 0.1 square cm·degrees Celsius / watt, which can effectively dissipate the heat generated by the device under high-frequency and high-power operating conditions, preventing device performance degradation and reliability reduction caused by heat accumulation.

[0168] The specific implementation method of step S03 is to use photolithography and metal deposition technology to realize the production of multi-layer field plate structure. First, a silicon dioxide or silicon nitride dielectric layer with a thickness of 200 to 300 nanometers is deposited on the surface of the gallium nitride chip by plasma enhanced chemical vapor deposition process. A pattern is formed by photoresist coating, exposure and development, and then a step-like structure is formed on the dielectric layer by reactive ion etching process, and the thickness of the dielectric layer at different steps decreases successively. Subsequently, a titanium layer (with a thickness of 50 to 80 nanometers), an aluminum layer (with a thickness of 400 to 600 nanometers), a nickel layer (with a thickness of 50 to 100 nanometers) and a gold layer (with a thickness of 200 to 300 nanometers) are deposited in sequence by electron beam evaporation or magnetron sputtering technology to form a multi-layer field plate electrode structure with a total thickness of 0.8 to 1.2 μm. The field plate electric field modulation equation is used to calculate the multi-layer field plate effect, which is specifically expressed as follows:

[0169]

[0170] Where, E peakis the peak electric field intensity after field plate modulation, in volts / cm; E0 is the peak electric field intensity without field plate, in volts / cm; β is the field plate efficiency coefficient, dimensionless, ranging from 0.3 to 0.6; L FP L is the field plate extension length, in μm; GD is the distance from source to drain, in μm; t die is the thickness of the dielectric layer, in μm; t FP is the field plate metal thickness, in μm; α is the thickness influence index, dimensionless, ranging from 0.2 to 0.5; δ is the position correction coefficient, dimensionless, ranging from 0.1 to 0.3; x is the distance from the gate edge to the measurement point, in μm.

[0171] Calculation of the effective electric field distribution of the multilayer field plate structure:

[0172]

[0173] Where, E eff (x, y, z) is the effective electric field intensity distribution function after considering the multilayer field plate structure, in volts / cm; E i (x, y, z) is the electric field intensity distribution function independently contributed by the i-th field plate, in volts / cm; w i is the weight coefficient of the i-th field plate, dimensionless, satisfying is the shortest distance from the spatial point (x, y, z) to the i-th field plate, in μm; i is the electric field attenuation characteristic length of the i-th field plate, in μm; n is the number of field plate layers.

[0174] The multilayer field plate structure extends from the source to the drain, with an extension length of 25% to 40% of the source-to-drain distance. This multilayer field plate structure effectively reduces the peak electric field intensity by increasing the curvature radius of the electrode edge. Theoretically, it can reduce the peak electric field intensity by 30% to 50%, significantly improving the breakdown voltage and reliability of the device.

[0175] The specific implementation of step S04 is to select a high dielectric constant resin material, such as polyaryletherketone or epoxy-modified polyimide, with a dielectric constant between 4.0 and 6.0 and a breakdown strength of not less than 500KV / mm. First, the chip surface is plasma treated to improve surface wettability and adhesion. Then, a precision dispensing device is used to precisely control the application of a high dielectric constant resin layer between the chip and the lead frame. The temperature of the dispensing head is controlled at 30 to 40°C, the dispensing pressure is 0.2 to 0.4 MPa, and the dispensing speed is 5 to 10 mm / second. The specific representation of the dielectric layer breakdown model is as follows:

[0176]

[0177] Where, E br is the actual breakdown field strength of the dielectric layer, in KV / mm; E br0 is the intrinsic breakdown field strength of the dielectric layer under standard conditions, in KV / mm; t is the actual thickness of the dielectric layer, in μm; t0 is the reference thickness, which is 1 μm; γ is the thickness effect index, dimensionless, ranging from 0.2 to 0.4; T is the operating temperature, in Kelvin; T0 is the reference temperature, which is 298 Kelvin; T c is the temperature characteristic constant, in Kelvin, ranging from 50 to 100 Kelvin; η is the humidity sensitivity coefficient, dimensionless, ranging from 0.05 to 0.15; RH is the relative humidity, in percentage; RH0 is the reference relative humidity, with a value of 50%; ξ is the impurity influence coefficient, dimensionless, ranging from 0.8 to 1.2; f imp is the normalized function of impurity concentration, dimensionless, ranging from 0 to 0.5.

[0178] High dielectric constant resin layer thickness design model:

[0179]

[0180] Where, t min is the minimum safe thickness of the high dielectric constant resin layer, in μm; V max is the maximum operating voltage in volts; σ V is the voltage fluctuation coefficient, dimensionless, ranging from 0.1 to 0.2; K sf is the safety factor, dimensionless, ranging from 1.5 to 2.5; E br is the dielectric breakdown field strength, in KV / mm; σ E is the dispersion coefficient of material breakdown strength, dimensionless, ranging from 0.1 to 0.15; t add It is the additional thickness allowance, the unit is μm, and the range is 5 to 10 μm.

[0181] After the resin is coated, it is pre-cured at 60 to 80°C for 1 to 2 hours, and then finally cured at 150 to 180°C for 2 to 3 hours. The thickness of the high dielectric constant resin layer after curing is controlled at 50 to 100μm, and the thickness uniformity deviation is controlled within the range of ±5%. The high dielectric constant resin layer completely covers the high electric field areas identified in step S01 to ensure that the electric field strength in these areas is reduced to a safe level. In addition, the addition of nano-alumina particles (content of 2% to 5%) to the resin can further improve the thermal conductivity and mechanical strength of the resin, reduce the thermal expansion coefficient, and reduce the risk of failure caused by thermal stress.

[0182] The specific implementation of step S05 is to select an epoxy molding compound with an ion content of less than 10 parts per million, a temperature cycling reliability rating meeting JEDEC standard J-STD-020D Level 3, and a glass transition temperature exceeding 150°C. The mold is first vacuum preheated at 80 to 100°C for 60 to 90 minutes to completely remove moisture and gas from the mold. The epoxy molding compound is then preheated to 90 to 110°C to reduce viscosity, and then infused using a vacuum injection molding process at 120 to 150°C and a pressure of 5 to 8 MPa. During the injection molding process, a vacuum of at least 10 Pascals is maintained, and the injection speed is controlled at 5 to 10 cubic centimeters per second. After injection molding, the mold is cured in stages, initially at 150 to 170°C for 1 to 2 hours, then at 180 to 200°C for 2 to 3 hours, and finally slowly cooled to room temperature at a cooling rate not exceeding 2°C per minute. This multi-stage curing process effectively reduces internal stress and prevents bubbles and delamination during the packaging process. After curing, the package quality is assessed using ultrasonic scanning and X-ray inspection technology to ensure that there are no voids, cracks, or delamination inside the package, and that the contact interfaces are well bonded.

[0183] The specific implementation method of step S06 is to build a high-voltage electric field tolerance test platform, which includes a high-precision voltage source (accuracy better than 0.1%), a microcurrent measurement system (accuracy reaches nanoampere level) and a constant temperature control system (temperature fluctuation is controlled within ±0.5°C). First, the packaged gallium nitride chip is stabilized at an ambient temperature of 25±2°C, and the voltage is gradually applied to 120% of the rated operating voltage, and the voltage rise rate is controlled at 1% of the rated voltage per second. After reaching the target voltage, the constant voltage state is maintained for 168 hours (7 days), during which the surface leakage current value is recorded every 6 hours. The leakage current evolution model is specifically expressed as follows:

[0184]

[0185] Where, I leak (t) is the surface leakage current at time t, in amperes; I0 is the initial leakage current, in amperes; A is the fast aging coefficient, dimensionless, ranging from 0.01 to 0.05; τ1 is the characteristic time of the fast process, in hours, ranging from 10 to 20 hours; B is the slow aging coefficient, dimensionless, ranging from 0.001 to 0.01; η2 is the reference time of the slow process, in hours, with a value of 168 hours; n is the aging time index, dimensionless, ranging from 0.3 to 0.7; E is the actual electric field strength, in volts / cm; E th is the threshold electric field at which leakage current increases significantly, in volts / cm; E0 is the characteristic electric field constant, in volts / cm.

[0186] Electric field tolerance criteria:

[0187]

[0188] Where, ΔI max is the maximum change in leakage current, in amperes; I0 is the initial leakage current, in amperes; λ crit is the critical rate of change threshold, dimensionless, and its value is 0.05.

[0189] During the test, relative humidity was maintained between 40% and 60% to eliminate humidity effects. After the test, the leakage current was analyzed over time to ensure that its variation did not exceed 5% of the original value. If the leakage current variation exceeded the threshold, the electrode structure and dielectric layer quality in the high electric field area were inspected, and steps S03 and S04 were optimized and adjusted. This test verifies the stability of the package structure under long-term high electric field stress and evaluates the electric field distribution at the electrode edge and the performance of the dielectric material.

[0190] The specific implementation of step S07 is the same as above and will not be described in detail here.

[0191] The specific implementation method of step S08 is to use a highly accelerated life test system that complies with the JEDEC standard JESD22-A110, which has a temperature control accuracy of ±0.5°C and a humidity control accuracy of ±2%. The packaged gallium nitride chip is placed in the test chamber, and the ambient temperature is set to 125°C and the relative humidity is 85%. Before the test, the chip is pretreated and baked at 60°C for 24 hours to remove adsorbed moisture. After the test starts, 80% of the rated voltage is applied between the drain and source of the chip, and the gate voltage is set to the off state below the threshold voltage. The failure acceleration model is specifically expressed as follows:

[0192]

[0193] Where AF is the acceleration factor, dimensionless; E a is the temperature activation energy, in electron volts, ranging from 0.5 to 1.2 electron volts; k is the Boltzmann constant, with a value of 8.617×10 -5 electron volt / Kelvin; T use T is the normal operating temperature in Kelvin; test is the test temperature in Kelvin; V test is the test voltage in volts; V use is the operating voltage, in volts; γ is the voltage acceleration index, dimensionless, ranging from 2.5 to 3.5; RH test To test relative humidity, the unit is percentage; RH useis the relative humidity, expressed in percentage; β is the humidity acceleration index, dimensionless, ranging from 2.0 to 3.0; ΔH is the humidity-temperature synergy parameter, expressed in electron volts, ranging from 0.01 to 0.05 electron volts.

[0194] Lifespan prediction model:

[0195]

[0196] Where, t life To predict the device life under actual use conditions, the unit is hours; t test is the failure time under highly accelerated life test conditions, in hours; AF is the acceleration factor, dimensionless; SF i is the reduction factor of the i-th additional stress, dimensionless; m is the number of additional stress types considered.

[0197] The test lasted 1000 hours, with leakage current recorded hourly using a high-precision source meter (SMU) with a resolution better than 10 nanoamperes. After the test, a leakage current curve was plotted over time, and the slope and breakpoints were analyzed to identify potential failure mechanisms such as electrode migration, dielectric breakdown, or interface degradation. Scanning electron microscopy and energy spectrum analysis were also used to examine chip surface morphology and composition changes, verifying the stability of the package structure under the triple stresses of high temperature, high humidity, and high voltage.

[0198] The specific implementation of step S09 is the same as above and will not be described in detail here.

[0199] The specific implementation of step S10 is to construct a high electric field stress model based on the three-dimensional electric field distribution simulation results of step S01. This model integrates Maxwell stress tensor theory and finite element analysis to calculate the mechanical stress distribution caused by the electric field. The electro-mechanical coupling equation is specifically expressed as follows:

[0200]

[0201] Where σ ij (r) is the total stress tensor at spatial position r, in Pascals; is the mechanical stress tensor in Pascals; is the Maxwell stress tensor in Pascals; i, j are tensor indices with values of 1, 2, and 3, representing the x, y, and z directions, respectively.

[0202] Maxwell stress tensor calculation formula:

[0203]

[0204] Where ε0 is the dielectric constant of vacuum, which is 8.85×10 -12Farad / meter; ε r (r) is the relative dielectric constant of the material at position r, dimensionless; E i (r) and E j (r) is the electric field strength tensor component at position r, in volts per meter; δ ij is the Kronecker delta function, which is 1 when i=j and 0 otherwise; k (r) is the polarization intensity tensor component at position r, in coulombs per square meter.

[0205] Prediction model of critical breakdown electric field strength at the interface:

[0206]

[0207] Where, is the critical breakdown electric field strength at the interface position r, in volts / cm; is the intrinsic breakdown field strength of the interface in the stress-free state, in volts / cm; α stress is the stress sensitivity coefficient, dimensionless, ranging from 0.1 to 0.3; σ nn (r) is the normal stress on the interface, in Pascals; σ crit is the critical stress, in Pascals; α curv is the curvature sensitivity coefficient, dimensionless, ranging from 0.2 to 0.4; κ(r) is the curvature at the interface position r, in units of 1 / μm; t die is the thickness of the dielectric layer, in μm; W trap (r) is the trap energy density at position r, in joules per cubic meter; W0 is the reference energy density, in joules per cubic meter.

[0208] First, the electric field strength is increased to more than 2.5×10 6The area with a voltage of 30 kiloelectron volts / cm is identified as a high electric field stress area. Then, a focused ion beam system is used, which is equipped with a gallium ion source, an acceleration voltage of 30 kiloelectron volts, and an adjustable beam current range of 10 picoamperes to 10 nanoamperes. In the high electric field area, the gate spacing (i.e., the spacing between gates) is used as a reference, and an automated pattern generation algorithm is used to design the layout of the micro-nano channel structure. The focused ion beam forms a parallel channel structure in the high electric field area, with the channel depth controlled at 1 to 2 μm, the width at 0.5 to 1 μm, and the spacing between adjacent channels at 5 to 10 μm. During the etching process, the ion beam current density is controlled at 0.1 to 0.5 picoamperes / square μm, and the etching rate is approximately 0.1 μm / minute to ensure etching quality and dimensional accuracy. These micro-nano channels reduce the peak electric field intensity by changing the surface electric field distribution. Theoretical calculations show that the peak electric field intensity can be reduced by 15% to 25%. At the same time, the channel structure increases the surface area, improves heat dissipation, and acts as a charge trap to capture surface free charges, forming a local electric field buffer zone, suppressing electric field concentration, and improving the stability and reliability of the device under high voltage working conditions.

[0209] The specific implementation of step S11 is to construct an electric field distribution and reliability prediction model based on the GaN chip geometric parameters, material parameters, electric field distribution data, and surface leakage current data obtained in the previous steps. This model consists of an upper-level electric field distribution model and a lower-level material reliability model. The upper-level electric field distribution model is based on a graph neural network structure, and its message passing equation is specifically expressed as follows:

[0210]

[0211] Where, is the feature vector of node r in the l-th layer network; is the feature vector of node i in the l+1th layer network; φ is the node feature update function, which is usually implemented using a multi-layer perceptron; is the set of neighbor nodes of node i; c ij is a normalization constant, which is usually taken as the square root of the number of neighbors; ψ is a message generation function, which is also usually implemented using a multilayer perceptron; e ij is the edge feature vector between node i and node j, which contains material interface information.

[0212] The lower-level model of material reliability is based on a long short-term memory network with a hybrid attention mechanism. Its attention calculation equation is specifically expressed as follows:

[0213]

[0214] Where, α i，t is the weight of the i-th attention head at time step t; e i，t is the energy value of the i-th attention head at time step t; va 、W a 、U a and b a is the learnable network parameter; s t-1 is the hidden state of the previous time step; h i，t is the feature representation of the i-th attention head at time step t.

[0215] The coupled equations of the two models are:

[0216] f coupling (G, X, t) = λ1f GNN (G, X) + λ2f LSTM (f GNN (G, X), t) + λ3f GNN (G, f LSTM (f GNN (G, X), t-1);

[0217] Where, f coupling is the output function of the coupling model; G is a graph representing the geometric structure and material distribution of the GaN chip; X is the input feature matrix, which contains the working condition parameters; t is the time step; f GNN is the graph neural network function; f LSTM is the long short-term memory network function; λ1, λ2 and λ3 are weight coefficients, satisfying λ1+λ2+λ3=1.

[0218] To better understand and implement the present invention, Example 2 of a specific application scenario is provided below: Researchers used the enhanced packaging method for gallium nitride power semiconductor devices of the present invention to fabricate a high-voltage gallium nitride power switch device for use in electric vehicle fast-charging systems. This application scenario requires the device to have a rated breakdown voltage of 1200V and a rated current of 25A. Furthermore, the device must maintain stable operation over a wide temperature range of -40°C to 125°C and withstand harsh temperature and humidity environments.

[0219] First, the researchers simulated the three-dimensional electric field distribution of the GaN epitaxial wafer. A complete three-dimensional geometric model was constructed using COMSOL Multiphysics software. The model included a 5.2μm thick GaN epitaxial layer, a 1.8μm thick AlGaN barrier layer, a source, drain, and gate electrode structure. During the simulation, the potential distribution was obtained by solving the Poisson equation, where the relative dielectric constant was set to 9.0 for GaN, 8.6 for AlGaN, and 3.9 for the SiO2 dielectric layer. The simulation results showed that the electric field strength in the gate edge region reached 3.78×10 6V / cm, far exceeding the critical breakdown electric field strength of GaN materials. Through parameter scanning optimization, the optimal structural parameters of the electrode spacing of 26μm and the dielectric layer thickness of 4.2μm were determined, as shown in Table 1:

[0220] Table 1 Optimized electrode structure parameters

[0221] Structural parameters Initial value Optimized value Improvement effect Gate-drain spacing 18μm 26μm Maximum electric field reduced by 22% Dielectric layer thickness 2.8μm 4.2μm Surface leakage current reduced by 35% Field plate extension length 3.5μm 8.2μm Electric field uniformity improved by 40% Field plate edge curvature 0.5μm 2.1μm The peak value of the fringe electric field is reduced by 28%

[0222] Next, the researchers used an aluminum nitride ceramic substrate as a heat dissipation substrate with a thermal conductivity of 185W / m·K. A nanosilver sintering process was used for chip bonding. The average particle diameter of the nanosilver paste was 35nm and the solid content was 87%. In a vacuum environment, the temperature was raised to 280°C at a rate of 3°C / min and the holding time was 40 minutes, forming a silver sintering layer with a thickness of 15μm. The thermal resistance value from the chip to the substrate was measured to be 0.072cm by transient thermal resistance test. 2 ℃ / W, much lower than the 0.18cm of traditional solder connection 2 °C / W, as shown in Table 2:

[0223] Table 2 Comparison of thermal performance of different bonding processes

[0224]

[0225] Subsequently, the researchers designed a three-layer field plate structure on the surface of the gallium nitride chip, which is composed of titanium (70nm) / aluminum (550nm) / nickel (80nm) / gold (250nm) metal layers in sequence, with a total thickness of 0.95μm. The field plate structure extends from the source to the drain, and the extension length is 32% of the source-drain distance. The calculation results based on the field plate electric field modulation equation show that the multi-layer field plate structure reduces the peak electric field intensity from 3.78×10 6 V / cm was reduced to 2.12×10 6 V / cm, a decrease of 43.9%. At the same time, the electric field distribution is more uniform, and the edge electric field gradient is reduced by 52%.

[0226] Between the chip and the leadframe, the researchers applied a layer of modified polyaryletherketone (PAEK) high-dielectric-constant resin with a dielectric constant of 5.2 and a breakdown strength of 625 kV / mm. Precision dispensing equipment controlled the resin layer thickness to 85 μm, with thickness uniformity within ±3.5%. Adding 3.5% nanoalumina particles to the resin increased thermal conductivity to 0.8 W / m·K while reducing the coefficient of thermal expansion to 22 ppm / °C, as shown in Table 3.

[0227] Table 3 Performance parameters of high dielectric constant resin layer

[0228] Performance parameters Numerical Test Method Dielectric constant 5.2 Impedance Analyzer @1MHz Breakdown strength 625kV / mm High voltage breakdown test Thermal conductivity 0.8W / m·K Laser flash method Coefficient of thermal expansion 22ppm / ℃ Thermomechanical Analyzer Glass transition temperature 218℃ Differential Scanning Calorimetry Volume resistivity <![CDATA[2.8×10 14 Ohm cm]]> High resistance meter

[0229] The primary package is made of low-ion epoxy molding compound, with a chloride ion content of only 5.2ppm and a sodium ion content of 3.8ppm. Vacuum injection molding is performed at 135°C and a pressure of 6.5MPa to ensure the absence of bubbles and delamination. X-ray inspection and ultrasonic scanning results show no internal defects in the package and good interface bonding.

[0230] Researchers conducted electric field tolerance tests on packaged GaN chips, applying a high voltage of 1440V (120% of the rated voltage of 1200V) for 168 hours. The measured surface leakage current changed by only 3.2% of its original value, well below the required limit of 5%. The test data were consistent with the predictions of the surface leakage current evolution model, with a rapid aging coefficient A of 0.022, a slow aging coefficient B of 0.005, and an aging time exponent n of 0.42.

[0231] The outer layer of the chip was coated with a siloxane-modified polyimide insulating coating with a thickness of 18μm and cured at 200°C for 80 minutes. The coating achieved a contact angle of 112 degrees, demonstrating excellent moisture resistance. A highly accelerated life test was conducted at 125°C / 85% RH for 1000 hours, during which 80% of the rated voltage (960V) was applied. The leakage current curve recorded during the test is shown in Table 4:

[0232] Table 4 Leakage current change data in highly accelerated life test

[0233] Test time (hours) Leakage current (nA) Relative rate of change (%) 0 58.2 0 100 62.4 7.2 200 65.3 12.2 300 67.1 15.3 400 68.5 17.7 500 69.4 19.2 600 70.2 20.6 700 70.8 21.6 800 71.2 22.3 900 71.5 22.9 1000 71.8 23.4

[0234] Thermal cycling testing completed 500 cycles between -40°C and 150°C, with a heating rate of 15°C / min and a cooling rate of 10°C / min. The test results demonstrated that the package structure remained intact, with no delamination or cracking. The change in electrical parameters before and after testing was less than 10%, demonstrating the package's excellent thermomechanical stability.

[0235] The researchers used focused ion beam technology to form a micro-nano channel structure in the high electric field area. The channel depth was 1.5μm, the width was 0.8μm, and the spacing was 7.5μm. This structure effectively reduced the peak of the surface electric field intensity and reduced the local electric field concentration phenomenon. Surface scanning electron microscopy showed that the micro-nano channel structure was evenly distributed in the high field area and did not cause damage to the main structure of the device. The final chip structure and its partial structure are shown in Figure 2. Figure 2-5 As shown; the heat dissipation direction of the chip is as follows Figure 6 shown.

[0236] Finally, the device's performance was evaluated based on an electric field distribution and reliability prediction model. The model's graph neural network consists of four graph convolutional layers, each with 96 kernels. The long short-term memory network uses six attention heads and has a hidden layer dimension of 192. Prediction results show that under normal operating conditions (85°C, 60% RH, and 90% of rated voltage), the device has an expected service life of over 100,000 hours, with a failure probability of less than 0.1% over a 10-year lifetime.

[0237] Traditional GaN power device packaging methods primarily utilize a single-layer field plate structure and conventional epoxy resin encapsulation. These methods lack specialized structural optimization for high-electric-field regions and employ a highly thermally conductive silver sintering process. These traditional methods are prone to device performance degradation and failure in high-temperature, high-humidity, and high-voltage environments. The mean time between failures (MTBF) is typically less than 30,000 hours, and reliability is poor in temperature cycling and high-humidity environments. Traditional methods primarily rely on increasing safety margins to ensure reliability, such as reducing operating voltage or increasing design dimensions. This results in devices that cannot fully utilize their performance.

[0238] Compared to traditional methods, the enhanced packaging method provided by this invention optimizes structural parameters through three-dimensional electric field simulation, employs a multilayer field plate structure to reduce peak electric field intensity, uses a silver sintering process to improve heat dissipation, forms micro-nanochannel structures in high-field areas to alleviate electric field concentration, and combines a high-dielectric-constant resin layer and a siloxane-modified polyimide outer layer for protection, significantly improving device reliability and service life. In particular, the design optimization method based on electric field distribution and reliability prediction models achieves a shift from empirical design to theoretically guided design, significantly improving product development efficiency.

[0239] It should be noted that the variables involved in the present invention are explained in detail as shown in Tables 5, 6 and 7 below.

[0240] Table 5 Variable Explanation Table (Part 1)

[0241]

[0242] Table 6 Variable Explanation Table (Part 2)

[0243]

[0244]

[0245] Table 7 Variable Explanation Table (Part 3)

[0246]

[0247]

[0248] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed by the present invention, which should be covered by the scope of protection of the present invention.

Claims

1. A packaging method for an enhancement-mode gallium nitride power semiconductor device, characterized in that: include: Perform three-dimensional electric field distribution simulation on the GaN chip and optimize the electrode spacing and dielectric layer thickness based on the simulation data. Secure the GaN chip to a heat dissipation substrate to form a heat conduction path. The GaN chip surface electrodes are designed using a multi-layer field plate structure; a high-dielectric-constant resin layer is applied between the GaN chip and the lead frame; low-ion content epoxy molding compound is used for primary packaging; the packaged GaN chip undergoes electric field tolerance testing; a siloxane-modified polyimide insulating coating is applied to the outer layer of the GaN chip; and highly accelerated life testing and thermal cycling tests are performed. Focused ion beam technology is used to form micro-nano channel structures in high electric field areas, and a local electric field buffer zone is constructed to complete the packaging. The electric field distribution and reliability prediction model is used to calculate the expected service life and failure probability curve of the packaged gallium nitride chip.

2. The packaging method of the enhancement-mode gallium nitride power semiconductor device according to claim 1, characterized in that: The three-dimensional electric field distribution simulation includes the following steps: 6 The areas with a volt / cm are marked, and the electrode spacing is optimized to be 20 to 30 μm and the dielectric layer thickness is optimized to be 3 to 5 μm based on the three-dimensional electric field distribution simulation data.

3. The packaging method of the enhancement-mode gallium nitride power semiconductor device according to claim 1, characterized in that: Fixing the gallium nitride chip on the heat dissipation substrate includes fixing the gallium nitride chip on a heat dissipation substrate made of aluminum nitride ceramic material, using a silver sintering process to bond the chip at a temperature of 250 to 300°C, and forming a heat conduction path with a thermal resistance value of less than 0.1 square cm·degrees Celsius / watt.

4. The packaging method of the enhancement-mode gallium nitride power semiconductor device according to claim 1, characterized in that: The multilayer field plate structure is formed by sequentially depositing titanium, aluminum, nickel, and gold. The total thickness of the multilayer field plate structure is 0.8 to 1.2 μm, and the extension length of the multilayer field plate structure is 25% to 40% of the distance from the source to the drain.

5. The packaging method of the enhancement-mode gallium nitride power semiconductor device according to claim 1, characterized in that: The high dielectric constant resin layer has a breakdown strength of not less than 500 KV / mm, a thickness of the high dielectric constant resin layer is 50 to 100 μm, and the high dielectric constant resin layer covers the entire high electric field region.

6. The packaging method of the enhancement-mode gallium nitride power semiconductor device according to claim 1, characterized in that: The primary packaging using low-ion content epoxy molding compound includes a vacuum injection molding process performed at 120 to 150° C. and a pressure of 5 to 8 MPa to ensure that there are no bubbles or delamination.

7. The packaging method of the enhancement-mode gallium nitride power semiconductor device according to claim 1, characterized in that: The electric field tolerance test of the packaged gallium nitride chip includes applying a voltage 20% higher than the rated operating voltage for 168 hours, and measuring the surface leakage current change within 5% of the original value.

8. The packaging method of the enhancement-mode gallium nitride power semiconductor device according to claim 1, characterized in that: The thickness of the siloxane-modified polyimide insulating coating is 15 to 25 μm, the curing temperature is 180 to 220° C., and the curing time is 60 to 90 minutes.

9. The packaging method of the enhancement-mode gallium nitride power semiconductor device according to claim 1, characterized in that: The electric field distribution and reliability prediction model performs calculations based on the acquired geometric parameters, material parameters, electric field distribution data, and surface leakage current data of the gallium nitride chip, and outputs the expected service life and failure probability curve of the gallium nitride chip.

10. The packaging method of an enhancement-mode gallium nitride power semiconductor device according to claim 1, wherein: The structure of the electric field distribution and reliability prediction model is a hierarchical deep learning framework consisting of an upper-layer electric field distribution model and a lower-layer material reliability model; The electric field distribution upper-layer model uses a geometric structure perception module based on a graph neural network to extract the physical structure characteristics of the gallium nitride chip, and the material reliability lower-layer model uses a long short-term memory network with a hybrid attention mechanism to predict the life evolution curve of the gallium nitride chip under different stress conditions.

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