Preparation method of electronic component package based on DPC technology

Abstract

The invention discloses a preparation method of an electronic component package based on a DPC process. The electronic component package comprises a cover plate, an enclosure frame, a top gold-plated copper layer, solid copper columns, an aluminum oxide substrate and a bottom gold-plated copper layer, wherein the cover plate is arranged at the upper part of the enclosure frame, and an airtight space is formed by the cover plate, the enclosure frame and the top gold-plated copper layer; the enclosure frame is arranged at the upper part of the top gold-plated copper layer; the top gold-plated copper layer is arranged at the upper part of the aluminum oxide substrate; the solid copper column is arranged in the aluminum oxide substrate; and the aluminum oxide substrate is arranged on the bottom gold-plated copper layer. According to the invention, the packaging requirements of high-power microwave electronic components are met, the thermal conductivity is high, the radio frequency performance in the frequency band of 0.1 MHz to 20GHz is excellent, and the packaging structure has the advantages of high bearing temperature, easy observation of the welding condition, miniaturization, high integration level and the like.

Description

Technical Field

[0001] The present invention belongs to the field of microwave radio frequency device packaging, and in particular relates to a preparation method for electronic component packaging based on a DPC process. Background Art

[0002] In recent years, electronic devices have been developing towards miniaturization, lightweighting, and low cost, leading to an increasingly urgent need to increase the integration of microwave and radio frequency modules. HTCC and LTCC processes, with their advantages such as high integration density, multi-layer coordinated microwave / digital / control wiring, and excellent high-frequency performance, have become the primary means of achieving miniaturized, high-density integrated, and multifunctional modules. However, the thermal conductivity of the substrate is only 2-3 W / mK, and that of the HTCC substrate is only around 16 W / mK, making them unable to meet the packaging requirements of high-power microwave integrated circuits.

[0003] Chinese patent CN204204832U discloses a heat dissipation cavity structure based on LTCC. It provides a heat dissipation path for the chip through the combination of LTCC, Kovar cavity, and tungsten copper inserts. However, it greatly increases the process complexity. The heat dissipation efficiency of tungsten copper is limited, and the use of high-density tungsten copper material is not conducive to device lightweighting.

[0004] The direct copper plating (DPC) process electroplates micron-thick copper on the surface of the alumina substrate 5 and densely arranges solid copper pillars 6 within the substrate, effectively improving the substrate's thermal conductivity and meeting the needs of electronic components with high heat dissipation requirements. However, ceramic substrates manufactured according to traditional DPC design rules will experience ceramic cracking if the temperature exceeds 320°C. If the frame 2 is sintered at 300°C using gold-tin solder, the highly thermally conductive gold-tin solder cannot be used to assemble high-power electronic components, otherwise it will cause the frame 2 to remelt, seriously affecting airtightness. The DPC process cannot design sidewall mounting holes or gold plating at the bottom pad position of the substrate, resulting in the inability to observe tin creep from the outside during soldering on the bottom of the package. If pins are not soldered or solder joints are poorly soldered, it is difficult to troubleshoot. Summary of the Invention

[0005] The present invention proposes a preparation method for electronic component packaging based on a DPC process, which utilizes the good thermal conductivity of a DPC substrate to package high-power electronic components. Taking into account the sintering temperature curve and the characteristics of the DPC substrate, the design rules are optimized through repeated experiments and exploration, and the minimum hole-edge spacing of the solid copper pillars is expanded from the traditional 0.4 mm to 0.62 mm, and the maximum temperature tolerance of the DPC substrate is increased from 320°C to 410°C. The frame is sintered to the top gold-plated copper layer using gold-germanium (Au88Ge12) solder, providing a temperature gradient for sintering the chip inside the package using gold-tin solder at 300°C. The gold-plated copper layer at the bottom of the package is designed with a three-dimensional pattern, so that the DPC package can observe the welding condition of the package bottom and optimize its radio frequency performance. At a frequency of 20 GHz, the return loss is improved by 8 dB and the insertion loss is improved by 0.1 dB compared with the previous method. The cover plate is mounted on the frame using a parallel seam welding process to form an airtight space.

[0006] The technical solution to achieve the present invention is: a preparation method for electronic component packaging based on the DPC process, the preparation steps are as follows:

[0007] Step 1: Use laser to drill holes on the alumina substrate.

[0008] Step 2: Use magnetron sputtering to sputter a seed layer on the top and bottom surfaces of the alumina substrate according to the design pattern, and then use exposure and development processes to complete the patterning of the circuit.

[0009] Step 3: Electroplating copper on the alumina substrate after circuit patterning to produce a top copper layer, a middle solid copper column, and a bottom copper layer.

[0010] Step 4: Electroplating nickel and gold on the surfaces of the two copper layers of the alumina substrate respectively to complete the production of the top gold-plated copper layer and the bottom gold-plated copper layer.

[0011] Step 5: Cut the alumina substrate of step 4 to obtain a bottom substrate for electronic component packaging, hereinafter referred to as a DPC substrate.

[0012] Step 6: Solder the varable frame onto the top gold-plated copper layer using gold-germanium solder.

[0013] Step 7: Sinter the electronic components onto the top gold-plated copper layer using gold-tin solder and perform gold wire bonding.

[0014] Step 8: Install the cover on the frame through parallel seam welding process to form an airtight space and complete the packaging.

[0015] Compared with the existing technology, the present invention has the following significant advantages: 1) Compared with HTCC and LTCC processes, the DPC substrate of the present invention has a 30% lower thermal resistance and a higher thermal conductivity than the HTCC substrate, which can meet the packaging requirements of high-power electronic components; 2) By increasing the maximum temperature tolerance of the DPC substrate from 320°C to 410°C, the chip assembly temperature can be increased to 300°C, providing a larger temperature gradient and preventing conflicts between different process steps; 3) Compared with traditional DPC packaging, the present invention can observe the soldering condition of the package bottom and evaluate whether the soldering quality is qualified through the three-dimensional pattern design of the bottom. At the same time, the three-dimensional pattern is used to adjust the port impedance matching, thereby improving the RF performance of the package. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of the electronic component packaging structure based on the DPC process described in the present invention.

[0017] Figure 2 The figure is a flow chart of the electronic component packaging preparation process based on the DPC process of the present invention.

[0018] Figure 3 Schematic diagram of thermal simulation results of electronic component packaging substrate based on DPC process of the present invention.

[0019] Figure 4 This is a temperature curve diagram for the frame assembly of the present invention.

[0020] Figure 5 Schematic diagram of the three-dimensional pattern of electronic component packaging based on the DPC process of the present invention.

[0021] Figure 6 The following is a comparison chart of the RF performance of electronic component packaging based on the DPC process, where a) is a return loss simulation comparison chart, and b) is a insertion loss simulation comparison chart.

[0022] Figure 7 Schematic diagram of electronic component packaging application based on DPC process.

[0023] 1. Cover; 2. Frame; 3. Electronic components; 4. Top gold-plated copper layer; 5. Alumina substrate; 6. Solid copper pillar; 7. Bottom gold-plated copper layer. DETAILED DESCRIPTION

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] The following will further introduce the specific implementation methods, as well as the technical difficulties and inventive points of this invention in combination with this design example.

[0026] Combine Figure 1 and Figure 2 The preparation method of the electronic component package based on the DPC process of the present invention comprises the following steps:

[0027] Step 1: Use laser to drill holes on the alumina substrate 5.

[0028] Step 2: Use magnetron sputtering to sputter a seed layer on the top and bottom surfaces of the alumina substrate 5 according to the designed pattern, and then use exposure and development processes to complete the patterning of the circuit.

[0029] Step 3: Electroplating copper on the alumina substrate 5 after the circuit patterning is completed to produce a top copper layer, a middle solid copper column 6 and a bottom copper layer.

[0030] Step 4: Electroplating nickel and gold on the surfaces of the two copper layers of the alumina substrate 5 respectively to complete the production of the top gold-plated copper layer 4 and the bottom gold-plated copper layer 7;

[0031] Step 5: cutting the alumina substrate 5 of step 4 to obtain a bottom substrate for electronic component packaging, i.e., a DPC substrate;

[0032] Step 6: Solder the Kovar frame 2 onto the top gold-plated copper layer 4 using gold-germanium (Au88Ge12) solder;

[0033] Step 7: Sinter the high-power electronic components onto the top gold-plated copper layer 4 using gold-tin (Au80Sn20) solder, and adhere the remaining electronic components onto the top gold-plated copper layer 4 using conductive adhesive, and perform gold wire bonding.

[0034] Step 8: Install the cover plate 1 on the frame 2 through a parallel seam welding process to form an airtight space and complete the packaging.

[0035] The present invention utilizes a DPC process to electroplate copper onto an alumina substrate 5, forming a solid copper column 6 inside the alumina substrate 5 and forming copper tens of microns thick on the top and bottom surfaces of the alumina, thereby effectively reducing the thermal resistance of the DPC substrate. Thermal simulation verification was performed on the substrate, and a gallium nitride power electronic component 3 with a heat dissipation power of 40 watts was placed on the alumina substrate 5 at a bottom temperature of 60°C. The junction temperature of the electronic component 3 was lower than the safe junction temperature of the gallium nitride device, and therefore it was considered to meet the packaging requirements for high-power electronic components. The thermal simulation results are shown in the figure below. Figure 3 shown.

[0036] The frame 2 is sintered to the top gold-plated copper layer 4 using gold-germanium (Au88Ge12) solder. The chip can be sintered inside the package at 300°C using gold-tin solder. The temperature curve diagram of the frame 2 assembly is shown in FIG. Figure 4 The process parameters are shown in Table 1:

[0037] Table 1 Reference parameters for the assembly process of frame 2

[0038]

[0039] The bottom copper layer is locally thickened by secondary electroplating to achieve three-dimensional patterning, which is optimized in terms of both process and RF performance. It can not only observe and evaluate the welding condition at the bottom of the DPC package, but also use the three-dimensional pattern to adjust the port matching, making the RF performance of the package even better. The schematic diagram of the three-dimensional pattern is shown in the figure. Figure 5 The microwave performance at 20GHz is improved by 8dB in return loss and 0.1dB in insertion loss. The RF performance comparison is shown in the figure below. Figure 6 In order to verify the thermal conductivity, RF performance and reliability of the package of the present invention, a power amplifier SIP with an output power of 16W at 6-18GHz was designed and implemented. The application diagram is shown in the figure. Figure 7 As shown in Figure 2, the measured results are consistent with the theoretical design values.

Claims

1. A method for preparing electronic component packaging based on DPC process, characterized in that: The preparation steps are as follows: Step 1: drilling holes on the alumina substrate (5) using a laser; Step 2: using magnetron sputtering to sputter a seed layer on the top and bottom surfaces of the alumina substrate (5) according to the design pattern, and then using exposure and development processes to complete the patterning of the circuit; Step 3: Electroplating copper on the alumina substrate (5) after the circuit patterning is completed to produce a top copper layer, a middle solid copper column (6) and a bottom copper layer; Step 4: Electroplating nickel and gold on the surfaces of the two copper layers of the alumina substrate (5) respectively to complete the production of the top gold-plated copper layer (4) and the bottom gold-plated copper layer (7); Step 5, cutting the alumina substrate (5) of step 4 to obtain a bottom substrate for electronic component packaging, hereinafter referred to as a DPC substrate; Step 6: Solder the varable frame (2) onto the top gold-plated copper layer (4) using gold-germanium solder; Step 7: Sintering the electronic components onto the top gold-plated copper layer (4) through gold-tin solder and performing gold wire bonding; Step 8: Install the cover plate (1) on the surrounding frame (2) through a parallel seam welding process to form an airtight space and complete the packaging.

2. The method for preparing electronic component packaging based on the DPC process according to claim 1, characterized in that: There are a plurality of solid copper pillars (6), the top surface and the bottom surface of which are respectively connected to the top gold-plated copper layer (4) and the bottom gold-plated copper layer (7).

3. The method for preparing electronic component packaging based on the DPC process according to claim 2, characterized in that: Taking into account the sintering temperature curve and the characteristics of the DPC substrate, the design rules were optimized, the minimum hole-edge spacing of the solid copper pillar (6) was expanded to 0.62 mm, and the maximum temperature tolerance of the DPC substrate was increased to 410°C.

4. The method for preparing electronic component packaging based on the DPC process according to claim 2, characterized in that: The surrounding frame (2) is sintered onto the top gold-plated copper layer (4) using gold-germanium solder.

5. The method for preparing electronic component packaging based on the DPC process according to claim 1, characterized in that: The electronic components are assembled on the top gold-plated copper layer (4) in the form of gold-tin solder sintering or conductive adhesive bonding; the connection between the electronic components and between the electronic components and the top gold-plated copper layer (4) is achieved through gold wires.

6. The method for preparing electronic component packaging based on the DPC process according to claim 1, characterized in that: A three-dimensional pattern is designed for the bottom gold-plated copper layer (7), and solder resist is laid on the area where soldering is not required.

7. The method for preparing electronic component packaging based on the DPC process according to claim 1, characterized in that: The cover plate (1) and the surrounding frame (2) are both made of cuttable materials and are connected by parallel seam welding.

8. The method for preparing electronic component packaging based on the DPC process according to claim 1, characterized in that: The thermal resistance of the DPC substrate is 30% lower than that of the HTCC substrate, meeting the packaging requirements of high-power microwave electronic components.

9. The method for preparing electronic component packaging based on the DPC process according to claim 1, characterized in that: The package is suitable for the frequency band of 0.1 MHz to 20 GHz and has excellent radio frequency performance.

Images