Circuit for configuring reference current for nonvolatile memory and nonvolatile memory
By designing a circuit that automatically configures the reference current in nonvolatile memory, the yield loss problem caused by process fluctuations is solved, and a stable mass production yield and reliable read current configuration are achieved, reducing production costs.
Patent Information
- Application Number
- CN202510530126.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-25
- Publication Date
- 2025-08-12
AI Technical Summary
When existing nonvolatile memory products fluctuate, the reference current fixation leads to yield loss, and existing solutions increase costs and are not flexible enough.
Design a circuit for nonvolatile memory, through current reference circuits, memory arrays, comparators and digital logic control circuits, automatically configure the reference current to adapt to process deviations, ensuring the accuracy and stability of the read current.
It achieves a stable mass production yield under different chip process deviations, avoids the time and labor investment of manually configuring the reading current parameters, and improves the reliability and production efficiency of non-volatile memory.
Smart Images
Figure CN120472970A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuits, and in particular to a circuit for configuring a reference current for a non-volatile memory and a non-volatile memory. Background Art
[0002] In current non-volatile memory products, the reference current for the read circuit is typically configured as a fixed parameter during wafer testing. However, process fluctuations can cause changes in the current characteristics of memory cells in both the erased and programmed states. This fixed reference current can lead to yield loss during wafer testing, either during the erased and programmed state verification test entries or during the programmed state test entries.
[0003] In this situation, the typical approach is to accept yield loss or to check the wafer WAT (Wafer Acceptance Test) data in advance. Based on the WAT data, the wafer test program is manually adjusted to configure the corresponding read current parameters for different batches. However, these methods will increase costs.
[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to ordinary technicians in this field. Summary of the Invention
[0005] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.
[0006] Embodiments of the present disclosure provide a circuit for configuring a reference current of a non-volatile memory and a non-volatile memory chip, so as to realize automatic configuration of the reference current and thus reduce cost loss.
[0007] In some embodiments, the circuit for configuring a reference current of a non-volatile memory includes:
[0008] A current reference circuit is used to generate a reference current, the value of the reference current is configurable; a storage array includes multiple storage cells; a comparator is connected to the current reference circuit and the storage array; and is used to compare the reference current and the cell current to output a comparison result; wherein the cell current is the current of the selected storage cell in the first typical area or the second typical area in the storage array; a digital logic control circuit is connected to the current reference circuit and the comparator, and is used to obtain the extreme current corresponding to the first typical area and the second typical area based on the comparison result of the comparator; and the value of the reference current is configured according to the extreme current.
[0009] In some embodiments, the non-volatile memory includes: the aforementioned circuit for configuring a reference current for the non-volatile memory.
[0010] The circuit for configuring a reference current for a non-volatile memory and the non-volatile memory provided in the embodiments of the present disclosure can achieve the following technical effects:
[0011] The circuit of the disclosed embodiment can obtain the extreme currents in the first and second typical regions; it then configures a reference current based on the extreme currents. This ensures the reliability of the configured reference current and adapts to process variations across different chips. This ensures stable yield rates in mass production of nonvolatile memory while avoiding the time and effort required to manually configure and read current parameters.
[0012] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] One or more embodiments are exemplarily described by corresponding drawings. These exemplary descriptions and drawings do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation. In addition,
[0014] Figure 1 This is a circuit diagram for configuring a reference current for a non-volatile memory provided by an embodiment of the present disclosure;
[0015] Figure 2 is another circuit diagram for configuring a reference current for a non-volatile memory provided by an embodiment of the present disclosure;
[0016] Figure 3 is another circuit diagram for configuring a reference current for a non-volatile memory provided by an embodiment of the present disclosure;
[0017] Figure 4 It is a schematic diagram of obtaining the reference current code corresponding to the maximum current value of data '0';
[0018] Figure 5 It is a schematic diagram of obtaining the reference current code corresponding to the minimum current value of data '1';
[0019] Figure 6 Schematic diagram of the current distribution of data '0' and '1' in the memory array.
[0020] Reference numerals:
[0021] 100: current reference circuit; 200: storage array; 300: comparator; 400: digital logic control circuit; 500: gating circuit; 600: internal configuration storage area;
[0022] 101: amplifier; 102: first PMOS transistor; 103: second PMOS transistor; 104: variable resistor; 201: storage unit; 601: first storage area; 602: first storage area; 603: first storage area. DETAILED DESCRIPTION
[0023] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The accompanying drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.
[0024] In the description and claims of the embodiments of the present disclosure, as well as in the accompanying drawings, the terms "first," "second," and the like are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate to describe the embodiments of the present disclosure herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.
[0025] In the embodiments of the present disclosure, the terms "upper", "lower", "inside", "middle", "outside", "front", "back" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated devices, elements or components to having a specific direction, or to be constructed and operated in a specific direction. Moreover, in addition to being used to indicate directions or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.
[0026] Furthermore, the terms "disposed," "connected," and "fixed" should be interpreted broadly. For example, "connected" can mean a fixed connection, a removable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediary, or an internal connection between two devices, elements, or components. Those skilled in the art will understand the specific meanings of these terms in the embodiments of this disclosure based on the specific circumstances.
[0027] Unless otherwise stated, the term "plurality" means two or more.
[0028] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B means: A or B.
[0029] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.
[0030] It should be noted that, unless there is any conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other.
[0031] Combine Figure 1 、 2 As shown, an embodiment of the present disclosure provides a circuit for configuring a reference current for a non-volatile memory, comprising a current reference circuit 100, a memory array 200, a comparator 300, and a digital logic control circuit 400. The current reference circuit 100 is used to generate a reference current IREF, the value of which is configurable. The memory array 200 comprises a first typical region and a second typical region, each of which comprises a plurality of memory cells. The comparator 300 is connected to the current reference circuit 100 and the memory array 200; and is used to compare the reference current IREF with the cell current ICELL to output a comparison result DOUT. The cell current ICELL is the current of the selected memory cell 201 in the first typical region or the second typical region in the memory array 200. The digital logic control circuit 400 is connected to the current reference circuit 100 and the comparator 300; and is used to obtain the extreme current corresponding to the first typical region and the second typical region based on the comparison result of the comparator 300; and configure the value of the reference current according to the extreme current.
[0032] Here, to adapt to the varying current characteristics of memory cells caused by process variations, the reference current is personalized for the memory chip. A circuit is provided that automatically configures the reference current, wherein the reference current is configurable. Specifically, the cell current of a selected memory cell and the current reference current are read. The cell current and reference current are compared, and based on the comparison results, the extreme currents corresponding to the first and second typical regions are obtained. The reference current is then configured based on the extreme currents.
[0033] It can be understood that the memory cell distinguishes between data "0" and "1" by storing charge; the first typical area and the second typical area are used to store data "0" and "1" respectively. During the wafer testing phase, in order to ensure the accuracy of the read data, it is necessary to configure a suitable reference current value to ensure the correct distinction between data "0" and "1". In detail, based on the distribution characteristics of data "0" and "1" (see Figure 6 ), by comparing the cell current with the reference current, the extreme currents corresponding to the first and second typical regions are obtained. Based on the extreme currents, a reference current is then configured to adapt to the current characteristics of the memory cells in the current chip. This ensures the reliability of the configured reference current and adapts to process variations across different chips. This ensures stable yield rates in mass production of non-volatile memory while avoiding the time and effort required to manually configure and read current parameters.
[0034] As an example, the first typical region is a typical region for data "0," and the second typical region is a typical region for data "1." By reading the cell current of the memory cell in the first typical region and comparing the result with reference currents of different values, the extreme current of the first typical region is obtained. Similarly, the extreme current of the second typical region is obtained. A current window is formed between the two extreme currents. When the reference current is configured to a current value within this window, the data "0" and "1" in the memory cell can be accurately distinguished.
[0035] The circuit for configuring a reference current for a non-volatile memory device, provided by an embodiment of the present disclosure, can obtain the extreme currents for the first and second typical regions; the reference current is then configured based on these extreme currents. This ensures that the configured reference current is correlated with the distribution of "0" and "1" data in the chip, ensuring its reliability and adapting to process variations across different chips. This ensures stable yield rates in mass production of non-volatile memory devices while avoiding the time and effort required to manually configure and read current parameters.
[0036] Optionally, the current reference circuit 100 includes an amplifier 101 , a current mirror circuit, and a variable resistor 104 .
[0037] Amplifier 101 has an input terminal connected to a reference voltage VREF. A current mirror circuit includes a first PMOS transistor 102 and a second PMOS transistor 103. The sources of the first and second PMOS transistors 102 and 103 are both connected to a power supply, and their gates are both connected to the output terminal of amplifier 101. The drain of the first PMOS transistor 102 is connected to the other input terminal of amplifier 101 and to a variable resistor 104. The drain of the second PMOS transistor 103 is connected to the input terminal of a comparator 300. The range value of the variable resistor is controlled by a digital logic control circuit.
[0038] Here, one input terminal of the amplifier is connected to a reference voltage, and the other input terminal and the output terminal are connected to a current mirror circuit. Thus, a reference current is generated using the reference voltage, and the setting of the amplifier helps to improve the stability and accuracy of the reference current. In addition, the setting of the variable resistor allows the reference current to be configured based on the current characteristics of the storage unit. Reference current IREF = VREF / R1; VREF is the reference voltage, and R1 is the resistance of the variable resistor. In addition, it should be noted that the digital logic control circuit controls the gear value of the variable resistor through a digital code (i.e., the reference current code), thereby adjusting the value of the reference current, that is, each reference current code corresponds to a reference current value, and also corresponds to a gear value of the variable resistor.
[0039] When obtaining the extreme current corresponding to the first typical region and the second typical region, the gear value of the variable resistor can be adjusted based on the comparison result of the comparator. This can thereby obtain the variable resistor gear corresponding to the extreme current, i.e., the reference current code. This can then determine the current value corresponding to the reference current code and configure an adaptive reference current.
[0040] Optionally, the first PMOS transistor 102 and the second PMOS transistor 103 have the same size.
[0041] Here, the two PMOS transistors have the same size, achieving a one-to-one replication of the current. That is, the current magnitudes of the branches in which the two PMOS transistors are located are the same. This facilitates control by the digital control logic circuit.
[0042] Optionally, the circuit for configuring the reference current of the non-volatile memory further includes a gating circuit 500, which is connected in series between the second PMOS transistor 103 and the memory array 200. The gating circuit 500 is used to select a memory cell to be read, wherein the size of the memory cell is 1 bit, that is, the memory cell can only store one "0" and one "1".
[0043] Optionally, the circuit for configuring the reference current of the non-volatile memory further includes: an internal configuration storage area 600 . The internal configuration storage area is connected to the digital control logic circuit; the internal configuration storage area includes a first storage area 601 and a second storage area 602 .
[0044] Among them, the first storage area is used to record the first reference current code IREF_CODE_0, which is determined based on the maximum unit current of the first typical area of the storage array read; the second storage area is used to record the second reference current code IREF_CODE_1, which is determined based on the minimum unit current of the second typical area of the storage array read.
[0045] Here, an internal configuration storage area is provided in the non-volatile memory for storing a reference current code. The reference current code corresponds to the variable resistor position value and also corresponds to the reference current value. The internal configuration storage area includes a first storage area and a second storage area. The first storage area is used to store a first reference current code, and the second storage area is used to store a second reference current code. The first reference current code is determined based on the maximum cell current read from the first typical region of the memory array; the second reference current code is determined based on the minimum cell current read from the second typical region of the memory array.
[0046] Based on the above analysis, it can be known that data "0" corresponds to a typical area in the storage array, and data "1" corresponds to another typical area in the storage array. According to the current distribution characteristics of data "0" and "1" in the storage array, a reference current is configured. The configured reference current needs to be between the two currents, so that the storage cell current of the storage array can be accurately read during the wafer testing phase. For the typical area of data "0", the reference current needs to be greater than the cell current of the typical area of data "0". For the typical area of data "1", the reference current needs to be less than the cell current of the typical area of data "1". Based on this requirement, the current upper limit value (i.e., the maximum cell current) is determined for the typical area of data "0", and the current lower limit value (i.e., the minimum cell current) is determined for the typical area of data "1". Among them, the code corresponding to the maximum cell current is the first reference current code, and the code corresponding to the minimum cell current is the second reference current code.
[0047] In the disclosed embodiment, the first typical area of the storage array refers to the typical area of data "0", and the second typical area refers to the typical area of data "1". The internal configuration storage area stores the first reference current code and the second reference current code. During the test phase or when the chip is working, the two codes can be called from the internal configuration storage area to automatically configure the reference current. In this way, the automatically configured reference current is between the upper and lower current limits of the typical area of data "0" and the typical area of data "1", thereby avoiding misjudgment of the reading unit current value due to temperature drift or process fluctuations.
[0048] In addition, the first reference current code and the second reference current code are determined by the digital control logic circuit based on the comparison result of the comparator.
[0049] Optionally, the digital logic control circuit determines the first reference current code IREF_CODE_0 including:
[0050] During the wafer testing phase, the digital logic control circuit configures the reference current code to a minimum value; and loops through the following steps until the comparator outputs a first value, whereby the reference current code corresponding to the comparator outputting the first value is used as a first reference current code:
[0051] The cell current of the first typical area of the memory array is read, and the cell current is compared with a reference current corresponding to a minimum value of the reference current code.
[0052] When the comparison result output by the comparator is not the first value, the reference current code is adjusted to increase the adjusted reference current.
[0053] Here, combined Figure 4 The process of determining the first reference current code by the digital logic control circuit is described in detail. During the wafer testing stage, the digital logic control circuit executes step S101 to configure the reference current code to the minimum value (the corresponding reference current is also the minimum value at this time). Then, step S102 is executed to read the cell current of the first typical area of the storage array. Step S103 determines whether the comparison result DOUT of the comparator is the first value; if so, step S105 is executed to use the current reference current code as the first reference current code. If not, step S104 is executed to increase the value of the reference current code so that the adjusted reference current increases. Then, step S102 is executed cyclically until the comparison result DOUT of the comparator is the first value.
[0054] In the embodiment of the present disclosure, the first value is "0", that is, when the reference current is greater than the cell current, the comparison result DOUT = "0"; when the reference current is less than the cell current, the comparison result DOUT = "1". In some embodiments, the first value can be "1". The value of the first value depends on the connection between the comparator and the storage array and the current reference circuit. In addition, it should be noted that step S102 of reading the cell current of the first typical area of the storage array refers to reading the cell current of each storage cell in the first typical area in sequence. When the comparison result corresponding to any cell current is not the first value, the value of the reference current code is adjusted. When the comparison results corresponding to all cell currents are the first value, the first reference current code is determined. In this way, it is ensured that the reference current corresponding to the first reference current code is greater than the maximum cell current of the first typical area.
[0055] Optionally, the digital logic control circuit determines the second reference current code IREF_CODE_1 including:
[0056] During the wafer test phase, the digital logic control circuit configures the reference current code to be a maximum value; the following steps are looped until the comparator outputs a second value, and the reference current code corresponding to the second value output by the comparator is used as the second reference current code:
[0057] The cell current of the second typical area of the memory array is read, and the cell current is compared with a reference current corresponding to a maximum value of the reference current code.
[0058] When the comparison result output by the comparator is not the second value, the reference current code is adjusted so that the adjusted reference current is reduced.
[0059] Here, the principle of determining the second reference current code by the digital logic control circuit is basically the same as the principle of determining the second reference current code described above. Figure 5 During the wafer testing phase, the digital logic control circuit executes step S201 to configure the reference current code to the maximum value (the corresponding reference current is also the maximum value at this time). Then, step S202 is executed to read the cell current of the second typical area of the storage array. Step S203 determines whether the comparison result DOUT of the comparator is the second value; if so, step S205 is executed to use the current reference current code as the second reference current code. If not, step S204 is executed to reduce the value of the reference current code so that the adjusted reference current is reduced. Step S202 is then executed repeatedly until the comparison result DOUT of the comparator is the second value. Here, the second value is 1.
[0060] Optionally, the internal configuration storage area 600 further includes a third storage area 603. The third storage area is used to record a third reference current code.
[0061] The third reference current code is greater than the first reference current code and less than the second reference current code.
[0062] Here, the internal configuration storage area also includes a third storage area for recording a third reference current code. The third reference current code is between the first reference current code and the second reference current code. In this way, for each chip, the variable resistance level value can be individually configured. When the chip is operating, the reference current configuration can be read from the third storage area to load the read reference current.
[0063] Optionally, the digital logic control circuit further comprises: configuring a third reference current code based on the first reference current code and the second reference current code; wherein,
[0064] IREF(IREF_CODE_R)=k0×IREF(IREF_CODE_0)+k1×IREF(IREF_CODE_1)
[0065] Where, 0 < k0 < 1, 0 < k1 < 1, IREF(IREF_CODE_0) is the reference current corresponding to the first reference current code IREF_CODE_0, IREF(IREF_CODE_1) is the reference current corresponding to the second reference current code IREF_CODE_1, and IREF(IREF_CODE_R) is the reference current corresponding to the third reference current code IREF_CODE_R.
[0066] Here, based on the cell current characteristics of the memory cell, the reference current is configured. Among them, the configured reference current is between the reference current corresponding to the first reference current code and the reference current corresponding to the second reference current code. More specifically, the reference current is configured by using the coefficients k0, k1 and the currents corresponding to the first reference current code and the second reference current code. Among them, the values of the coefficients k0 and k1 are both less than 1. In this way, the configured reference current can meet the personalized configuration of the chip, and the reference current can accurately distinguish data "0" and "1". Thereby ensuring the reliability of the read current, and thus ensuring the stability of the mass production yield of the Flash memory. At the same time, the configuration of the reference current can be automatically obtained through calculation, avoiding the time cost and manpower input of manually configuring the read current parameters.
[0067] Optionally, when the current reference circuit 100 and the memory array 200 are connected to the non-inverting input terminal of the comparator 300, the comparator 300 further includes an inverter to output an inverted comparison result.
[0068] Here, the read cell current and the reference current are compared to output a comparison voltage to the non-inverting input terminal of the comparator, and then the comparison voltage and the reference voltage (connected to the inverting input terminal of the comparator) are compared to output a comparison result. When the reference current is greater than the cell current, the comparison voltage is greater than the reference voltage. In this case, in order to make the comparator output result DOUT = '0', an inverter is provided at the output terminal of the comparator to invert the comparison result.
[0069] An embodiment of the present disclosure provides a non-volatile memory, including the circuit for configuring the reference current for the non-volatile memory as described above.
[0070] The above description and the drawings fully illustrate the embodiments of the present disclosure, so that those skilled in the art can practice them. Other embodiments may include structural and other changes. The embodiments only represent possible variations. Unless explicitly required, the individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replaced by parts and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.
Claims
1. A circuit for configuring a reference current for a non-volatile memory, characterized in that: include: A current reference circuit, configured to generate a reference current, wherein the value of the reference current is configurable; A memory array includes a first typical area and a second typical area, each typical area including a plurality of memory cells; a comparator connected to the current reference circuit and the storage array; used to compare the reference current and the cell current to output a comparison result; wherein the cell current is the current of the selected memory cell in the first typical area or the second typical area in the memory array; The digital logic control circuit is connected to the current reference circuit and the comparator, and is used to obtain the extreme current corresponding to the first typical area and the second typical area based on the comparison result of the comparator; and configure the value of the reference current according to the extreme current.
2. The circuit according to claim 1, wherein: The current reference circuit includes: an amplifier, one input terminal of which is connected to a reference voltage; A current mirror circuit includes a first PMOS transistor and a second PMOS transistor; the sources of the first PMOS transistor and the second PMOS transistor are both connected to a power supply, and the gates are both connected to the output end of the amplifier; the drain of the first PMOS transistor is connected to the other input end of the amplifier and to a variable resistor; the drain of the second PMOS transistor is connected to the comparator; Wherein, the gear value of the variable resistor is controlled by a digital logic control circuit.
3. The circuit according to claim 2, characterized in that The first PMOS transistor and the second PMOS transistor have the same size.
4. The circuit according to any one of claims 1 to 3, characterized in that Also includes: An internal configuration storage area connected to the digital control logic circuit; comprising a first storage area and a second storage area; Among them, the first storage area is used to record a first reference current code, which is determined by the digital logic control circuit based on the maximum unit current of the first typical area of the storage array read; the second storage area is used to record a second reference current code, which is determined by the digital logic control circuit based on the minimum unit current of the second typical area of the storage array read.
5. The circuit according to claim 4, characterized in that The digital logic control circuit determining the first reference current code includes: During the wafer testing phase, the digital logic control circuit configures the reference current code to be a minimum value; and loops through the following steps until the comparator outputs a first value, so that the reference current code corresponding to the comparator outputting the first value is used as the first reference current code: reading a cell current of a first typical area of a memory array, and comparing the cell current with a reference current corresponding to a minimum value of a reference current code; When the comparison result output by the comparator is not the first value, the value of the reference current code is adjusted to increase the adjusted reference current.
6. The circuit according to claim 4, characterized in that The digital logic control circuit determining the second reference current code includes: During the wafer testing phase, the digital logic control circuit configures the reference current code to be a maximum value; and loops through the following steps until the comparator outputs a second value, so that the reference current code corresponding to the second value output by the comparator is used as the second reference current code: reading a cell current of a second typical area of the memory array, and comparing the cell current with a reference current corresponding to a maximum value of the reference current code; When the comparison result output by the comparator is not the second value, the reference current code is adjusted so that the adjusted reference current is reduced.
7. The circuit according to claim 4, characterized in that The internal configuration storage area also includes: A third storage area for recording a third reference current code; wherein the third reference current code is greater than the first reference current code and less than the second reference current code.
8. The circuit according to claim 7, characterized in that The digital logic control circuit further includes: Configuring a third reference current code based on the first reference current code and the second reference current code; wherein, IREF(IREF_CODE_R) = k0 × IREF(IREF_CODE_0) + k1 × IREF(IREF_CODE_1) 0 < k0 < 1, 0 < k1 < 1, IREF(IREF_CODE_0) is the reference current corresponding to the first reference current code IREF_CODE_0, IREF(IREF_CODE_1) is the reference current corresponding to the second reference current code IREF_CODE_1, and IREF(IREF_CODE_R) is the reference current corresponding to the third reference current code IREF_CODE_R.
9. The circuit according to claim 1, wherein: When the current reference circuit and the storage array are connected to the non-inverting input terminal of the comparator, the comparator further includes an inverter to output an inverted comparison result.
10. A non-volatile memory, characterized in that: Including the circuit for configuring a reference current for a non-volatile memory according to any one of claims 1 to 9.