Bus common-mode voltage detection circuit of CAN bus transceiver

Abstract

The invention discloses a bus common-mode voltage detection circuit of a CAN bus transceiver, and relates to the technical field of integrated circuits, and the circuit comprises a sampling module, a comparison module and a logic module. The comparison module is respectively connected with the sampling module and the logic module, and the sampling module is connected with an output circuit of the CAN bus transceiver; the sampling module is used for collecting driving current of an output circuit of the CAN bus transceiver and sending the driving current to the comparison module; the comparison module is used for comparing the driving current with a preset reference current and outputting a comparison result to the logic module; the comparison result comprises signal states of the high-side current comparison signal and the reverse-side current comparison signal; and the logic module is used for determining that the bus common-mode voltage of the CAN bus transceiver is not in a preset normal range when the signal state of the high-side current comparison signal or the reverse-side current comparison signal in the comparison result is a high level, thereby facilitating fault diagnosis and maintenance.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a CAN bus transceiver bus common mode voltage detection circuit. Background Art

[0002] Although the CAN bus uses differential-mode voltage to identify and transmit signals, factors such as cable length and distribution parameters, and electromagnetic interference can affect the stability and range of the common-mode voltage. Excessively high or low bus common-mode voltages can degrade bus system performance, increasing bit error rates, reducing transmission distance, and addressing system anti-interference capabilities.

[0003] The existing CAN bus drive circuit structure is as follows Figure 1 As shown, the driver module converts the DH and DL voltages into output currents by controlling PMOS MA1 and NMOS MA4, respectively. To ensure that CANH and CANL achieve positive and negative voltage withstand characteristics, the drain of MA1 is connected to the positive terminal of high-voltage diode DA1, the negative terminal of DA1 is connected to the source of MA2, the gate of MA2 is grounded GND, and the drain of MA2 is the CANH output terminal of the CAN bus. The positive high voltage of CANH is cut off by DA1 for protection, and the negative voltage of CANH is isolated by MA2. The drain of NMOS MA4 is connected to the source of NMOS MA3, the gate of MA3 is connected to the power supply VCC, and the drain of MA3 is connected to the negative terminal of high-voltage diode DA2. The positive terminal of DA2 is the CANL output terminal of the CAN bus. The positive high voltage of CANL is protected by MA3, and the negative voltage of CANL is cut off by DA2 for protection.

[0004] CAN bus ports are bidirectional ports with both output and input functions. Figure 1 The diagram shows a CAN bus driver circuit. It uses DH and DL to control the dominant and recessive states of the two ports, CANH and CANL, effectively controlling the differential voltage. Detecting the bus differential voltage as an input to determine whether the bus is dominant or recessive is a basic function of the CAN bus chip. However, it does not detect abnormal common-mode voltages when the bus is dominant. Summary of the Invention

[0005] The main purpose of this application is to provide a CAN bus transceiver bus common mode voltage detection circuit, which aims to solve the technical problem that the CAN bus driving circuit fails to detect the common mode voltage abnormality when the bus is dominant.

[0006] To achieve the above-mentioned object, the present application proposes a CAN bus transceiver bus common mode voltage detection circuit, which is applied to a CAN bus transceiver; The CAN bus transceiver bus common mode voltage detection circuit includes: a sampling module, a comparison module and a logic module; The comparison module is connected to the sampling module and the logic module respectively, and the sampling module is connected to the output circuit of the CAN bus transceiver; The sampling module is used to collect the driving current of the output circuit of the CAN bus transceiver and send the driving current to the comparison module; The comparison module is used to compare the driving current with a preset reference current and output a comparison result to the logic module; the comparison result includes: a high-side current comparison signal, a signal state of a reverse-side current comparison signal, and a line-side current comparison signal; The logic module is used to determine the bus output dominant / recessive of the CAN bus transceiver according to the logical combination of the high-side current comparison signal, the reverse-side current comparison signal and the line-side current comparison signal in the comparison result; The logic module is further configured to convert the signal state of the reverse side current comparison signal in the comparison result from a low level to a high level when the bus output of the CAN bus transceiver is in a dominant state; The logic module is used to determine that the bus common mode voltage of the CAN bus transceiver is not within a preset normal range when the signal state of the high-side current comparison signal or the reverse-side current comparison signal in the comparison result is a high level, so that the COM terminal output of the logic module is a high level.

[0007] Optionally, the CAN bus transceiver bus common mode voltage detection circuit further includes: a reference current module; The reference current module is connected to the comparison module; The reference current module is used to send a reference current signal to the comparison module; The comparison module is used to compare the driving current with a preset reference current in the reference current signal, and output the comparison result to the logic module.

[0008] Optionally, the sampling module includes: a first sampling unit and a second sampling unit; The first sampling unit is connected to the comparison module and the output circuit of the CAN bus transceiver, and the second sampling unit is connected to the comparison module and the output circuit of the CAN bus transceiver; The first sampling unit is configured to collect a first driving current of an output circuit of the CAN bus transceiver and send the first driving current to the comparison module; The second sampling unit is used to collect a second driving current of the output circuit of the CAN bus transceiver and send the second driving current to the comparison module; The comparison module is further configured to compare the first driving current, the second driving current and a preset reference current, and output the comparison result to the logic module.

[0009] Optionally, the comparison module includes: a first comparison unit, a second comparison unit and a third comparison unit; The first comparison unit is connected to the sampling module, the second comparison unit, the third comparison unit and the logic module; the second comparison unit is connected to the sampling module, the first comparison unit, the third comparison unit and the logic module; the third comparison unit is connected to the sampling module, the first comparison unit, the second comparison unit and the logic module; The first comparison unit is configured to output a comparison result indicating that the high-side current comparison signal is at a high level to the logic module when the difference between the first drive current and the second drive current is greater than a preset reference current; The second comparison unit is configured to output a comparison result indicating that the reverse side current comparison signal is at a high level to the logic module when the difference between the second drive current and the first drive current is greater than a preset reference current; the comparison result further includes: a signal state of the line side current comparison signal; The third comparison unit is configured to output a comparison result indicating that the line-side current comparison signal is at a high level to the logic module when the sum of the first drive current and the second drive current is greater than a preset reference current.

[0010] Optionally, the logic module is further configured to determine that the bus common mode voltage of the CAN bus transceiver is within a preset normal range when the signal states of the high-side current comparison signal and the reverse-side current comparison signal in the comparison result are low levels; The logic module is further configured to determine that the bus output of the CAN bus transceiver is in a dominant state when the signal state of the received line-side current comparison signal is high; The logic module is further configured to determine that the bus output of the CAN bus transceiver is in a recessive state when the signal state of the received line-side current comparison signal is low.

[0011] Optionally, the first sampling unit includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor and a fifth MOS transistor; The gate of the first MOS transistor, the gate of the fourth MOS transistor, the drain of the fourth MOS transistor, and the drain of the fifth MOS transistor are respectively connected to the output circuit of the CAN bus transceiver, the drain of the first MOS transistor is connected to a power supply, the source of the fifth MOS transistor is grounded, the source of the first MOS transistor is connected to the source of the second MOS transistor, the gate of the second MOS transistor is respectively connected to the drain of the second MOS transistor and the gate of the third MOS transistor, the source of the third MOS transistor is connected to the source of the fourth MOS transistor, and the drain of the third MOS transistor is respectively connected to the gate of the fifth MOS transistor and the comparison module.

[0012] Optionally, the second sampling unit includes: a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor; The source of the sixth MOS transistor is connected to a power supply, the gate of the sixth MOS transistor is respectively connected to the drain of the eighth MOS transistor and the comparison module, the drain of the sixth MOS transistor, the source of the seventh MOS transistor, and the source of the eighth MOS transistor are respectively connected to the output circuit of the CAN bus transceiver, and the gate of the seventh MOS transistor is respectively connected to the drain of the seventh MOS transistor and the gate of the eighth MOS transistor.

[0013] Optionally, the first comparison unit includes: a ninth MOS transistor, a tenth MOS transistor, and an eleventh MOS transistor; The source of the ninth MOS transistor is grounded, the gate of the ninth MOS transistor is connected to the second comparing unit and the sampling module respectively, the drain of the ninth MOS transistor is connected to the drain of the tenth MOS transistor and the drain of the eleventh MOS transistor respectively, the gate of the tenth MOS transistor is connected to the third comparing unit, the source of the tenth MOS transistor and the source of the eleventh MOS transistor are connected to a power supply, and the gate of the eleventh MOS transistor is connected to the second comparing unit and the sampling module respectively.

[0014] Optionally, the second comparing unit includes: a twelfth MOS transistor, a thirteenth MOS transistor and a fourteenth MOS transistor; The source of the twelfth MOS transistor is connected to a power supply, the gate of the twelfth MOS transistor is connected to the first comparing unit and the sampling module respectively, the drain of the twelfth MOS transistor is connected to the drain of the thirteenth MOS transistor and the drain of the fourteenth MOS transistor respectively, the source of the thirteenth MOS transistor and the source of the fourteenth MOS transistor are grounded respectively, and the gate of the fourteenth MOS transistor is connected to the first comparing unit and the sampling module respectively.

[0015] Optionally, the third comparison unit includes: a fifteenth MOS transistor, a sixteenth MOS transistor, and a seventeenth MOS transistor; The source of the fifteenth MOS transistor is connected to a power supply, the gate of the fifteenth MOS transistor is connected to the first comparing unit and the sampling module respectively, the drain of the fifteenth MOS transistor is connected to the drain of the sixteenth MOS transistor and the drain of the seventeenth MOS transistor respectively, and the source of the sixteenth MOS transistor and the source of the seventeenth MOS transistor are grounded.

[0016] One or more technical solutions proposed in this application have at least the following effects: The present application discloses a CAN bus transceiver bus common mode voltage detection circuit, which is applied to a CAN bus transceiver; the CAN bus transceiver bus common mode voltage detection circuit includes: a sampling module, a comparison module and a logic module; the comparison module is connected to the sampling module and the logic module respectively, and the sampling module is connected to the output circuit of the CAN bus transceiver; the sampling module is used to collect the driving current of the CAN bus transceiver output circuit and send the driving current to the comparison module; the comparison module is used to compare the driving current with a preset reference current and output the comparison result to the logic module; the comparison result includes: the signal state of the high-side current comparison signal, the reverse-side current comparison signal and the line-side current comparison signal; the logic module An logic module is provided for determining whether the bus output of the CAN bus transceiver is dominant or recessive based on the logical combination of the high-side current comparison signal, the reverse-side current comparison signal and the line-side current comparison signal in the comparison result; the logic module is also provided for converting the signal state of the reverse-side current comparison signal in the comparison result from a low level to a high level when the bus output of the CAN bus transceiver is dominant; the logic module is provided for determining that the bus common-mode voltage of the CAN bus transceiver is not within a preset normal range when the signal state of the high-side current comparison signal or the reverse-side current comparison signal in the comparison result is high, so that the COM terminal output of the logic module is high, so that the bus common-mode voltage abnormality can be detected in time, which facilitates the diagnosis and maintenance of the fault, improves the reliability of the bus communication, and enhances the anti-interference capability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 Output circuit diagram for existing CAN bus transceiver; Figure 2 This is a schematic structural diagram of a first embodiment of a CAN bus transceiver bus common-mode voltage detection circuit proposed in an embodiment of the present application; Figure 3 This is a schematic structural diagram of a second embodiment of a CAN bus transceiver bus common-mode voltage detection circuit proposed in an embodiment of the present application; Figure 4 This is a circuit schematic diagram of the second embodiment of the CAN bus transceiver bus common mode voltage detection circuit proposed in the embodiments of the present application.

[0019] Description of Figure Numbers: 10: Sampling module; 20: Comparison module; 30: Logic module.

[0020] The purpose, features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0021] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not intended to limit the present application.

[0022] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0023] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0024] In addition, the descriptions of "first", "second", etc. in this application are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0025] The main solution of the embodiment of the present application is: the driving current of the CAN bus transceiver output circuit is collected by the sampling module 10 and sent to the comparison module 20, the comparison module 20 compares the driving current with the preset reference current, and outputs the comparison result to the logic module 30; the comparison result includes the signal state of the high-side current comparison signal and the reverse-side current comparison signal; the logic module 30 is used to determine that the bus common-mode voltage of the CAN bus transceiver is not within the preset normal range when the signal state of the high-side current comparison signal or the reverse-side current comparison signal in the comparison result is a high level.

[0026] The present application provides a solution, and discloses a CAN bus transceiver bus common mode voltage detection circuit, which is applied to a CAN bus transceiver; the CAN bus transceiver bus common mode voltage detection circuit includes: a sampling module 10, a comparison module 20 and a logic module 30; the comparison module 20 is connected to the sampling module 10 and the logic module 30 respectively, and the sampling module 10 is connected to the output circuit of the CAN bus transceiver; the sampling module 10 is used to collect the driving current of the CAN bus transceiver output circuit and send the driving current to the comparison module 20; the comparison module 20 is used to compare the driving current with a preset reference current and output the comparison result to the logic module 30; the comparison result includes: the signal state of the high side current comparison signal, the reverse side current comparison signal and Line-side current comparison signal; the logic module 30 is used to determine the dominant or recessive nature of the bus output of the CAN bus transceiver based on the logical combination of the high-side current comparison signal, the reverse-side current comparison signal and the line-side current comparison signal in the comparison result; the logic module 30 is also used to convert the signal state of the reverse-side current comparison signal in the comparison result from a low level to a high level when the bus output of the CAN bus transceiver is in a dominant state; the logic module 30 is used to determine that the bus common-mode voltage of the CAN bus transceiver is not within a preset normal range when the signal state of the high-side current comparison signal or the reverse-side current comparison signal in the comparison result is a high level, so that the COM terminal output of the logic module 30 is a high level, which can detect the abnormality of the bus common-mode voltage in time, facilitate fault diagnosis and maintenance, improve bus communication reliability, and enhance the system's anti-interference ability.

[0027] Based on this, an embodiment of the present application provides a CAN bus transceiver bus common mode voltage detection circuit.

[0028] refer to Figure 2 , Figure 2 This is a structural diagram of the first embodiment of the CAN bus transceiver bus common mode voltage detection circuit proposed in the embodiments of the present application.

[0029] Considering the problem that the CAN bus driver circuit does not detect the common mode voltage abnormality when the bus is dominant. Figure 2 As shown, the circuit described in this embodiment is applied to a CAN bus transceiver; The CAN bus transceiver bus common mode voltage detection circuit includes: a sampling module 10, a comparison module 20 and a logic module 30; The comparison module 20 is connected to the sampling module 10 and the logic module 30 respectively, and the sampling module 10 is connected to the output circuit of the CAN bus transceiver; The sampling module 10 is used to collect the driving current of the output circuit of the CAN bus transceiver and send the driving current to the comparison module 20; The comparison module 20 is used to compare the driving current with a preset reference current and output a comparison result to the logic module 30; the comparison result includes: a high-side current comparison signal, a signal state of a reverse-side current comparison signal, and a line-side current comparison signal; The logic module 30 is used to determine the bus output dominant / recessive of the CAN bus transceiver according to the logical combination of the high-side current comparison signal, the reverse-side current comparison signal and the line-side current comparison signal in the comparison result; The logic module 30 is further configured to convert the signal state of the reverse side current comparison signal in the comparison result from a low level to a high level when the bus output of the CAN bus transceiver is in a dominant state; The logic module 30 is used to determine that the bus common mode voltage of the CAN bus transceiver is not within a preset normal range when the signal state of the high-side current comparison signal or the reverse-side current comparison signal in the comparison result is a high level, so that the COM terminal output of the logic module 30 is a high level.

[0030] It should be noted that if Figure 2As shown, the sampling module 10 includes a CANH current sampling module (first sampling unit) and a CANL current sampling module (second sampling unit). The CANH current sampling module is connected to the drain of the CANH driver transistor MA1 via the HA port, and to the drain of the sampling transistor MA5 of the CANH driver transistor via the HB port. The CANH current sampling module processes the signals at points HA and HB. iH is the output of the CANH current sampling module. The CANL current sampling module is connected to the drain of the CANL driver transistor MA4 via the LA port, and to the drain of the sampling transistor MA6 of the CANL driver transistor via the LB port. The CANL current sampling module processes the signals at points LA and LB. iL is the output of the CANL current sampling module, meaning that in this embodiment, the drive currents are iH and iL. The reference current module generates a (preset) reference current iB. The comparison results are: iH - iL / iL - iH / iL + iH compared with iB. The signal states of the HSC high-side current comparison signal, the RSC reverse-side current comparison signal, and the LSC line-side current comparison signal are output to the logic module 30. The bus common-mode voltage of the CAN bus transceiver is not within the preset normal range, which means that the bus common-mode voltage is lower than the lower threshold or higher than the upper threshold. The preset normal range is the range between the upper threshold and the lower threshold.

[0031] In a specific implementation, the sampling module 10 is used to collect the driving current of the output circuit of the CAN bus transceiver and send the driving current to the comparison module 20; the comparison module 20 is used to compare the driving current with a preset reference current and output the comparison result to the logic module 30; the comparison result includes: the signal state of the high-side current comparison signal, the reverse-side current comparison signal and the line-side current comparison signal; the logic module 30 is used to determine the bus current of the CAN bus transceiver according to the logical combination of the high-side current comparison signal, the reverse-side current comparison signal and the line-side current comparison signal in the comparison result. Output dominant / recessive; the logic module 30 is also used to convert the signal state of the reverse side current comparison signal in the comparison result from a low level to a high level when the bus output of the CAN bus transceiver is in a dominant state; the logic module 30 is used to determine that the bus common mode voltage of the CAN bus transceiver is not within a preset normal range when the signal state of the high side current comparison signal or the reverse side current comparison signal in the comparison result is a high level, so that the COM terminal output of the logic module 30 is a high level, which can detect the abnormality of the bus common mode voltage in time, facilitate fault diagnosis and maintenance, improve bus communication reliability, and enhance the system's anti-interference ability.

[0032] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the first embodiment can be referred to the above introduction and will not be described in detail later. Figure 3 , Figure 3This is a structural diagram of the second embodiment of the CAN bus transceiver bus common mode voltage detection circuit proposed in the embodiments of the present application.

[0033] Considering providing a reference current for the comparison module 20. Figure 3 As shown, the CAN bus transceiver bus common mode voltage detection circuit of this embodiment further includes: a reference current module; The reference current module is connected to the comparison module 20; The reference current module is used to send a reference current signal to the comparison module 20; The comparison module 20 is configured to compare the driving current with a preset reference current in the reference current signal and output a comparison result to the logic module 30 .

[0034] It should be noted that the reference current module generates (presets) a reference current iB.

[0035] In a specific implementation, the reference current module is configured to send a reference current signal to the comparison module 20; the comparison module 20 is configured to compare the drive current with a preset reference current in the reference current signal and output the comparison result to the logic module 30. This ensures stable circuit operation and accurate judgment. The iB generated by the reference current module is a stable current value, providing a reliable reference standard for subsequent comparison operations. Even under different operating environments and conditions, as long as iB remains stable, the accuracy of the comparison result is guaranteed, ensuring that the entire circuit accurately judges the bus state, enabling the circuit to operate according to the intended logic and correctly detecting and controlling the bus common-mode voltage and output state. By comparing with iB, the sampled current signal (drive current) can be converted into high and low level signals to facilitate subsequent logic processing and control operations. This comparison method based on a fixed reference current can, to a certain extent, eliminate interference from other factors in the circuit, such as component parameter variations and power supply voltage fluctuations, thereby improving the consistency and accuracy of circuit judgments and ensuring stable operation of the entire system.

[0036] Furthermore, the sampling module 10 includes: a first sampling unit and a second sampling unit; The first sampling unit is connected to the comparison module 20 and the output circuit of the CAN bus transceiver, and the second sampling unit is connected to the comparison module 20 and the output circuit of the CAN bus transceiver; The first sampling unit is configured to collect a first driving current of an output circuit of the CAN bus transceiver and send the first driving current to the comparison module 20; The second sampling unit is used to collect the second driving current of the output circuit of the CAN bus transceiver and send the second driving current to the comparison module 20; The comparison module 20 is further configured to compare the first driving current, the second driving current and a preset reference current, and output the comparison result to the logic module 30 .

[0037] It should be noted that the first sampling unit is a CANH current sampling module, the second sampling unit is a CANL current sampling module, the first driving current is iH, and the second driving current is iL.

[0038] In a specific implementation, the first sampling unit is used to collect the first driving current of the output circuit of the CAN bus transceiver and send the first driving current to the comparison module 20; the second sampling unit is used to collect the second driving current of the output circuit of the CAN bus transceiver and send the second driving current to the comparison module 20; the comparison module 20 is also used to compare the first driving current, the second driving current and the preset reference current, and output the comparison result to the logic module 30, thereby realizing the sampling of the driving current of the output circuit of the CAN bus transceiver and comparing it with the preset reference current.

[0039] Furthermore, the comparison module 20 includes: a first comparison unit, a second comparison unit and a third comparison unit; The first comparison unit is connected to the sampling module 10, the second comparison unit, the third comparison unit and the logic module 30; the second comparison unit is connected to the sampling module 10, the first comparison unit, the third comparison unit and the logic module 30; the third comparison unit is connected to the sampling module 10, the first comparison unit, the second comparison unit and the logic module 30; The first comparison unit is configured to output a comparison result indicating that the high-side current comparison signal is at a high level to the logic module 30 when the difference between the first driving current and the second driving current is greater than a preset reference current; The second comparison unit is configured to output a comparison result indicating that the reverse side current comparison signal is at a high level to the logic module 30 when the difference between the second drive current and the first drive current is greater than a preset reference current; the comparison result further includes: a signal state of the line side current comparison signal; The third comparison unit is configured to output a comparison result indicating that the line-side current comparison signal is at a high level to the logic module 30 when the sum of the first driving current and the second driving current is greater than a preset reference current.

[0040] It should be noted that the first comparison unit is current comparison 1, which compares iH - iL and the reference current iB, and its output is HSC (high-side current comparison signal). When the bus common-mode voltage is lower than the lower threshold, the CANL current decreases, so iH - iL > iB and HSC is at a high level. The second comparison unit is current comparison 2, which compares iL - iH and the reference current iB, and its output is RSC (reverse-side current comparison signal). When the bus common-mode voltage is higher than the upper threshold, the CANH current decreases, so iL - iH > iB and RSC is at a high level. Under normal circumstances, when the bus common-mode voltage is between the upper and lower thresholds, the CANH and CANL currents are equal, so iH - iL < iB and iL - iH < iB, and both HSC and RSC are at a low level. The third comparison unit is current comparison 3, which compares iL - iH and the reference current iB, and its output is LSC (line-side current comparison signal). When the bus outputs a dominant signal, regardless of the range of the common-mode voltage, one of the bus CANH and CANL ports can normally output a driving current, so iL + iH > iB and LSC outputs a high level, indicating that the bus outputs a dominant signal; when the bus outputs a recessive signal, CANH and CANL are both turned off, iL and iH are zero, so iL + iH < iB and LSC outputs a low level.

[0041] In a specific implementation, the first comparison unit is configured to output a comparison result with the high-side current comparison signal at a high level to the logic module 30 when the difference between the first driving current and the second driving current is greater than a preset reference current; the second comparison unit is configured to output a comparison result with the reverse-side current comparison signal at a high level to the logic module 30 when the difference between the second driving current and the first driving current is greater than a preset reference current; the comparison result further includes: the signal state of the line-side current comparison signal; the third comparison unit is configured to output a comparison result with the line-side current comparison signal at a high level to the logic module 30 when the sum of the first driving current and the second driving current is greater than a preset reference current. Thus, the signal states of the HSC high-side current comparison signal, the RSC reverse-side current comparison signal, and the LSC line-side current comparison signal are determined by the comparison module 20.

[0042] Further, the logic module 30 is further configured to determine that the bus common-mode voltage of the CAN bus transceiver is within a preset normal range when the signal states of the high-side current comparison signal and the reverse-side current comparison signal in the comparison result are at a low level; The logic module 30 is further configured to determine that the bus output of the CAN bus transceiver is in a dominant state when receiving that the signal state of the line-side current comparison signal is at a high level; The logic module 30 is further configured to determine that the bus output of the CAN bus transceiver is in a recessive state when receiving that the signal state of the line-side current comparison signal is at a low level.

[0043] It should be noted that, as Figure 3 shown, the output terminals of the logic module 30 are COM and LD. The logic module 30 performs a logical combination on the input HSC (High-Side Current Comparison Signal), RSC (Reverse-Side Current Comparison Signal), and LSC (Line-Side Current Comparison Signal), and the output logic can reflect the range of the common-mode voltage and the output dominant / recessive nature: when the bus outputs dominantly, the current comparison 2 (the second comparison unit) outputs RSC as high; at this time, the logic module 30 outputs LD as high, indicating that the bus output is dominantly normal. When the common-mode voltage is lower than the preset low threshold, the current comparison 1 (the first comparison unit) outputs HSC as high; when the common-mode voltage is higher than the preset high threshold, the current comparison 2 (the second comparison unit) outputs RSC as high. As long as one of the RSC or HSC signals is high level, it means that the bus common-mode voltage is lower than the normal range or higher than the normal range, and COM is high. When the bus outputs recessively, CANH and CANL are both turned off, iL and iH are zero, so iL + iH < iB, and LSC outputs a low level.

[0044] In a specific implementation, the logic module 30 is further configured to determine that the bus common-mode voltage of the CAN bus transceiver is within the preset normal range when the signal states of the high-side current comparison signal and the reverse-side current comparison signal in the comparison result are low; the logic module 30 is further configured to determine that the bus output of the CAN bus transceiver is in a dominant state when receiving that the signal state of the line-side current comparison signal is high; the logic module 30 is further configured to determine that the bus output of the CAN bus transceiver is in a recessive state when receiving that the signal state of the line-side current comparison signal is low, so as to determine the bus output dominant / recessive state through the logical combination of HSC (High-Side Current Comparison Signal), RSC (Reverse-Side Current Comparison Signal), and LSC (Line-Side Current Comparison Signal).

[0045] Furthermore, please refer to Figure 4 , Figure 4 which is the circuit schematic diagram of the second embodiment of the bus common-mode voltage detection circuit of the CAN bus transceiver proposed in the embodiment of the present application. Considering collecting the drive current of the output circuit of the CAN bus transceiver through MOS transistors. As Figure 4 shown, the first sampling unit in this embodiment includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a fifth MOS transistor; The gate of the first MOS transistor, the gate of the fourth MOS transistor, the drain of the fourth MOS transistor, and the drain of the fifth MOS transistor are respectively connected to the output circuit of the CAN bus transceiver, the drain of the first MOS transistor is connected to a power supply, the source of the fifth MOS transistor is grounded, the source of the first MOS transistor is connected to the source of the second MOS transistor, the gate of the second MOS transistor is respectively connected to the drain of the second MOS transistor and the gate of the third MOS transistor, the source of the third MOS transistor is connected to the source of the fourth MOS transistor, and the drain of the third MOS transistor is respectively connected to the gate of the fifth MOS transistor and the comparison module 20.

[0046] It should be noted that the bus common mode voltage detection circuit includes a CANH current sampling circuit (first sampling unit), a reference current circuit (reference current module), a CANL current sampling circuit (second sampling unit), a current comparison module circuit (comparison module 20) and a logic circuit (logic module 30). Figure 4 As shown, bias current Ibias provides bias current for the branch containing the source and drain of MB25 through the current mirror formed by MB24 and MB25. The reference current flowing through branches MB1 and MB25 provides bias current for branches MB1, MB2, MB5, MB14, MB15, and MB42 through the current mirror. Simultaneously, the bias current of branch MB2 provides bias current for branches MB27, MB28, and MB29 through the current mirror of M26. Simultaneously, the bias current of branch MB28 provides bias current for the branch containing the source and drain of MB4 through the current mirror of MB3. The bias current of branch MB5 provides bias current for branches MB32, MB33, and MB34 through the current mirror of M31. The reference current flowing through branch MB15 provides bias current for the branch containing the source and drain of MB39 through the current mirror of MB38.

[0047] It can be understood that the first MOS transistor is MB20, the second MOS transistor is MB22, the third MOS transistor is MB23, the fourth MOS transistor is MB21, and the fifth MOS transistor is MB30.

[0048] In the specific implementation, MB20, MB22, MB23, MB21, and MB30 form a negative feedback structure (the first sampling unit) to ensure that the voltage at point HB tracks the voltage at point HA in real time, reducing the impact of channel length modulation on the CANH driver and sampling transistors. This ensures the accuracy of the CANH pin drive current sampled by the source and drain branches of MB30. The CANH pin drive current sampled by the source and drain branches of MB30 is passed through a current mirror formed by MB30, MB35, MB40, and MB41 to provide bias current for the source and drain branches of MB35, MB40, and MB41, respectively. The sampled CANH pin drive current flowing through the source and drain of MB35 and MB10 is passed through a current mirror formed by MB10 and MB11 to provide bias current for the source and drain branches of MB11. The sampling current of the CANH pin driving current flowing through the source and drain of MB11 and MB36 provides a bias current for the branch where the source and drain of MB37 are located through the current mirror composed of MB36 and MB37.

[0049] Furthermore, the second sampling unit includes: a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor; The source of the sixth MOS transistor is connected to a power supply, the gate of the sixth MOS transistor is respectively connected to the drain of the eighth MOS transistor and the comparison module 20, the drain of the sixth MOS transistor, the source of the seventh MOS transistor, and the source of the eighth MOS transistor are respectively connected to the output circuit of the CAN bus transceiver, and the gate of the seventh MOS transistor is respectively connected to the drain of the seventh MOS transistor and the gate of the eighth MOS transistor.

[0050] It can be understood that the sixth MOS transistor is MB9, the seventh MOS transistor is MB16, and the eighth MOS transistor is MB17.

[0051] In the specific implementation, MB9, MB16, and MB17 form a negative feedback structure (the second sampling unit) to sample the CANL drive current (second drive current). This ensures that the voltage at point LB tracks the voltage at point LA in real time, reducing the impact of channel length modulation on the CANL driver and sampling transistors. This ensures the accuracy of the CANL pin drive current sampled by the MB9 source and drain branches. The CANL pin drive current sampled by the MB9 source and drain branches is passed through the current mirrors formed by MB9, MB12, MB13, and MB43 to provide bias currents for the MB12 source and drain branches, the MB13 source and drain branches, and the MB43 source and drain branches, respectively. The CANL pin drive current sampled through the MB12 and MB18 source and drain branches is passed through the current mirror formed by MB18 and MB19 to provide bias currents for the MB19 source and drain branches.

[0052] Furthermore, the first comparison unit includes: a ninth MOS transistor, a tenth MOS transistor, and an eleventh MOS transistor; The source of the ninth MOS transistor is grounded, the gate of the ninth MOS transistor is connected to the second comparing unit and the sampling module 10 respectively, the drain of the ninth MOS transistor is connected to the drain of the tenth MOS transistor and the drain of the eleventh MOS transistor respectively, the gate of the tenth MOS transistor is connected to the third comparing unit, the source of the tenth MOS transistor and the source of the eleventh MOS transistor are connected to a power supply, and the gate of the eleventh MOS transistor is connected to the second comparing unit and the sampling module 10 respectively.

[0053] It can be understood that the ninth MOS transistor is MB41 , the tenth MOS transistor is MB42 , and the eleventh MOS transistor is MB43 .

[0054] In a specific implementation, MB41, MB42, and MB43 form current comparator 1 (the first comparator unit). The current flowing through the source and drain branches of the PMOS transistor MB42 serves as a reference current, denoted by IREF_1. The current flowing through the source and drain branches of the PMOS transistor MB43 serves as a sampled current of the CANL pin drive current, denoted by ICANL_1. The current flowing through the source and drain branches of the NMOS transistor MB41 serves as a sampled current of the CANH pin drive current, denoted by ICANH_1. When the bus common-mode voltage is low, the CANL pin current is low, and ICANH_1 - ICANL_1 > IREF_1, causing the LD pin output to be high.

[0055] Furthermore, the second comparison unit includes: a twelfth MOS transistor, a thirteenth MOS transistor and a fourteenth MOS transistor; The source of the twelfth MOS transistor is connected to a power supply, the gate of the twelfth MOS transistor is connected to the first comparing unit and the sampling module 10 respectively, the drain of the twelfth MOS transistor is connected to the drain of the thirteenth MOS transistor and the drain of the fourteenth MOS transistor respectively, the source of the thirteenth MOS transistor and the source of the fourteenth MOS transistor are grounded respectively, and the gate of the fourteenth MOS transistor is connected to the first comparing unit and the sampling module 10 respectively.

[0056] It can be understood that the twelfth MOS transistor is MB13, the thirteenth MOS transistor is MB39, and the fourteenth MOS transistor is MB40.

[0057] In a specific implementation, MB13, MB39, and MB40 form Current Comparison 2 (the second comparison unit). The current flowing through the source-drain branch of PMOS transistor MB13 is the sampled current of the CANL drive current, denoted as ICANL_2; the current flowing through the branch of NMOS transistor MB39 is the reference current, denoted as IREF_2; the current flowing through the source-drain branch of NMOS transistor MB40 is the sampled current of the CANH drive current, denoted as ICANH_2. When the bus common-mode voltage is too high, the CANH current is small, ICANL_2 - ICANH_2 > IREF_2, and the LD output is at a high level.

[0058] Further, the third comparison unit includes: a fifteenth MOS transistor, a sixteenth MOS transistor, and a seventeenth MOS transistor; The source of the fifteenth MOS transistor is connected to the power supply. The gate of the fifteenth MOS transistor is respectively connected to the first comparison unit and the sampling module 10. The drain of the fifteenth MOS transistor is respectively connected to the drains of the sixteenth MOS transistor and the seventeenth MOS transistor. The source of the sixteenth MOS transistor and the source of the seventeenth MOS transistor are grounded.

[0059] It can be understood that the fifteenth MOS transistor is MB14, the sixteenth MOS transistor is MB19, and the seventeenth MOS transistor is MB37.

[0060] In a specific implementation, MB14, MB19, and MB37 form Current Comparison 3 (the third comparison unit). The current flowing through the source-drain branch of PMOS transistor MB14 is the reference current, denoted as IREF_3; the current flowing through the source-drain branch of NMOS transistor MB19 is the sampled current of the CANL pin drive current, denoted as ICANL_3; the current flowing through the source-drain branch of NMOS transistor MB37 is the sampled current of the CANH pin drive current, denoted as ICANH_3. When the circuit operates in the recessive state, there is no current in the bus drive circuit, ICANH_3 + ICANL_3 < IREF_3, and the COM pin output is at a low level; when the circuit operates in the dominant state, there is current in the bus drive circuit, ICANH_3 + ICANL_3 > IREF_3, and the COM pin output is at a high level.

[0061] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be included in the patent protection scope of the present application by the same token.

Claims

1. A CAN bus transceiver bus common mode voltage detection circuit, characterized in that: The circuit is applied to a CAN bus transceiver; The CAN bus transceiver bus common mode voltage detection circuit includes: a sampling module, a comparison module and a logic module; The comparison module is connected to the sampling module and the logic module respectively, and the sampling module is connected to the output circuit of the CAN bus transceiver; The sampling module is used to collect the driving current of the output circuit of the CAN bus transceiver and send the driving current to the comparison module; The comparison module is used to compare the driving current with a preset reference current and output a comparison result to the logic module; the comparison result includes: a high-side current comparison signal, a signal state of a reverse-side current comparison signal, and a line-side current comparison signal; The logic module is used to determine the bus output dominant / recessive of the CAN bus transceiver according to the logical combination of the high-side current comparison signal, the reverse-side current comparison signal and the line-side current comparison signal in the comparison result; The logic module is further configured to convert the signal state of the reverse side current comparison signal in the comparison result from a low level to a high level when the bus output of the CAN bus transceiver is in a dominant state; The logic module is used to determine that the bus common mode voltage of the CAN bus transceiver is not within a preset normal range when the signal state of the high-side current comparison signal or the reverse-side current comparison signal in the comparison result is a high level, so that the COM terminal output of the logic module is a high level.

2. The CAN bus transceiver bus common mode voltage detection circuit according to claim 1, wherein: The CAN bus transceiver bus common mode voltage detection circuit further includes: a reference current module; The reference current module is connected to the comparison module; The reference current module is used to send a reference current signal to the comparison module; The comparison module is used to compare the driving current with a preset reference current in the reference current signal, and output the comparison result to the logic module.

3. The CAN bus transceiver bus common mode voltage detection circuit according to claim 1, wherein: The sampling module includes: a first sampling unit and a second sampling unit; The first sampling unit is connected to the comparison module and the output circuit of the CAN bus transceiver, and the second sampling unit is connected to the comparison module and the output circuit of the CAN bus transceiver; The first sampling unit is configured to collect a first driving current of an output circuit of the CAN bus transceiver and send the first driving current to the comparison module; The second sampling unit is used to collect a second driving current of the output circuit of the CAN bus transceiver and send the second driving current to the comparison module; The comparison module is further configured to compare the first driving current, the second driving current and a preset reference current, and output the comparison result to the logic module.

4. The CAN bus transceiver bus common mode voltage detection circuit according to claim 3, wherein: The comparison module includes: a first comparison unit, a second comparison unit and a third comparison unit; The first comparison unit is connected to the sampling module, the second comparison unit, the third comparison unit and the logic module; the second comparison unit is connected to the sampling module, the first comparison unit, the third comparison unit and the logic module; the third comparison unit is connected to the sampling module, the first comparison unit, the second comparison unit and the logic module; The first comparison unit is configured to output a comparison result indicating that the high-side current comparison signal is at a high level to the logic module when the difference between the first drive current and the second drive current is greater than a preset reference current; The second comparison unit is configured to output a comparison result indicating that the reverse side current comparison signal is at a high level to the logic module when the difference between the second drive current and the first drive current is greater than a preset reference current; the comparison result further includes: a signal state of the line side current comparison signal; The third comparison unit is configured to output a comparison result indicating that the line-side current comparison signal is at a high level to the logic module when the sum of the first drive current and the second drive current is greater than a preset reference current.

5. The CAN bus transceiver bus common mode voltage detection circuit according to claim 4, characterized in that: The logic module is further configured to determine that the bus common mode voltage of the CAN bus transceiver is within a preset normal range when the signal states of the high-side current comparison signal and the reverse-side current comparison signal in the comparison result are low levels; The logic module is further configured to determine that the bus output of the CAN bus transceiver is in a dominant state when the signal state of the received line-side current comparison signal is high; The logic module is further configured to determine that the bus output of the CAN bus transceiver is in a recessive state when the signal state of the received line-side current comparison signal is low.

6. The CAN bus transceiver bus common mode voltage detection circuit according to claim 3, wherein: The first sampling unit includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor and a fifth MOS transistor; The gate of the first MOS transistor, the gate of the fourth MOS transistor, the drain of the fourth MOS transistor, and the drain of the fifth MOS transistor are respectively connected to the output circuit of the CAN bus transceiver, the drain of the first MOS transistor is connected to a power supply, the source of the fifth MOS transistor is grounded, the source of the first MOS transistor is connected to the source of the second MOS transistor, the gate of the second MOS transistor is respectively connected to the drain of the second MOS transistor and the gate of the third MOS transistor, the source of the third MOS transistor is connected to the source of the fourth MOS transistor, and the drain of the third MOS transistor is respectively connected to the gate of the fifth MOS transistor and the comparison module.

7. The CAN bus transceiver bus common mode voltage detection circuit according to claim 3, wherein: The second sampling unit includes: a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor; The source of the sixth MOS transistor is connected to a power supply, the gate of the sixth MOS transistor is respectively connected to the drain of the eighth MOS transistor and the comparison module, the drain of the sixth MOS transistor, the source of the seventh MOS transistor, and the source of the eighth MOS transistor are respectively connected to the output circuit of the CAN bus transceiver, and the gate of the seventh MOS transistor is respectively connected to the drain of the seventh MOS transistor and the gate of the eighth MOS transistor.

8. The CAN bus transceiver bus common mode voltage detection circuit according to claim 4, wherein: The first comparison unit includes: a ninth MOS transistor, a tenth MOS transistor, and an eleventh MOS transistor; The source of the ninth MOS transistor is grounded, the gate of the ninth MOS transistor is connected to the second comparing unit and the sampling module respectively, the drain of the ninth MOS transistor is connected to the drain of the tenth MOS transistor and the drain of the eleventh MOS transistor respectively, the gate of the tenth MOS transistor is connected to the third comparing unit, the source of the tenth MOS transistor and the source of the eleventh MOS transistor are connected to a power supply, and the gate of the eleventh MOS transistor is connected to the second comparing unit and the sampling module respectively.

9. The CAN bus transceiver bus common mode voltage detection circuit according to claim 4, wherein: The second comparison unit includes: a twelfth MOS transistor, a thirteenth MOS transistor and a fourteenth MOS transistor; The source of the twelfth MOS transistor is connected to a power supply, the gate of the twelfth MOS transistor is connected to the first comparing unit and the sampling module respectively, the drain of the twelfth MOS transistor is connected to the drain of the thirteenth MOS transistor and the drain of the fourteenth MOS transistor respectively, the source of the thirteenth MOS transistor and the source of the fourteenth MOS transistor are grounded respectively, and the gate of the fourteenth MOS transistor is connected to the first comparing unit and the sampling module respectively.

10. The CAN bus transceiver bus common mode voltage detection circuit according to claim 4, wherein: The third comparison unit includes: a fifteenth MOS transistor, a sixteenth MOS transistor, and a seventeenth MOS transistor; The source of the fifteenth MOS transistor is connected to a power supply, the gate of the fifteenth MOS transistor is connected to the first comparing unit and the sampling module respectively, the drain of the fifteenth MOS transistor is connected to the drain of the sixteenth MOS transistor and the drain of the seventeenth MOS transistor respectively, and the source of the sixteenth MOS transistor and the source of the seventeenth MOS transistor are grounded.

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