Display panel, display device and preparation method of PIN diode

Abstract

The invention provides a display panel, a display device and a preparation method of a PIN diode, and relates to the technical field of semiconductors. Since the array layer of the display panel forms a plurality of film layers by adopting an ion implantation mode in the preparation process, the PIN diode is integrated in the array layer firstly, and then the P-type semiconductor layer is prepared by adopting the ion implantation mode used in the preparation process of the array layer in the preparation process of the array layer, so that the P-type semiconductor layer can be prepared in the preparation process of the array layer. The purposes of simplifying the preparation process flow and reducing the production cost are achieved. Furthermore, the ion implantation depth of the first doped ions is smaller than the thickness of the P-type semiconductor layer, and a diffusion space is provided for diffusion of the first doped ions in the region of the P-type semiconductor layer in which the first doped ions are not directly implanted, so that the depth of the first doped ions diffused to the intrinsic semiconductor layer is reduced to the greatest extent, and the diffusion efficiency of the intrinsic semiconductor layer is improved. And the photoelectric property of the PIN diode is ensured.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a display panel, a display device, and a PIN diode. Background Art

[0002] With the development of display technology, the application of display panels is becoming more and more extensive, and has gradually been applied to all aspects of people's work and life, such as mobile phones, televisions, tablets, and car displays.

[0003] Currently, PIN diodes are usually set up to enable display panels to achieve more functions, such as full-screen fingerprint recognition function, and adjusting the screen brightness according to the external ambient light.

[0004] However, in the current display panel equipped with PIN diodes, the N-type semiconductor layer, the intrinsic semiconductor layer and the P-type semiconductor layer are all prepared using a CVD (Chemical Vapor Deposition) process, and the P-type semiconductor layer and the N-type semiconductor layer are prepared using the CVD process in two different chambers, respectively. This results in a complicated preparation process and high cost. Summary of the Invention

[0005] In view of the above problems, this application provides a method for manufacturing a display panel, a display device, and a PIN diode, which simplifies the manufacturing process, reduces production costs, and ensures the optoelectronic performance of the PIN diode. The specific solution is as follows:

[0006] A first aspect of the present application provides a display panel, comprising:

[0007] substrate;

[0008] an array layer located on one side of the substrate;

[0009] A PIN diode integrated in the array layer; the PIN diode includes an N-type semiconductor layer, an intrinsic semiconductor layer, and a P-type semiconductor layer;

[0010] The P-type semiconductor layer includes doping ions implanted by ion implantation, the doping ions include first doping ions, and the ion implantation depth of the first doping ions is less than the thickness of the P-type semiconductor layer.

[0011] A second aspect of the present application provides a method for preparing a PIN diode, which is used to prepare the PIN diode described above. The method for preparing the PIN diode comprises:

[0012] forming an N-type semiconductor layer and an intrinsic semiconductor layer stacked in layers;

[0013] forming a film layer to be processed on a side of the intrinsic semiconductor layer away from the N-type semiconductor layer;

[0014] Doping ions are implanted into the film layer to be processed by ion implantation to form a P-type semiconductor layer; wherein the doping ions include first doping ions, and the ion implantation depth of the first doping ions is less than the thickness of the P-type semiconductor layer.

[0015] A third aspect of the present application provides a display device, which includes the display panel described above.

[0016] By means of the above-mentioned technical solution, the present application provides a method for manufacturing a display panel, a display device, and a PIN diode. Since the array layer of the display panel itself uses ion implantation to form some film layers during the manufacturing process, in the present application, the PIN diode is first integrated into the array layer. Secondly, in the process of preparing the array layer, the P-type semiconductor layer is prepared by the ion implantation method used in the array layer manufacturing process, thereby simplifying the manufacturing process and reducing production costs. Considering that the first dopant ions implanted into the P-type semiconductor layer by ion implantation will diffuse into the intrinsic semiconductor layer and affect the photoelectric performance of the PIN diode, in the present application, the ion implantation depth of the first dopant ions is made less than the thickness of the P-type semiconductor layer. The area of the P-type semiconductor layer where the first dopant ions are not directly implanted provides a diffusion space for the diffusion of the first dopant ions, thereby minimizing the depth of the first dopant ions diffusing into the intrinsic semiconductor layer and ensuring the photoelectric performance of the PIN diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the originals and elements are not necessarily drawn to scale.

[0018] Figure 1 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0019] Figure 2 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0020] Figure 3 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0021] Figure 4 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0022] Figure 5A schematic flow chart of a method for preparing a PIN diode provided in an embodiment of the present invention;

[0023] Figure 6 A schematic flow chart of another method for preparing a PIN diode provided in an embodiment of the present invention;

[0024] Figure 7 A schematic flow chart of another method for preparing a PIN diode provided in an embodiment of the present invention;

[0025] Figure 8 A schematic flow chart of another method for preparing a PIN diode provided in an embodiment of the present invention;

[0026] Figure 9 A schematic diagram of photocurrent corresponding to different ion implantation energies and the same first ion implantation dose provided by an embodiment of the present invention;

[0027] Figure 10 A schematic diagram of a projection range under a first ion implantation energy and a first ion implantation dose provided by an embodiment of the present invention;

[0028] Figure 11 A schematic diagram of a projection range under a second ion implantation energy and a first ion implantation dose provided by an embodiment of the present invention;

[0029] Figure 12 A schematic flow chart of another method for preparing a PIN diode provided in an embodiment of the present invention;

[0030] Figure 13 A schematic diagram of a first ion implantation energy and corresponding photocurrents under different doping ions provided by an embodiment of the present invention;

[0031] Figure 14 A schematic diagram of a second ion implantation energy and corresponding photocurrents under different doping ions provided by an embodiment of the present invention;

[0032] Figure 15 A schematic diagram of a first ion implantation energy, B doping, and a projection range when the dose of B doped ions is the first ion implantation dose provided by an embodiment of the present invention;

[0033] Figure 16 A schematic diagram of a first ion implantation energy, BF doping, and a projection range when the total BF doping dose is the first ion implantation dose provided by an embodiment of the present invention;

[0034] Figure 17 A schematic flow chart of another method for preparing a PIN diode provided in an embodiment of the present invention;

[0035] Figure 18A schematic diagram of the corresponding photocurrent under the same ion implantation energy and different ion implantation doses provided by an embodiment of the present invention;

[0036] Figure 19 A schematic diagram of a process for forming an intrinsic semiconductor layer provided by an embodiment of the present invention;

[0037] Figure 20 A schematic flow chart of another method for preparing a PIN diode provided in an embodiment of the present invention;

[0038] Figure 21 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation methods of the present application are only used to explain the specific embodiments of the present application and are not intended to limit the present application. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0040] It should be noted that the directional words appearing in the present invention are based on the relative position relationship shown in the drawings and cannot be used as an absolute limitation to the present application.

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0042] refer to Figure 1 , Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention; Figure 2 , Figure 2 A schematic structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. 1 . The display panel 100 provided by an embodiment of the present invention includes: a substrate 12 .

[0043] The array layer 13 is located on one side of the substrate 12 .

[0044] The PIN diode 14 is integrated in the array layer 13 ; the PIN diode 14 includes an N-type semiconductor layer 141 , an intrinsic semiconductor layer 142 , and a P-type semiconductor layer 143 .

[0045] The P-type semiconductor layer 143 includes dopant ions implanted by ion implantation. The dopant ions include first dopant ions. The implantation depth of the first dopant ions is less than the thickness of the P-type semiconductor layer 143 .

[0046] Specifically, in the embodiment of the present invention, Figure 1 As shown, the display panel includes first signal lines L1 extending along the row direction and second signal lines L2 extending along the column direction. The first signal lines L1 and the second signal lines L2 intersect, and the intersections define a plurality of sub-pixels 11 arranged in an array. The first signal lines L1 extending along the row direction may include Scan signal lines, Vref signal lines, and DVH signal lines, etc. The second signal lines L2 extending along the column direction may include Data signal lines and PVDD signal lines, etc.

[0047] The substrate 12 is a flexible insulating material substrate having properties such as stretchability, bendability or curvature, and its material includes but is not limited to polyimide material (PI for short), polycarbonate material (PC for short), or polyethylene terephthalate material (PET for short).

[0048] like Figure 2 As shown, the array layer 13 includes, but is not limited to, a first insulating layer 15, a second insulating layer 16, a third insulating layer 17, a fourth insulating layer 18, a passivation layer 19, a planarization layer 20, and a pixel definition layer 21. The pixel definition layer 21 has a plurality of sub-pixel opening regions PP and a light-transmitting region TT. An anode layer 22, a light-emitting layer 23, and a cathode layer 24 are disposed within the pixel opening regions PP, thereby forming the light-emitting elements required for the sub-pixels 11.

[0049] like Figure 2 As shown, the display panel 100 also includes a transistor 25, which forms other functional circuits such as pixel circuits. The transistor 25 includes an active layer 251, a gate 252, a source 253, and a drain 254. The active layer 251 is located on the side of the second insulating layer 16 facing away from the substrate 12, and the gate 252 is located on the side of the third insulating layer 17 facing away from the substrate 12. The source 253 and the drain 254 are located in the same layer and on the side of the fourth insulating layer 18 facing away from the substrate 12. The passivation layer 19 is provided on the side of the source 253 and the drain 254 facing away from the substrate 12, the planarization layer 20 is provided on the side of the passivation layer 19 facing away from the substrate 12, and the pixel definition layer 21 is provided on the side of the planarization layer 20 facing away from the substrate 12.

[0050] A light-transmitting area TT is defined between at least some of the adjacent two sub-pixels 11 , and an orthographic projection of the light-transmitting area TT at least completely covers the intrinsic semiconductor layer 142 to ensure that light can irradiate the intrinsic semiconductor layer 142 .

[0051] The PIN diode 14 provided in the embodiments of the present invention includes, but is not limited to, a photo PIN diode. This embodiment of the present invention uses a photo PIN diode as an example for illustration. Conventional diodes directly form a PN junction by combining an N-type doped semiconductor layer and a P-type doped semiconductor layer. However, the PIN diode 14 provided in the embodiments of the present invention incorporates a low-doped intrinsic semiconductor layer 142 between a P-type semiconductor layer 143 and an N-type semiconductor layer 141.

[0052] refer to Figure 3 , Figure 3 The PIN diode 14 provided in the embodiment of the present invention further includes: a first electrode 144 connected to the N-type semiconductor layer 141 , and a second electrode 145 connected to the P-type semiconductor layer 143 .

[0053] refer to Figure 4 , Figure 4 Schematic diagram of another display panel structure provided by an embodiment of the present invention. In the embodiment of the present invention, the anode layer 22 is connected to the P-type semiconductor layer 143 and / or the N-type semiconductor layer 141. Figure 4 As shown, the N-type semiconductor layer 141 is electrically connected to the anode layer 22 through the first electrode 144 , and the P-type semiconductor layer 143 is electrically connected to the anode layer 22 through the second electrode 145 .

[0054] Since the anode layer 22 is composed of independent anode units, some anode units that are not required to constitute the sub-pixels 11 are formed during the preparation of the anode layer 22 to achieve electrical connection with the PIN diode 14, thereby simplifying the circuit connection.

[0055] A photo PIN diode operates under reverse bias and generates a photocurrent when illuminated. The magnitude of the photocurrent is proportional to the light intensity. Specifically, when a reverse bias is applied to the PN junction, the direction of the applied electric field aligns with the PN junction's built-in electric field, strengthening the potential barrier and essentially depleting carriers near the PN junction interface, forming a depletion region. When a light beam impinges on the PN junction, and the photon energy exceeds the semiconductor material's bandgap, electrons in the valence band absorb the photon energy and transition to the conduction band, forming an electron-hole pair. In the depletion region, electrons drift toward the N region and holes toward the P region under the influence of the built-in electric field. If a circuit external to the PN junction forms a loop, a photocurrent is generated. As the incident light power changes, the photocurrent also changes linearly, thereby converting the optical signal into an electrical signal.

[0056] Based on this, in the embodiment of the present invention, since the array layer 13 of the display panel 100 itself uses ion implantation to form some film layers during the preparation process, that is, there is a mature ion implantation process on the preparation production line of the array layer 13, the PIN diode 14 is first integrated into the array layer 13 in the present application, and secondly, in the process of preparing the array layer 13, the P-type semiconductor layer 143 is prepared by the ion implantation method used in the preparation process of the array layer 13. Compared with the existing technology, the purpose of simplifying the preparation process and reducing production costs is achieved.

[0057] The photocurrent of the PIN diode 14 depends on the concentration and migration speed of minority carriers in the PIN diode 14. Ion implantation can lead to the diffusion of the first dopant ions into the intrinsic semiconductor layer 142, which can increase the space charge region of the PN junction, narrow the depletion layer, reduce the number of minority carriers generated, and lower the photocurrent. Specifically, in the present embodiment, the first dopant ions implanted into the P-type semiconductor layer 143 by ion implantation can diffuse into the intrinsic semiconductor layer 142, affecting the photoelectric performance of the PIN diode 14. Therefore, in the present embodiment, the ion implantation depth of the first dopant ions is set to be less than the thickness of the P-type semiconductor layer 143. The regions of the P-type semiconductor layer 143 not directly implanted with the first dopant ions provide a diffusion space for the first dopant ions to diffuse, thereby minimizing the depth of the first dopant ions diffusing into the intrinsic semiconductor layer 142. This results in a smaller space charge region of the PN junction, a relatively wider depletion layer, an increased number of minority carriers generated, and an increased photocurrent, thereby ensuring the photoelectric performance of the PIN diode 14.

[0058] In an optional embodiment of the present invention, the P-type semiconductor layer 143 is prepared by ion implantation based on an IMP (Ion Implantation) process.

[0059] In an optional embodiment of the present invention, the doping ions further include second doping ions; the ion mass of the second doping ions is greater than the ion mass of the first doping ions.

[0060] Specifically, in the embodiment of the present invention, the first doping ion is B ion, that is, the P-type semiconductor layer 143 is formed by the injection of B ions. The second doping ion includes but is not limited to at least one of F ions and Ar ions. Under the same ion injection energy, the ion with a large mass moves at a slower speed, and the ion with a small mass moves at a faster speed. In order to prevent the first doping ion from moving faster and making its ion injection depth deeper, the second doping ion is injected at the same time as the first doping ion. The second doping ion is used to slow down or buffer the diffusion of the first doping ion to a deeper area, thereby minimizing the depth of the first doping ion diffusion to the intrinsic semiconductor layer 142 and ensuring the photoelectric performance of the PIN diode 14.

[0061] From another perspective, by introducing a second doping ion, such as Ar ions and / or F ions, the proportion of B ions will be reduced, so that under the same ion injection energy, the injection depth and dose will become smaller, thereby achieving the purpose of reducing the diffusion depth of B ions.

[0062] In an optional embodiment of the present invention, a film forming speed of the P-type semiconductor layer 143 is less than 25% of a film forming speed of the intrinsic semiconductor layer 142 .

[0063] Specifically, in the embodiment of the present invention, the film formation speed of the P-type semiconductor layer 143 is less than 25% of the film formation speed of the intrinsic semiconductor layer 142, indicating that the formed P-type semiconductor layer 143 will be denser than the intrinsic semiconductor layer 142, thereby slowing down the diffusion speed of the first doped ions in the P-type semiconductor layer 143, and the interface between the two will further slow down the diffusion speed of the first doped ions, thereby minimizing the depth of the first doped ions diffusing into the intrinsic semiconductor layer 142, thereby ensuring the photoelectric performance of the PIN diode 14.

[0064] Among them, when the film forming speed of the P-type semiconductor layer 143 is less than the film forming speed of the intrinsic semiconductor layer 142 by more than 25%, exemplarily the film forming speed of the P-type semiconductor layer 143 is less than 40% of the film forming speed of the intrinsic semiconductor layer 142, the density of the P-type semiconductor layer 143 will be higher. Although the diffusion speed of the first doped ions in the P-type semiconductor layer 143 can be further slowed down, there may be a situation where the first doped ions cannot be completely diffused throughout the entire P-type semiconductor layer 143, that is, the effective area of the P-type semiconductor layer 143, that is, the area of the P-type semiconductor layer 143 doped with the first doped ions, will have an area not doped with the first doped ions between the effective area of the P-type semiconductor layer 143, that is, the area of the P-type semiconductor layer 143 doped with the first doped ions, and the intrinsic semiconductor layer 142, which will affect the photoelectric performance of the PIN diode 14.

[0065] When the film forming speed of the P-type semiconductor layer 143 is less than 25% of the film forming speed of the intrinsic semiconductor layer 142, exemplarily, the film forming speed of the P-type semiconductor layer 143 is less than 15% of the film forming speed of the intrinsic semiconductor layer 142, and the film density difference between the P-type semiconductor layer 143 and the intrinsic semiconductor layer 142 is not very large, which cannot serve the purpose of slowing down the diffusion speed of the first doped ions, and thus cannot reduce the depth of the first doped ions diffused into the intrinsic semiconductor layer 142, which will affect the photoelectric performance of the PIN diode 14.

[0066] Therefore, in the embodiment of the present invention, the film forming speed of the P-type semiconductor layer 143 is set to be less than 25% of the film forming speed of the intrinsic semiconductor layer 142, so as to minimize the depth of the first dopant ion diffusion into the intrinsic semiconductor layer 142 and ensure the photoelectric performance of the PIN diode 14.

[0067] In an optional embodiment of the present invention, the ion implantation depth of the first dopant ion is H, and the thickness of the P-type semiconductor layer 143 is G.

[0068] Where H = G / 2.

[0069] Specifically, in an embodiment of the present invention, when preparing the P-type semiconductor layer 143, the first doped ions are injected into the position of half of the film thickness of the P-type semiconductor layer 143. The remaining half thickness of the P-type semiconductor layer 143 provides a diffusion space for the diffusion of the first doped ions. Under the condition of H=G / 2, it can be ensured that the first doped ions diffuse into the entire P-type semiconductor layer 143. In this case, no or only very few first doped ions diffuse into the intrinsic semiconductor layer 142, thereby minimizing the depth of the first doped ions diffusing into the intrinsic semiconductor layer 142 and ensuring the photoelectric performance of the PIN diode 14.

[0070] Among them, when H<G / 2, although it can be guaranteed that no first doped ions diffuse into the intrinsic semiconductor layer 142, there may be a situation where the first doped ions cannot completely diffuse into the entire P-type semiconductor layer 143, that is, the effective area of the P-type semiconductor layer 143, that is, the area of the P-type semiconductor layer 143 doped with the first doped ions, and there will be an area not doped with the first doped ions between the effective area of the P-type semiconductor layer 143 and the intrinsic semiconductor layer 142, which will affect the photoelectric performance of the PIN diode 14.

[0071] When H>G / 2, although the first doped ions can be guaranteed to diffuse into the entire P-type semiconductor layer 143, more first doped ions may diffuse into the intrinsic semiconductor layer 142, and thus the depth of the first doped ions diffused into the intrinsic semiconductor layer 142 cannot be reduced, which will affect the photoelectric performance of the PIN diode 14.

[0072] Therefore, in the embodiment of the present invention, H=G / 2 is set. While ensuring that the first doped ions diffuse into the entire P-type semiconductor layer 143, no or very few first doped ions diffuse into the intrinsic semiconductor layer 142, thereby minimizing the depth of the first doped ions diffusing into the intrinsic semiconductor layer 142 and ensuring the photoelectric performance of the PIN diode 14.

[0073] In an optional embodiment of the present invention, the thickness range of the P-type semiconductor layer 143 is 300 angstroms to 500 angstroms, for example, the thickness of the P-type semiconductor layer 143 is 300 angstroms, 350 angstroms, 400 angstroms or 500 angstroms; the thickness range of the intrinsic semiconductor layer 142 is 5000 angstroms to 8000 angstroms, for example, the thickness of the intrinsic semiconductor layer 142 is 5000 angstroms, 6650 angstroms or 8000 angstroms; the thickness range of the N-type semiconductor layer 141 is 1500 angstroms to 2500 angstroms, for example, the thickness of the N-type semiconductor layer 141 is 1500 angstroms, 1750 angstroms or 2000 angstroms.

[0074] Based on the above embodiment of the present invention, another embodiment of the present invention further provides a method for preparing a PIN diode, referring to Figure 5 , Figure 5 A schematic flow chart of a method for preparing a PIN diode provided in an embodiment of the present invention. The method for preparing a PIN diode provided in an embodiment of the present invention is used to prepare the PIN diode 14 mentioned in any of the above embodiments. The method for preparing a PIN diode provided in an embodiment of the present invention includes:

[0075] S101 : forming an N-type semiconductor layer 141 and an intrinsic semiconductor layer 142 that are stacked.

[0076] S102 : forming a film layer to be processed on a side of the intrinsic semiconductor layer 142 away from the N-type semiconductor layer 141 .

[0077] S103 : Implanting dopant ions into the film layer to be processed by ion implantation to form a P-type semiconductor layer 143 ; wherein the dopant ions include first dopant ions, and the ion implantation depth of the first dopant ions is less than the thickness of the P-type semiconductor layer 143 .

[0078] Specifically, in the embodiment of the present invention, the P-type semiconductor layer 143 is formed by ion implanting the first dopant ions into the film layer to be treated. The photocurrent of the PIN diode 14 depends on the concentration and migration speed of the minority carriers in the PIN diode 14. Ion implantation can lead to the diffusion of the first dopant ions into the intrinsic semiconductor layer 142, which can increase the space charge region of the PN junction, narrow the depletion layer, reduce the number of minority carriers generated, and reduce the photocurrent. Specifically, in the embodiment of the present application, considering that the first dopant ions implanted into the P-type semiconductor layer 143 by ion implantation can diffuse into the intrinsic semiconductor layer 142 and affect the photoelectric performance of the PIN diode 14, the ion implantation depth of the first dopant ions is set to be less than the thickness of the P-type semiconductor layer 143. The areas of the P-type semiconductor layer 143 not directly implanted with the first dopant ions provide diffusion space for the first dopant ions to diffuse, thereby minimizing the depth of the first dopant ions diffusing into the intrinsic semiconductor layer 142. This reduces the space charge region of the PN junction, widens the depletion layer, increases the number of minority carriers generated, and increases the photocurrent, thereby ensuring the photoelectric performance of the PIN diode 14.

[0079] In an optional embodiment of the present invention, reference Figure 6 , Figure 6 A schematic flow chart of another method for preparing a PIN diode provided by an embodiment of the present invention. One possible implementation of step S101 of "forming a stacked N-type semiconductor layer 141 and an intrinsic semiconductor layer 142" is as follows:

[0080] S1011 : sequentially forming the N-type semiconductor layer 141 and the intrinsic semiconductor layer 142 by using a CVD process.

[0081] One possible implementation of step S102 of “forming a film layer to be processed on a side of the intrinsic semiconductor layer 142 facing away from the N-type semiconductor layer 141 ” is:

[0082] S1021 : forming a film layer to be processed on a side of the intrinsic semiconductor layer 142 away from the N-type semiconductor layer 141 by using a CVD process.

[0083] Specifically, in the embodiment of the present invention, the N-type semiconductor layer 141, the intrinsic semiconductor layer 142, and the film layer to be processed are all prepared using a CVD process. The CVD process is usually carried out in a high-temperature environment. The high temperature facilitates atomic diffusion, thereby forming a high-quality crystalline structure. The film layer generated by the CVD process reaction has the characteristics of high purity, good density, low residual stress, and good crystallization. These characteristics are of great significance for improving the electrical performance and reliability of semiconductor devices. Therefore, in the embodiment of the present application, the N-type semiconductor layer 141, the intrinsic semiconductor layer 142, and the film layer to be processed are prepared using a CVD process to improve the film quality of the N-type semiconductor layer 141, the intrinsic semiconductor layer 142, and the film layer to be processed, thereby improving the photoelectric performance of the prepared PIN diode 14.

[0084] In addition, the equipment used in the CVD process is relatively simple and easy to operate and maintain, which helps to reduce production costs and improve production efficiency.

[0085] In an optional embodiment of the present invention, reference Figure 7 , Figure 7 A schematic flow chart of another method for preparing a PIN diode provided in an embodiment of the present invention. One possible implementation of step S103 of "implanting dopant ions into the film layer to be processed to form a P-type semiconductor layer 143 by ion implantation" is as follows:

[0086] S1031 : Using an IMP process to implant the doping ions into the film layer to be processed by ion implantation to form the P-type semiconductor layer 143 .

[0087] Specifically, in the embodiment of the present invention, the P-type semiconductor layer 143 is formed by ion implanting the dopant ions into the film layer to be processed using an IMP process. The IMP process precisely controls the electrical properties of the material by implanting a high-energy ion beam into the semiconductor material. The number, depth, and distribution of implanted ions can be precisely controlled. Therefore, in the embodiment of the application, the IMP process can be precisely controlled so that the ion implantation depth of the first dopant ions is less than the thickness of the P-type semiconductor layer 143. The area of the P-type semiconductor layer 143 where the first dopant ions are not directly implanted provides a diffusion space for the diffusion of the first dopant ions, thereby minimizing the depth of the first dopant ions diffusing into the intrinsic semiconductor layer 142. This reduces the space charge region of the PN junction, widens the depletion layer, increases the number of minority carriers generated, and increases the photocurrent, thereby ensuring the photoelectric performance of the PIN diode 14.

[0088] Moreover, compared with other doping processes, the IMP process is a relatively low-temperature process, which helps to reduce thermal damage to the material. The doping ions injected by the IMP process are not limited by the solubility of the target material, have high purity, and can achieve uniform doping distribution over a large area, thereby ensuring the film quality of the prepared P-type semiconductor layer 143 and ultimately improving the photoelectric performance of the prepared PIN diode 14.

[0089] In an optional embodiment of the present invention, reference Figure 8 , Figure 8 A schematic flow chart of another method for preparing a PIN diode according to an embodiment of the present invention. The process parameters of the IMP process include the ion implantation energy. One possible implementation of step S1031, "using the IMP process to implant the dopant ions into the film to be processed to form the P-type semiconductor layer 143," is as follows:

[0090] S1031A: reducing the ion implantation energy and implanting the doping ions into the film layer to be processed by ion implantation to form the P-type semiconductor layer 143 .

[0091] Specifically, in the embodiment of the present invention, considering that the ion injection energy has a significant impact on the ion diffusion depth, the magnitude of the photocurrent depends on the concentration and movement speed of the minority carriers in the PIN diode 14. By reducing the ion injection energy, the ion diffusion depth can be reduced, the PN junction space charge region can be reduced, the depletion layer can be relatively widened, the number of minority carriers generated can be increased, the photocurrent can be increased, and the photoelectric performance of the PIN diode 14 can be ensured.

[0092] Exemplarily, the ion implantation energy can be reduced to less than 16K, and the doped ions can be implanted into the film layer to be processed by ion implantation to form the P-type semiconductor layer 143, thereby minimizing the depth of diffusion of the first doped ions into the intrinsic semiconductor layer 142 and ensuring the photoelectric performance of the PIN diode 14.

[0093] The following further illustrates the technical effects that can be achieved by the technical solution of this embodiment with specific experimental data.

[0094] refer to Figure 9 , Figure 9 A schematic diagram of photocurrent corresponding to different ion implantation energies and the same first ion implantation dose provided by an embodiment of the present invention.

[0095] Figure 9Curve 1 in the middle represents the photocurrent curve of the PIN diode 14 in which the P-type semiconductor layer 143 is formed by the first ion implantation energy and the first ion implantation dose, and curve 2 represents the photocurrent curve of the PIN diode 14 in which the P-type semiconductor layer 143 is formed by the second ion implantation energy and the first ion implantation dose. Figure 9 , the horizontal axis represents a reverse bias voltage applied to the P-type semiconductor layer 143 and the N-type semiconductor layer 141, and the vertical axis represents the photocurrent. The first ion implantation energy is greater than the second ion implantation energy, and both the first ion implantation energy and the second ion implantation energy are less than 16K.

[0096] The experimental test results show that reducing the ion implantation energy of the IMP process when preparing the P-type semiconductor layer 143 can significantly increase the photocurrent of the PIN diode 14 .

[0097] refer to Figure 10 , Figure 10 A schematic diagram of a projection range under a first ion implantation energy and a first ion implantation dose provided by an embodiment of the present invention; Figure 11 , Figure 11 A schematic diagram of a projection range under a second ion implantation energy and a first ion implantation dose provided by an embodiment of the present invention.

[0098] In other words, Figure 10 A schematic diagram of RP under a first ion implantation energy and a first ion implantation dose provided by an embodiment of the present invention; Figure 11 A schematic diagram of RP under a second ion implantation energy and a first ion implantation dose provided in an embodiment of the present invention; it reflects the average penetration depth of ion implantation in the IMP process.

[0099] Figure 10 The middle curve 3 represents the curve corresponding to the main element during the test, such as Si element; the curve 4 represents the curve corresponding to the first doping element during the test, such as B element; Figure 11 The middle curve 5 represents the curve corresponding to the main element during the test, such as Si element; the curve 6 represents the curve corresponding to the first doping element during the test, such as B element.

[0100] in Figure 10 and Figure 11 The middle horizontal axis represents the ion implantation depth; the left vertical axis represents the concentration, which converts the original signal into a physical quantity through calibration; the right vertical axis represents the signal intensity directly measured in the D-SIMS test.

[0101] The experimental test results analyzed by D-SIMS show that Figure 10 The medium RP value is about 34.6nm, Figure 11The RP value is about 15 nm, indicating that reducing the ion implantation energy of the IMP process when preparing the P-type semiconductor layer 143 can significantly reduce the ion implantation depth, thereby minimizing the depth of the first doped ions diffusing into the intrinsic semiconductor layer 142 , making the PN junction space charge region smaller, the depletion layer relatively wider, and the number of minority carriers generated increasing, the photocurrent increasing, and ensuring the photoelectric performance of the PIN diode 14 .

[0102] In an optional embodiment of the present invention, reference Figure 12 , Figure 12 A schematic flow chart of another method for preparing a PIN diode provided in an embodiment of the present invention. The doping ions further include second doping ions, the ion mass of the second doping ions being greater than the ion mass of the first doping ions; another possible implementation of "implanting the doping ions into the film layer to be processed to form the P-type semiconductor layer 143 by ion implantation" in step S103 is:

[0103] S1032 : Implanting the first doping ions and the second doping ions into the film layer to be processed simultaneously by ion implantation to form a P-type semiconductor layer 143 .

[0104] Specifically, in the embodiment of the present invention, the IMP process is adopted to simultaneously implant the first doping ions and the second doping ions into the film layer to be processed by ion implantation to form the P-type semiconductor layer 143 .

[0105] Among them, the first doping ion is B ion, that is, a P-type semiconductor layer is formed by the injection of B ions. The second doping ion includes but is not limited to at least one of F ion and Ar ion. Under the same ion injection energy, the ion with a large ion mass moves slower, and the ion with a small ion mass moves faster. In order to prevent the first doping ion from moving faster and making its ion injection depth deeper, the second doping ion is injected at the same time as the first doping ion. The second doping ion slows down or buffers the diffusion of the first doping ion to a deeper area, thereby minimizing the depth of the first doping ion diffusion to the intrinsic semiconductor layer 142 and ensuring the photoelectric performance of the PIN diode 14.

[0106] From another perspective, by introducing a second doping ion, such as Ar ions and / or F ions, the proportion of B ions will be reduced, so that under the same ion injection energy, the injection depth and dose will become smaller, thereby achieving the purpose of reducing the diffusion depth of B ions.

[0107] The following further illustrates the technical effects that can be achieved by the technical solution of this embodiment with specific experimental data.

[0108] refer to Figure 13 , Figure 13 A schematic diagram of the first ion implantation energy and the corresponding photocurrent under different doping ions provided in an embodiment of the present invention; Figure 14 , Figure 14 A schematic diagram of a second ion implantation energy and corresponding photocurrents under different doping ions provided by an embodiment of the present invention.

[0109] Figure 13 Curve 7 in the middle represents the photocurrent curve of the PIN diode 14 in which only B doping ions are implanted to form B doping and a P-type semiconductor layer 143 is formed at the first ion implantation energy, wherein the dose of the B doping ions is the first ion implantation dose; Curve 8 represents the photocurrent curve of the PIN diode 14 in which B doping ions and F doping ions are implanted to form BF doping and a P-type semiconductor layer 143 is formed at the first ion implantation energy, wherein the total dose of the BF doping is the first ion implantation dose. Figure 13 In FIG. 1 , the abscissa represents a reverse bias voltage applied to the P-type semiconductor layer 143 and the N-type semiconductor layer 141 , and the ordinate represents the photocurrent.

[0110] Figure 14 Curve 9 in the middle represents the photocurrent curve of the PIN diode 14 in which the P-type semiconductor layer 143 is formed by implanting B doping ions and F doping ions to form BF doping at the second ion implantation energy, wherein the total dose of BF doping is the first ion implantation dose; Curve 10 represents the photocurrent curve of the PIN diode 14 in which the P-type semiconductor layer 143 is formed by implanting B doping ions and F doping ions to form BF2 doping at the second ion implantation energy, wherein the total dose of BF2 doping is the first ion implantation dose. Figure 14 In FIG. 1 , the abscissa represents a reverse bias voltage applied to the P-type semiconductor layer 143 and the N-type semiconductor layer 141 , and the ordinate represents the photocurrent.

[0111] Experimental test results indicate that when using the IMP process to prepare P-type semiconductor layer 143, the introduction of F-doped ions reduces the proportion of B-doped ions, resulting in a smaller implantation depth and dose at the same ion implantation energy, reducing the diffusion depth of the B-doped ions. It has been verified that the photocurrent of PIN diode 14 corresponding to BF2 doping is significantly better than that of PIN diode 14 corresponding to BF doping, and the photocurrent of PIN diode 14 corresponding to BF doping is significantly better than that of PIN diode 14 corresponding to B doping.

[0112] Similarly, when using the IMP process to prepare P-type semiconductor layer 143, the introduction of Ar dopant ions reduces the proportion of B dopant ions, resulting in a smaller implantation depth and dose at the same ion implantation energy, reducing the diffusion depth of the B dopant ions. It has been verified that the photocurrent of PIN diode 14 corresponding to B and Ar doping is significantly better than the photocurrent of PIN diode 14 corresponding to B doping.

[0113] refer to Figure 15 , Figure 15 A schematic diagram of a first ion implantation energy, B doping, and a projection range when the dose of the B doped ions is the first ion implantation dose provided by an embodiment of the present invention; Figure 16 , Figure 16 A schematic diagram of a first ion implantation energy, BF doping, and a projection range when the total BF doping dose is the first ion implantation dose provided by an embodiment of the present invention.

[0114] In other words, Figure 15 A schematic diagram of RP provided by an embodiment of the present invention with a first ion implantation energy, B doping, and a dose of B doped ions being the first ion implantation dose; Figure 11 A schematic diagram of RP provided in an embodiment of the present invention for a first ion implantation energy, BF doping, and a total BF doping dose equal to the first ion implantation dose; it reflects the average penetration depth of ion implantation in the IMP process.

[0115] Figure 15 The middle curve 11 represents the curve corresponding to the main element during the test, such as Si element; the curve 12 represents the curve corresponding to B doping during the test; Figure 16 The middle curve 13 represents the curve corresponding to the main element during the test, such as Si element; the curve 14 represents the curve corresponding to BF doping during the test.

[0116] in Figure 15 and Figure 16 The middle horizontal axis represents the ion implantation depth; the left vertical axis represents the concentration, which converts the original signal into a physical quantity through calibration; the right vertical axis represents the signal intensity directly measured in the D-SIMS test.

[0117] The experimental test results analyzed by D-SIMS show that Figure 15 The medium RP value is about 34.6nm, Figure 16 The RP value is about 12 nm, indicating that the ion implantation depth of BF is significantly smaller than that of B, thereby minimizing the depth of diffusion of doped ions into the intrinsic semiconductor layer 142 , making the PN junction space charge region smaller and the depletion layer relatively wider, resulting in an increase in the number of minority carriers and photocurrent, thereby ensuring the photoelectric performance of the PIN diode 14 .

[0118] In an optional embodiment of the present invention, reference Figure 17 , Figure 17 A schematic flow chart of another method for preparing a PIN diode provided in an embodiment of the present invention. The process parameters of the IMP process also include an ion implantation dose. Another possible implementation of step S1031, "using the IMP process to implant the dopant ions into the film layer to be processed to form the P-type semiconductor layer 143," is as follows:

[0119] S1031B: reducing the ion implantation dose and implanting the doping ions into the film layer to be processed by ion implantation to form the P-type semiconductor layer 143 .

[0120] Specifically, in the embodiment of the present invention, it is taken into account that the ion implantation dose will also have a certain impact on the ion diffusion depth. The magnitude of the photocurrent depends on the concentration and movement speed of the minority carriers in the PIN diode 14. By reducing the ion implantation dose, the ion diffusion depth can be reduced, the PN junction space charge region can be reduced, the depletion layer can be relatively widened, the number of minority carriers generated can be increased, the photocurrent can be increased, and the photoelectric performance of the PIN diode 14 can be ensured.

[0121] For example, the ion implantation dose can be reduced to 5E12 ions / cm 2 -5E14ions / cm 2 The doping ions are implanted into the film layer to be processed by ion implantation to form the P-type semiconductor layer 143, thereby minimizing the depth of diffusion of the first doping ions into the intrinsic semiconductor layer 142 and ensuring the photoelectric performance of the PIN diode 14.

[0122] The following further illustrates the technical effects that can be achieved by the technical solution of this embodiment with specific experimental data.

[0123] refer to Figure 18 , Figure 18 A schematic diagram of the corresponding photocurrent under the same ion implantation energy and different ion implantation doses provided by an embodiment of the present invention.

[0124] Figure 18 The middle curve 15 represents the photocurrent curve of the PIN diode 14 in which the P-type semiconductor layer 143 is formed by the first ion implantation dose, and the curve 16 represents the photocurrent curve of the PIN diode 14 in which the P-type semiconductor layer 143 is formed by the second ion implantation dose. Figure 18 In FIG. 1 , the horizontal axis represents a reverse bias voltage applied to the P-type semiconductor layer 143 and the N-type semiconductor layer 141 , and the vertical axis represents the photocurrent.

[0125] The experimental test results show that reducing the ion implantation dose of the doping ions when preparing the P-type semiconductor layer 143 using the IMP process can significantly increase the photocurrent of the PIN diode 14 .

[0126] From the above description, it can be seen that the embodiment of the present invention adopts the IMP process to prepare the P-type semiconductor layer 143 by ion implantation, and by at least adjusting the ion implantation energy, the type of doped ions, and the ion implantation dose, the depth of the doped ions diffusion into the intrinsic semiconductor layer 142 is minimized to ensure the photoelectric performance of the PIN diode 14.

[0127] Obviously, in the scheme of adjusting the ion implantation energy, dopant ion species, and ion implantation dose, only one of the three parameters can be adjusted, any two of the three parameters can be adjusted, or all three parameters can be optimized and adjusted simultaneously. In the embodiment of the present invention, the main scheme is described by adjusting the ion implantation energy and dopant ion species separately or simultaneously.

[0128] In an optional embodiment of the present invention, reference Figure 19 , Figure 19 A schematic diagram of a process for forming an intrinsic semiconductor layer provided in an embodiment of the present invention. One possible way to form the intrinsic semiconductor layer 142 is:

[0129] S201 : Determine the effective thickness of the intrinsic semiconductor layer 142 required for the fabricated PIN diode 14 .

[0130] S202 : forming an intrinsic semiconductor layer 142 with a first thickness, wherein the first thickness is greater than the effective thickness.

[0131] Specifically, in the embodiment of the present invention, the effective thickness of the intrinsic semiconductor layer 142 required for the prepared PIN diode 14 is first determined. Then, when preparing the intrinsic semiconductor layer 142, an intrinsic semiconductor layer 142 having a thickness greater than the effective thickness is formed. At this time, the difference area between the first thickness and the effective thickness provides a diffusion space for the diffusion of the first doped ions. Even if the first doped ions diffuse into the intrinsic semiconductor layer 142 at this time, the effective thickness of the retained intrinsic semiconductor layer 142 that does not diffuse into the first doped ions can ensure the normal operation of the PIN diode 14, thereby ensuring the photoelectric performance of the PIN diode 14.

[0132] In an optional embodiment of the present invention, reference Figure 20 , Figure 20 A schematic flow chart of another method for preparing a PIN diode provided in an embodiment of the present invention. Before forming the N-type semiconductor layer 141, the method for preparing the PIN diode further includes:

[0133] S104 : forming a first electrode 144 , wherein the first electrode 144 is connected to the N-type semiconductor layer 141 .

[0134] After the P-type semiconductor layer 143 is prepared, the method for preparing the PIN diode further includes:

[0135] S105 : forming a second electrode 145 , wherein the second electrode 145 is connected to the P-type semiconductor layer 143 .

[0136] In the embodiment of the present invention, the anode layer 22 in the array layer 13 of the display panel 100 is connected to the P-type semiconductor layer 143 and / or the N-type semiconductor layer 141. Figure 4 As shown, the N-type semiconductor layer 141 is electrically connected to the anode layer 22 through the first electrode 144 , and the P-type semiconductor layer 143 is electrically connected to the anode layer 22 through the second electrode 145 .

[0137] Since the anode layer 22 is composed of independent anode units, some anode units that are not required to constitute the sub-pixels 11 are formed during the preparation of the anode layer 22 to achieve electrical connection with the PIN diode 14, thereby simplifying the circuit connection.

[0138] Accordingly, the embodiment of the present application further provides a display device, referring to Figure 21 , Figure 21 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. The display device 200 includes the display panel 100 described in the above embodiment of the present application. The display device 200 can be any electronic device with a display function, such as a touch screen display, a mobile phone, a tablet computer, a laptop computer, an e-reader, or a television.

[0139] The above is a detailed introduction to the preparation method of a display panel, a display device, and a PIN diode provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

[0140] It should be noted that each embodiment in this specification focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referenced to each other.

[0141] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that the process, method, article, or apparatus comprising a series of elements inherent to the elements, or also including elements inherent to these processes, methods, articles, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0142] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: The display panel includes: substrate; an array layer located on one side of the substrate; A PIN diode integrated in the array layer; the PIN diode includes an N-type semiconductor layer, an intrinsic semiconductor layer, and a P-type semiconductor layer; The P-type semiconductor layer includes doping ions implanted by ion implantation, the doping ions include first doping ions, and the ion implantation depth of the first doping ions is less than the thickness of the P-type semiconductor layer.

2. The display panel according to claim 1, wherein: The doping ions further include second doping ions; The ion mass of the second doping ions is greater than the ion mass of the first doping ions.

3. The display panel according to claim 2, wherein: The second doping ions include at least one of F ions and Ar ions.

4. The display panel according to claim 1, wherein: The film forming speed of the P-type semiconductor layer is less than 25% of the film forming speed of the intrinsic semiconductor layer.

5. The display panel according to claim 1, wherein: The ion implantation depth of the first dopant ion is H, and the thickness of the P-type semiconductor layer is G; Where H = G / 2.

6. The display panel according to claim 1, wherein: The PIN diode further comprises: A first electrode connected to the N-type semiconductor layer, and a second electrode connected to the P-type semiconductor layer.

7. The display panel according to any one of claims 1 to 6, characterized in that: The display panel further includes: a plurality of sub-pixels located on a side of the array layer facing away from the substrate; A light-transmitting area is provided between at least some adjacent two sub-pixels; An orthographic projection of the light-transmitting region at least completely covers the intrinsic semiconductor layer.

8. The display panel according to claim 7, wherein: The sub-pixel comprises: an anode layer, a light-emitting layer and a cathode layer which are stacked; The anode layer is connected to the P-type semiconductor layer and / or the N-type semiconductor layer.

9. The display panel according to claim 1, wherein: The PIN diode is a photo PIN diode.

10. A method for preparing a PIN diode, characterized in that: Used to prepare the PIN diode according to any one of claims 1 to 9, the preparation method of the PIN diode comprising: forming an N-type semiconductor layer and an intrinsic semiconductor layer stacked in layers; forming a film layer to be processed on a side of the intrinsic semiconductor layer away from the N-type semiconductor layer; Doping ions are implanted into the film layer to be processed by ion implantation to form a P-type semiconductor layer; wherein the doping ions include first doping ions, and the ion implantation depth of the first doping ions is less than the thickness of the P-type semiconductor layer.

11. The method for preparing a PIN diode according to claim 10, wherein: The method of forming a stacked N-type semiconductor layer and an intrinsic semiconductor layer includes: The N-type semiconductor layer and the intrinsic semiconductor layer are formed in sequence by adopting a CVD process.

12. The method for preparing a PIN diode according to claim 10, wherein: The step of implanting dopant ions into the film layer to be processed by ion implantation to form a P-type semiconductor layer includes: The doping ions are implanted into the film layer to be processed by ion implantation using an IMP process to form the P-type semiconductor layer.

13. The method for preparing a PIN diode according to claim 12, wherein: The process parameters of the IMP process include ion implantation energy. The IMP process is used to implant the dopant ions into the film layer to be processed to form the P-type semiconductor layer, including: The ion implantation energy is reduced to implant the doping ions into the film layer to be processed by ion implantation to form the P-type semiconductor layer.

14. The method for preparing a PIN diode according to claim 13, wherein: The step of reducing the ion implantation energy to implant the doping ions into the film layer to be processed to form the P-type semiconductor layer includes: The ion implantation energy is reduced to less than 16K, and the doping ions are implanted into the film layer to be processed by ion implantation to form the P-type semiconductor layer.

15. The method for preparing a PIN diode according to any one of claims 10 to 14, characterized in that: The doping ions further include second doping ions, wherein the ion mass of the second doping ions is greater than the ion mass of the first doping ions; The step of implanting dopant ions into the film layer to be processed by ion implantation to form a P-type semiconductor layer includes: The first doping ions and the second doping ions are simultaneously implanted into the film layer to be processed by ion implantation to form a P-type semiconductor layer.

16. The method for preparing a PIN diode according to claim 12, wherein: The process parameters of the IMP process also include an ion implantation dose. The IMP process is used to implant the doping ions into the film layer to be processed to form the P-type semiconductor layer, including: The ion implantation dose is reduced to implant the doping ions into the film layer to be processed by ion implantation to form the P-type semiconductor layer.

17. The method for preparing a PIN diode according to claim 16, wherein: The step of reducing the ion implantation dose and implanting the doping ions into the film layer to be processed by ion implantation to form the P-type semiconductor layer includes: Reduce the ion implantation dose to 5E12ions / cm 2 -5E14ions / cm 2 , the doping ions are implanted into the film layer to be processed by ion implantation to form the P-type semiconductor layer.

18. The method for preparing a PIN diode according to claim 10, wherein: Forming the intrinsic semiconductor layer includes: Determining the effective thickness of the intrinsic semiconductor layer required for the fabricated PIN diode; An intrinsic semiconductor layer having a first thickness is formed, wherein the first thickness is greater than the effective thickness.

19. The method for preparing a PIN diode according to claim 10, wherein: Before forming the N-type semiconductor layer, the method for preparing the PIN diode further includes: A first electrode is formed, wherein the first electrode is connected to the N-type semiconductor layer.

20. The method for preparing a PIN diode according to claim 10, wherein: The method for preparing the PIN diode further includes: A second electrode is formed, wherein the second electrode is connected to the P-type semiconductor layer.

21. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 9.

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