Independent addressing of single-wire and two-wire devices on shared RFFE bus interface

Abstract

A data communication apparatus coupled to a serial bus has a protocol controller that configures to a first plurality of slave devices a device identifier unique within the first plurality of slave devices, and configures to a second plurality of slave devices a device identifier unique within the second plurality of slave devices. A sequence start condition sent over the serial bus indicates a first communication mode in which a clock signal is provided to the serial bus or a second communication mode in which no clock signal is provided. A device identifier associated with the first plurality of slave devices is used to transmit a first datagram over the serial bus in the first communication mode, and a device identifier associated with the second plurality of slave devices is used to transmit a second datagram over the serial bus in the second communication mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. non-provisional application No. 18 / 157,000, filed on January 19, 2023, which is assigned to the assignee of this patent application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] The present disclosure relates generally to serial communications, and more particularly to addressing of devices configured for single-wire communications and devices configured for two-wire communications on a shared radio frequency front-end serial bus. Background Art

[0004] Mobile communication devices may include various components, including circuit boards, integrated circuit (IC) devices, and / or system-on-chip (SoC) devices. These components may include processing devices, user interface components, storage devices, and other peripheral components that communicate over a shared data communication bus, which may include a multi-point serial bus or a parallel bus. Common serial interfaces known in the industry include Inter-Integrated Circuit (I2C or I2C) and Inter-Integrated Circuit (I2C). 2 C) Serial interfaces and their derivatives and alternatives.

[0005] The Mobile Industry Processor Interface (MIPI) Alliance defines standards and protocols for the improved Inter-IC (I3C) serial interface, the Radio Frequency Front-End (RFFE) interface, the System Power Management Interface (SPMI), and other interfaces. These interfaces can be used to connect, for example, processors, sensors, and other peripheral devices. In some interfaces, multiple host devices are coupled to a serial bus, allowing two or more devices to act as hosts for different types of messages sent on the serial bus. The RFFE interface defines a communication interface that can be used to control various radio frequency (RF) front-end devices, including power amplifiers (PAs), low-noise amplifiers (LNAs), antenna tuners, filters, sensors, power management devices, switches, and more. These devices can be co-located in a single IC device or provided in multiple IC devices. In mobile communication devices, multiple antennas and radio transceivers can support multiple concurrent RF links. In another example, the SPMI specification defined by the MIPI Alliance provides a hardware interface that can be implemented between a baseband or application processor and peripheral components. In some implementations, SPMI is deployed to support power management operations within the device.

[0006] As device complexity increases, the demand for input / output pins also increases, and there is a need for simplified bus architectures and protocols that can coexist with legacy bus architectures and protocols. Summary of the Invention

[0007] Certain aspects of the present disclosure relate to systems, apparatus, methods, and techniques that may support communicating with a device interface using a single-wire link while some devices coupled to the single-wire link communicate using multiple wires.

[0008] In various aspects of the present disclosure, a method performed at a host device coupled to a serial bus includes: configuring each slave device in a first plurality of slave devices with a device identifier that is unique within the first plurality of slave devices; configuring each slave device in a second plurality of slave devices with a device identifier that is unique within the second plurality of slave devices; sending a sequence start condition over a data line of the serial bus, the sequence start condition indicating whether a clock pulse will be provided in a clock signal on a clock line of the serial bus concurrently with a transaction initiated by the sequence start condition; when the sequence start condition indicates that a clock pulse will be provided in the clock signal concurrently, sending a first datagram over the serial bus to one of the first plurality of slave devices using the device identifier associated with the first plurality of slave devices; and when the sequence start condition indicates that no clock pulse will be provided in the clock signal concurrently, sending a second datagram over the serial bus to one of the second plurality of slave devices using the device identifier associated with the second plurality of slave devices.

[0009] In various aspects of the present disclosure, a data communication apparatus has: an interface circuit adapted to couple the data communication apparatus to two lines of a serial bus; and a protocol controller configured to: configure each slave device in a first plurality of slave devices with a device identifier unique within the first plurality of slave devices; configure each slave device in a second plurality of slave devices with a device identifier unique within the second plurality of slave devices; send a sequence start condition over a data line of the serial bus, the sequence start condition indicating whether a clock pulse will be provided in a clock signal on a clock line of the serial bus concurrently with a transaction initiated by the sequence start condition; when the sequence start condition indicates that a clock pulse will be provided concurrently in the clock signal, send a first datagram over the serial bus to one of the first plurality of slave devices using the device identifier associated with the first plurality of slave devices; and when the sequence start condition indicates that no clock pulse will be provided concurrently in the clock signal, send a second datagram over the serial bus to one of the second plurality of slave devices using the device identifier associated with the second plurality of slave devices.

[0010] In various aspects of the present disclosure, a method performed at a slave device coupled to a serial bus includes: receiving a first sequence start condition from a data line of the serial bus, the first sequence start condition indicating a first operating mode of the serial bus, in which first operating mode, a first datagram sent after the first sequence start condition will be sent concurrently with a clock pulse in a clock signal sent on a clock line of the serial bus; receiving a second sequence start condition from the data line, the second sequence start condition indicating a second operating mode of the serial bus, in which second operating mode, a second datagram sent after the second sequence start condition will be sent together with embedded clock information in the data signal; responding to a first command included in the first datagram when the first command is sent to an address corresponding to a first device identifier associated with the slave device; and responding to the second command included in the second datagram when the second command is sent to an address corresponding to a second device identifier associated with the slave device.

[0011] In various aspects of the present disclosure, a device has interface circuitry adapted to couple the device to two lines of a serial bus, and a processor. The processor can be configured to receive a first sequence start condition from a data line of the serial bus, the first sequence start condition indicating a first operating mode of the serial bus, in which a first datagram sent after the first sequence start condition is sent concurrently with a clock pulse in a clock signal sent on a clock line of the serial bus; receive a second sequence start condition from the data line, the second sequence start condition indicating a second operating mode of the serial bus, in which a second datagram sent after the second sequence start condition is sent with embedded clock information in the data signal; respond to a first command included in the first datagram when the first command is sent to an address corresponding to a first device identifier associated with the device; and respond to a second command included in the second datagram when the second command is sent to an address corresponding to a second device identifier associated with the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 An apparatus is illustrated that employs a data link between IC devices that selectively operates according to one of a plurality of available standards.

[0013] Figure 2 The system architecture of an apparatus employing a data link between IC devices is illustrated.

[0014] Figure 3 Illustrated is a device configuration for coupling various RF front-end devices using multiple RFFE buses.

[0015] Figure 4A system in which single-wire slave devices and two-wire slave devices coexist according to certain aspects disclosed herein is illustrated.

[0016] Figure 5 Illustrate the sequence start condition defined by the RFFE protocol.

[0017] Figure 6 Examples of transactions conducted on a multimode serial bus in accordance with certain aspects disclosed herein are illustrated.

[0018] Figure 7 is a flow chart illustrating an example of communications in a device coupled to a hybrid bus that couples a single-wire slave device and a two-wire slave device to a host device.

[0019] Figure 8 Certain aspects of addressing on a hybrid serial bus configured according to certain aspects of the present disclosure are illustrated.

[0020] Figure 9 A host device configured to manage communications over a hybrid serial bus is illustrated in accordance with certain aspects of the present disclosure.

[0021] Figure 10 An erroneous two-wire SSC sent on a data line of a serial bus configured according to certain aspects of the present disclosure is illustrated.

[0022] Figure 11 Illustrate a datagram structure that can conform to or be compatible with the RFFE protocol.

[0023] Figure 12 One example of an apparatus employing processing circuitry that may be adapted according to certain aspects disclosed herein is illustrated.

[0024] Figure 13 is a flow chart illustrating a method for communicating data at a master device according to certain aspects disclosed herein.

[0025] Figure 14 Illustrated are examples of hardware implementations for host device apparatus adapted according to certain aspects disclosed herein.

[0026] Figure 15 is a flow chart illustrating a method for communicating data at a single-wire slave device in accordance with certain aspects disclosed herein.

[0027] Figure 16 An example of a hardware implementation of a single-wire slave device adapted according to certain aspects disclosed herein is illustrated. DETAILED DESCRIPTION

[0028] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations with which the concepts described herein may be practiced. In order to provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0029] Several aspects of the present invention will now be described with reference to various devices and methods. These devices and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0030] Certain aspects of the present disclosure relate to serial bus configurations in which multiple devices can communicate at various times. The described serial buses typically operate in a hierarchical manner, with one device controlling communications during a transaction. The controlling device may be referred to as a host device, bus master, management device, or another terminology supported by the standard defining the protocol implemented by the controlling device. In some serial bus configurations, a single controlling device manages or controls communications during all transactions conducted over the serial bus. In other serial bus configurations, multiple devices may operate as controlling devices, with one device acting as the controlling device for each transaction conducted over the serial bus. The controlling device may provide a common clock signal transmitted over a conventional two-wire serial bus. The controlling device may provide control signaling that identifies the type of transaction to be conducted over the conventional two-wire serial bus. During certain transactions, the controlling device may send commands directed to one or more receiving devices using address information provided in or with the command. Receiving devices may be referred to as slave devices, client devices, slave devices, peripheral devices, or another terminology supported by the standard defining the protocol implemented by the controlling device. For the purposes of this disclosure, the controlling device will be referred to as the host device, and the associated receiving devices will be referred to as slave devices.

[0031] Overview

[0032] Devices that include multiple SoCs and other IC devices often employ a shared communication interface that may include a serial bus or other data communication link for connecting the processor to a modem and other peripheral devices. The serial bus or other data communication link may operate according to one or more defined standards or protocols. For example, the serial bus may operate according to the I2C, I3C, SPMI, and / or RFFE protocols, or another protocol that may be configured for half-duplex operation. Increased functionality and operational complexity of devices coupled to the serial bus, as well as tighter timing constraints imposed to support applications, peripherals, and sensors, may result in greater demands on GPIO and communication link throughput.

[0033] Certain aspects of the present disclosure relate to techniques for communicating over a single wire by combining data and clock information in the same signal. In one example, the data and clock information can be encoded using pulse width modulation (PWM). In another example, Manchester encoded data carries clock information in each transmitted bit. In one aspect, a host device can be adapted to communicate with some slave devices over a single wire (data only) and communicate with other devices over a dual wire (data and clock). A protocol controller can signal the type of communication (single or dual) based on the duration of a sequence start condition (SSC) used to initiate a transaction.

[0034] Various aspects of the SSC are defined by the RFFE protocol. The duration of the high and low portions are specified by the protocol, and the rise and fall times of the transitions in the SSC are defined by the protocol. Limits on the frequency of the clock signal sent on the SCLK line of the RFFE bus may also be defined by the protocol. In one aspect of the present disclosure, the protocol controller may be configured to send a modified SSC to indicate when a transaction is in progress with a single-wire slave device. In some examples, the protocol controller may send an extended length SSC to target a single-wire slave device for communication. In some implementations, the protocol controller may send a shortened SSC to target a single-wire slave device for communication. In some instances, the protocol controller may send an SSC with modified rise and fall times to target a single-wire slave device for communication.

[0035] In one example, a host device includes an interface circuit adapted to couple the device to two lines of a serial bus and a protocol controller. The protocol controller may configure each slave device in a first plurality of slave devices with a device identifier unique within the first plurality of slave devices; configure each slave device in a second plurality of slave devices with a device identifier unique within the second plurality of slave devices; transmit a sequence start condition over a data line of the serial bus, the sequence start condition indicating whether a clock pulse will be provided in a clock signal on a clock line of the serial bus concurrently with a transaction initiated by the sequence start condition; transmit a first datagram over the serial bus to one of the first plurality of slave devices using the device identifier associated with the first plurality of slave devices when the sequence start condition indicates that a clock pulse will be provided concurrently in the clock signal; and transmit a second datagram over the serial bus to one of the second plurality of slave devices using the device identifier associated with the second plurality of slave devices when the sequence start condition indicates that no clock pulse will be provided concurrently in the clock signal.

[0036] Certain aspects disclosed herein may be used to replace or supplement serial bus protocols, such as I2C, I3C, SPMI, and / or RFFE protocols, or point-to-point interfaces based on UART, line multiplexing UART (LM-UART). Certain aspects are applicable to serial buses operating in half-duplex mode or full-duplex mode. Certain aspects are applicable to point-to-point interfaces, including UART-based interfaces, line multiplexing UART (LM-UART) interfaces. In some specific implementations, certain aspects disclosed herein may be deployed to support the exchange of virtual GPIO (VGI) messages. Certain aspects are applicable to multi-point interfaces and / or interfaces operating in point-to-point mode.

[0037] Example of a device using a serial data link

[0038] According to certain aspects of the present disclosure, serial data links may be used to interconnect electronic devices that are subcomponents of devices such as: cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, Global Positioning System (GPS) devices, smart home devices, smart lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, entertainment devices, vehicle components, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), appliances, sensors, security devices, vending machines, smart meters, drones, multi-rotor helicopters, or any other similarly functional devices.

[0039] Figure 1An example of an apparatus 100 that may employ a data communication bus is illustrated. Apparatus 100 may include an SoC, processing circuitry 102 having a plurality of circuits or devices 104, 106, and / or 108, which may be implemented in one or more ASICs or SoCs. In one example, apparatus 100 may be a communications device, and processing circuitry 102 may include a processing device provided in ASIC 104, one or more peripheral devices 106, and a transceiver 108 that enables the apparatus to communicate with a radio access network, a core access network, the Internet, and / or another network via an antenna 124.

[0040] ASIC 104 may have one or more processors 112, one or more modems 110, onboard memory 114, bus interface circuitry 116, and / or other logic circuitry or functionality. Processing circuit 102 may be controlled by an operating system, which may provide an application programming interface (API) layer that enables one or more processors 112 to execute software modules residing in onboard memory 114 or other processor-readable storage devices 122 provided on processing circuit 102. Software modules may include instructions and data stored in onboard memory 114 or processor-readable storage devices 122. ASIC 104 may access its onboard memory 114, processor-readable storage devices 122, and / or storage devices external to processing circuit 102. Onboard memory 114 and processor-readable storage devices 122 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash memory cards, or any other memory device useful in processing systems and computing platforms. The processing circuit 102 may include, implement, or access a local database or other parameter storage device that can maintain operating parameters and other information used to configure and operate the device 100 and / or the processing circuit 102. The local database can be implemented using registers, database modules, flash memory, magnetic media, EEPROM, a floppy disk, or a hard disk, etc. The processing circuit 102 can also be operably coupled to external devices such as an antenna 124, a display 126, operator controls such as switches or buttons 128, 130, and / or an integrated or external keyboard 132, and other components. The user interface module can be configured to operate with the display 126, the external keyboard 132, etc. via a dedicated communication link or via one or more serial data interconnects.

[0041] Processing circuitry 102 may provide one or more buses 118a, 118b, 120 that enable certain devices 104, 106, and / or 108 to communicate. In one example, ASIC 104 may include bus interface circuitry 116 that includes a combination of circuits, counters, timers, control logic, and other configurable circuits or modules. In one example, bus interface circuitry 116 may be configured to operate according to a communication specification or protocol. Processing circuitry 102 may include or control power management functionality that configures and manages the operation of apparatus 100.

[0042] Figure 2 The example includes a plurality of devices 202 and 2220-222 coupled to a serial bus 220. N Certain aspects of the apparatus 200. Devices 202 and 2220-222 N The devices 202 and 2220-222 may be implemented in one or more semiconductor IC devices such as application processors, SoCs, or ASICs. N The slave devices 2220-222 may include, support, or operate as modems, signal processing devices, display drivers, cameras, user interfaces, sensors, sensor controllers, media players, transceivers, RFFE devices, and / or other such components or devices. N One or more of the devices 202 and 2220-222 may be used to control, manage, or monitor sensor devices. N Communications between devices over serial bus 220 are controlled by master device 202. Some types of buses can support multiple master devices 202.

[0043] In one example, the master device 202 may include an interface controller 204 that manages access to the serial bus, configures the slave devices 2220-222 N The master device 202 may include a configuration register 206 or other storage device 224 and other control logic components 212 configured to handle protocols and / or higher-level functions. The control logic component 212 may include processing circuits such as a state machine, a sequencer, a signal processor, or a general-purpose processor. The master device 202 includes a transceiver 210 and line drivers / receivers 214a and 214b. The transceiver 210 may include a receiver, a transmitter, and common circuitry, wherein the common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on the timing in the clock signal 228 provided by the clock generation circuit 208. Other timing clocks 226 may be used by the control logic component 212 and other functions, circuits, or modules.

[0044] At least one device 2220-222 N It can be configured to operate as a slave device on the serial bus 220 and may include circuits and modules that support a display, image sensor, and / or control and communicate with one or more sensors that measure environmental conditions. In one example, the device 2220 configured to operate as a slave device may provide control functions, modules, or circuits 232, which include circuits and modules for supporting a display, image sensor, and / or control and communicate with one or more sensors that measure environmental conditions. The slave device 2220 may include configuration registers 234 or other storage 236, control logic 242, transceiver 240, and line drivers / receivers 244a and 244b. The control logic 242 may include processing circuitry such as a state machine, sequencer, signal processor, or general-purpose processor. The transceiver 210 may include a receiver, a transmitter, and common circuitry, wherein the common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on the timing in the clock signal 248 provided by the clock generation and / or recovery circuit 246. Clock signal 248 may be derived from a signal received from clock line 218. Other timing clocks 238 may be used by control logic 242 and other functions, circuits, or modules.

[0045] The serial bus 220 may operate according to RFFE, I2C, I3C, SPMI, or another protocol. N Can be configured to selectively operate as a master device or a slave device on the serial bus 220. Two or more devices 202, 2220-222 N Can be configured to operate as a master device on the serial bus 220 .

[0046] In some specific implementations, the serial bus 220 can operate according to the I3C protocol. Devices that communicate using the I3C protocol can coexist on the same serial bus 220 with devices that communicate using the I2C protocol. The I3C protocol can support different communication modes, including a single data rate (SDR) mode that is compatible with the I2C protocol. The high data rate (HDR) mode can provide data transfer rates between 6 megabits per second (Mbps) and 16 Mbps, and some HDR modes can provide higher data transfer rates. The I2C protocol can comply with the de facto I2C standard, providing data rates that can range between 100 kilobits per second (kbps) and 3.2 Mbps. In addition to data format and bus control aspects, the I2C and I3C protocols can also define electrical and timing aspects of signals sent on the two-wire serial bus 220. In some aspects, the I2C and I3C protocols can define direct current (DC) characteristics that affect certain signal levels associated with the serial bus 220 and / or alternating current (AC) characteristics that affect certain timing aspects of signals sent on the serial bus 220. In some examples, two-wire serial bus 220 sends data on data line 216 and a clock signal on clock line 218. In some instances, data can be encoded in signaling states or signaling state transitions of data line 216 and clock line 218.

[0047] Figure 3 FIG3 is a diagram illustrating an example of a configuration employing multiple RFFE buses 330, 332, 334 to couple various RF front-end devices 318, 320, 322, 324, 326, 328, illustrating communication links within a chipset or device 302. In this example, a modem 304 includes an RFFE interface 308 that couples the modem 304 to a first RFFE bus 330. The modem 304 can communicate with a baseband processor 306 and a radio frequency integrated circuit (RFIC 312) via respective communication links 310, 336, or, in some implementations, via a shared communication link 310 or 336. The illustrated device 302 can be embodied in one or more of a mobile communication device, a mobile phone, a mobile computing system, a mobile phone, a laptop computer, a tablet computing device, a media player, a gaming device, a wearable computing device, a wearable communication device, an appliance, and the like.

[0048] In various examples, the device 302 may be implemented with one or more baseband processors 306, a modem 304, an RFIC 312, multiple communication links 310, 336, multiple RFFE buses 330, 332, 334, and / or other types of buses. The device 302 may include other processors, circuits, modules, and may be configured for various operations and / or different functionality. Figure 3In the illustrated example, the modem 304 is coupled to the RF tuner 318 via its RFFE interface 308 and a first RFFE bus 330. The RFIC 312 may include one or more RFFE interfaces 314, 316, a controller, a state machine, and / or a processor that configure and control certain aspects of the RF front end. In the illustrated example, the RFIC 312 communicates with the PA 320 and the power tracking module 322 via a first RFFE interface and a second RFFE bus 332 in its RFFE interface 314. In the illustrated example, the RFIC 312 communicates with the switch 324 and one or more LNAs 326, 328 via a second RFFE interface and a third RFFE bus 334 in its RFFE interface 316.

[0049] Bus latency can affect the ability of a serial bus to handle high-priority, real-time, and / or other time-constrained messages. Low-latency messages, or messages requiring low bus latency, may involve sensor states, real-time events generated by devices, and virtualized GPIOs. In one example, bus latency can be measured as the time elapsed between a message becoming available for transmission and the delivery of the message. In another example, bus latency can be measured as the time elapsed between a message becoming available for transmission and the start of transmission of the message. Other measures of bus latency may be used. Bus latency typically includes delays incurred when sending higher priority messages, interrupt processing, the time required to terminate a datagram in progress on the serial bus, the time to send commands to cycle the bus between transmit and receive modes, bus arbitration, and / or the sending of commands specified by the protocol.

[0050] In one example, a latency-sensitive message carries or includes a coexistence message. Coexistence messages can be sent across a multi-system platform to prevent or mitigate situations where certain types of RFFE devices collide with each other. RFFE devices that can be the source or subject of coexistence messages include, for example, the switch 324, LNAs 326, 328, PA 320, and other types of devices operating concurrently in a manner that generates inter-device RF interference and / or could potentially cause damage to one or more devices. Coexistence management messages can be exchanged between certain devices that are shared across different radio access technologies, wireless subscriptions, and / or applications. For example, the switch 324, LNAs 326, 328, PA 320, and / or antennas may be shared by two different radio access technologies with different transmit and receive schedules, and if a device begins transmitting using one radio access technology and receiving using another, damage to the LNAs 326, 328 or other devices may occur. Devices that may interfere with each other can exchange coexistence management (CxM) messages to allow each device to signal impending actions that could cause interference or collisions. For example, two modems 304 can exchange CxM messages to manage the operation of shared components. In conventional systems, CxM messages can be exchanged using dedicated serial links, each implemented using a two-wire or four-wire universal asynchronous receiver / transmitter (UART). In multi-radio, multi-application systems, CxM interconnects and other device interconnects can consume a large number of physical input / output (I / O) pins and interconnects, increasing cost and routing complexity.

[0051] Multi-point interfaces (such as RFFE, SPMI, I3C, etc.) can reduce the number of physical input / output (I / O) pins used to communicate between multiple devices. The protocols that support communication over a multi-point serial bus define a datagram structure for sending command, control, and data payloads. The datagram structure for different protocols defines certain common features, including addressing for selecting a device to receive or send data, clock generation and management, interrupt handling, and device priority. In this disclosure, the example of the RFFE protocol may be used to illustrate certain aspects disclosed herein. However, the concepts disclosed herein are applicable to other serial bus protocols and standards.

[0052] According to certain aspects disclosed herein, a two-wire serial bus can be adapted to operate alternately in a conventional two-wire mode and a single-wire mode. In one example, the serial bus can operate according to an RFFE protocol, such that a clock line and a data line are used for communication with a two-wire slave device coupled to the serial bus, and the data line is used for communication with a single-wire slave device coupled to the serial bus without a clock signal. A host device can use pulse width modulation to encode data sent to a single-wire slave device.

[0053] Figure 4 A system 400 is illustrated in accordance with certain aspects disclosed herein, wherein a single-wire slave device 404 and a two-wire slave device 406 can coexist, and wherein a host device 402 can communicate with both the single-wire slave device 404 and the two-wire slave device 406. The host device 402 can be provided in an RFIC, a modem, an application processor, or another type of device. The host device 402 is coupled to one or more slave devices 404, 406 via at least an SDATA line 410 of a two-wire serial bus 408, which also has an SCLK line 412. Data can be encoded in a data signal transmitted via the SDATA line 410, and in a two-wire communication mode, a receiver can extract the data using a clock signal transmitted via the SCLK line 412. In the illustrated example, the serial bus 408 operates according to the RFFE protocol. In other examples, the serial bus 408 can operate according to another protocol, such as the I3C protocol, the SPMI protocol, or the like. In the illustrated example, each single-wire slave device 404 and each two-wire slave device 406 is coupled to SDATA line 410. Single-wire slave device 404 is adapted for single-wire communication mode, while two-wire slave device 406 is also coupled to SCLK line 412 to receive a clock signal used in two-wire communication mode.

[0054] The host device 402 may include a protocol controller 414, which may be implemented by processing circuitry including a processor, controller, state machine, or other logic components. The protocol controller 414 may be configured to support one or more protocols that may be used to manage the operation of the serial bus 408. In some implementations, the protocol controller 414 may be operable to configure one or more slave devices 404, 406. The protocol controller 414 may determine the configuration of the slave devices 404, 406 that are designated recipients of data to be transmitted via the serial bus 408 and may accordingly encode the data in the signal to be transmitted via the SDATA line 410. In some instances, a broadcast message for a combination of single-wire slave devices 404 and dual-wire slave devices 406 may be transmitted twice: once in single-wire communication mode and once in dual-wire communication mode. The protocol controller 414 may also determine whether and / or when a clock signal is to be transmitted via the SCLK line 412. In some implementations, the clock signal is suppressed when data is being transmitted to one or more single-wire slave devices 404 in single-wire communication mode.

[0055] According to certain aspects disclosed herein, a host device 402 can select between a single-wire slave device 404 and a two-wire slave device 406 when starting a transaction. The host device 402 can use different sequence start conditions (SSCs) to precede single-wire transactions and two-wire transactions. In some implementations, certain interface characteristics of the single-wire slave device 404 and / or the two-wire slave device 406 can be configurable. For example, the single-wire slave device 404 and / or the two-wire slave device 406 coupled to the serial bus 408 can match a specified bus capacitance when driving the SDATA line 410 based on a configurable register setting that defines a specified capacitance for the SDATA line 410. In other examples, the specified bus capacitance can be hardwired into the single-wire slave device 404 and / or the two-wire slave device 406.

[0056] Figure 5 RFFE sequence start timing 500 including SSC 504 defined by the RFFE protocol is illustrated. Figure 4 Serial bus 408 is initially in an idle state, with both SDATA line 410 and SCLK line 412 low. Host device 402 can initiate a transaction by sending a two-bit SSC 504. The bit time, or the time each bit is sent, can be determined by the frequency of an internal clock 502 used by host device 402. Internal clock 502 can be selected to control the bit rate of serial bus 408 during data transmission. SSC 504 includes a pulse sent on SDATA line 410 while SCLK line 412 remains low. The pulse includes a one-bit high portion 506 followed by a one-bit low portion 508. SSC 504 may be followed by a slave address 510. In conventional RFFE operation, information bits, including payload data, address, and control bits, are sampled or captured when clock pulses are provided on SCLK line 412. No clock pulses are provided during transmission by the SSC 504, and the receiving device recognizes that a transition in the signaling state on the SDATA line 410 while the SCLK line 412 remains low indicates control signaling.

[0057] Various aspects of the SSC 504 are defined by the RFFE protocol, including the duration of the high portion 506 and the low portion 508 of the SSC 504. The rise time (T R ) and the fall time (T F) is also defined by the protocol. Limits on the frequency of the clock signal sent on the SCLK line 412 may be defined by the design, application, and / or by the specification defining the RFFE protocol. The protocol controller 414 may be configured to send a modified SSC that indicates when a transaction is to be conducted with the single-wire slave device 404. In some examples, the protocol controller 414 may send an extended-length SSC to target the single-wire slave device 404 and / or indicate that the transaction is to be conducted in a single-wire communication mode, wherein the extended-length SSC has a duration that is longer than the duration of the SSC pulse provided according to the RFFE specification. In some implementations, the protocol controller 414 may send a shortened SSC to target the single-wire slave device 404, wherein the shortened SSC includes a pulse having a duration that is less than the duration of the SSC pulse provided according to the RFFE specification. In some instances, the protocol controller 414 may send an SSC with a modified rise time and / or fall time to target the single-wire slave device 404.

[0058] According to certain aspects, the legacy two-wire datagram is identified by a conventional SSC 504 indicating that signaling will be provided on both the SDATA line 410 and the SCLK line 412. A single-wire datagram may be identified by an SSC that includes a unique pulse timing marker on the SDATA line 410. In one example, the unique pulse timing marker is provided when the SSC pulse has a duration (pulse duration) that is guaranteed to exceed the high portion 506 of the conventional SSC 504. In another example, the unique pulse timing marker includes a pulse having a modified rise time (T R ) and fall time (T F ) where the receiver is equipped with slope detection circuitry. In various implementations, the modified SSC for the single-wire datagram provides timing and / or control information that configures the receiver for the modulation scheme used on the SDATA line 410. In one example, the modified SSC for the single-wire datagram indicates the duration of a bit interval and / or the center point of the bit interval. In some examples, signaling in clock cycles following the modified SSC indicates the duration of a bit interval and / or the center point of the bit interval.

[0059] In various implementations, the voltage levels defining the idle state of the bus can be configurable or can vary depending on the implementation. In some examples, the SDATA line 410 and the SCLK line 412 are at a low voltage (or zero volts) in the idle state, while in other examples, the SDATA line 410 and the SCLK line 412 are at a high voltage level in the idle state. The idle state voltage level can define the voltage level of the pulses sent in the pulse width modulated data signal and / or the direction of the transition used to indicate data in the phase modulated data signal. Figure 5 A generalized example of a system 520, 540 that operates in different idle states is included. In the first system 520, a host device 522 communicates with a slave device 524 via a serial bus 526, wherein the idle state is defined by a low voltage level 530, while an activity pulse rises to a higher voltage level 528. The serial bus 526 can be a single-wire bus, a two-wire bus, or a bus with multiple data lines. In some instances, the number of lines in the serial bus 526 is configurable, and the host device 522 and the slave device 524 can have configurable general-purpose input / output (GPIO) pins that can be configured to match the configuration of the serial bus 526. In some specific implementations, the host device 522 and / or the slave device 524 can have a predefined GPIO configuration. In some specific implementations, the host device 522 can be designed with GPIO pads and / or pins that can support operations in single-wire, two-wire, or mixed single-wire / two-wire applications.

[0060] In the second system 540, a host device 542 communicates with a slave device 544 via a serial bus 546, wherein an idle state is defined by a high voltage level 550, and an activity pulse drops to a lower voltage level 548. The serial bus 546 can be a single-wire bus, a dual-wire bus, or a bus with multiple data lines. In some instances, the number of lines in the serial bus 546 is configurable, and the host device 542 and the slave device 544 can have configurable general-purpose input / output (GPIO) pins that can be configured to match the configuration of the serial bus 546. In some specific implementations, the host device 542 and / or the slave device 544 can have a predefined GPIO configuration. In some specific implementations, the host device 542 can be designed with GPIO pads and / or pins that can support the operation in a single-wire, dual-wire, or mixed single-wire / dual-wire application.

[0061] Figure 6Examples of transactions 600 and 620 conducted on a multimode serial bus are illustrated. In the first transaction 600, a two-wire SSC 608 is transmitted by a master device. The master device then transmits a pulse 610 on the SCLK line 604 that indicates and / or distinguishes data bits on the SDATA line 602. In the first transaction 600, a datagram is transmitted that begins with slave device address bits 612, 614, 616, and 618. The duration of the two-wire SSC 608 is shorter than the duration defined for a single-wire SSC, causing the single-wire slave device 404 to ignore the slave address bits 612, 614, 616, and 618 and any subsequent data transmissions until a valid 1-bit SSC 622 is detected. In some implementations, the line interface circuitry in the single-wire slave device 404 provides a detect signal 606 that indicates whether a single-wire SSC has been detected.

[0062] In a second transaction 620, a single-wire SSC 622 is sent by the master device. The master device then gates, suppresses, or otherwise avoids sending pulses in the clock signal sent via the SCLK line 604. The master device sends information on the SDATA line 602. In the second transaction 620, the information may begin with the slave device address bits 624. The two-wire slave device 406 may be configured or adapted to ignore the slave address bits 624 when no pulses are provided on the SCLK line 604. When the single-wire SSC 622 has been detected, the line interface circuit in the single-wire slave device 404 provides a transition 626 to the active state in the detect signal 606.

[0063] A serial bus that couples both single-wire slave devices and dual-wire slave devices to a host device may be referred to as a hybrid bus in the present disclosure. A device coupled to the hybrid bus may implement some combination of hardware and software to dynamically detect the SSC duration and thereby identify the operating mode of an incoming transaction. The operating modes supported by a device coupled to the hybrid bus may include a single-wire mode and a dual-wire mode. A device coupled to the hybrid bus is typically configured to detect the operating mode of each incoming transaction. In one example, a device coupled to the hybrid bus may implement dynamic transaction detection by measuring the duration (width) of each incoming SSC pulse. The duration of the SSC pulse can typically distinguish between a single-wire transaction and a dual-wire transaction. In one example, dynamic detection is implemented using an internal oscillator or clock generator operating at a multiple of the RFFE bus clock frequency. In some instances, the internal oscillator or clock generator outputs a clock signal that oscillates at four times (4x) the RFFE bus clock frequency.

[0064] For the purposes of this disclosure, a two-wire transaction is preceded by an SSC pulse having a duration of one RFFE transmit clock cycle, and a single-wire transaction is preceded by an SSC pulse having a duration of three or more RFFE transmit clock cycles. Single-wire transactions conducted over the RFFE bus may be processed by devices with single-wire capabilities. Two-wire transactions conducted over the RFFE bus may be processed by devices with two-wire capabilities. Transactions may be processed by devices with a unique identifier ("Device ID") that matches the address field in the command sent in the transaction. Devices with a Device ID that does not match the address field in the command sent in the transaction may ignore the ignored command and monitor the data line for the next incoming command.

[0065] Figure 7 is a flow chart 700 illustrating an example of communication in a device coupled to a hybrid bus that couples a single-wire slave device and a two-wire slave device to a host device. For example, Figure 4 The system 400 shown in FIG. 4 includes a single-wire slave device 404 and a two-wire slave device 406. Figure 6 , they can coexist on the same bus. In some instances, one or more of the dual-wire slave devices 406 can be dual-mode devices that can operate as single-wire slave devices. The dual-mode device can be configured to dynamically switch between single-wire mode and dual-wire mode based on the detected SSC structure and configuration. That is, the dual-mode device can be configured to communicate using the dual-wire protocol when a conventional (shorter) SSC is detected, and to communicate using the single-wire protocol when a longer SSC is detected. The dual-mode device can be lockable in the selected or desired operating mode. In one example, the dual-mode device can be locked in single-wire mode in some cases and locked in dual-wire mode in other cases. During system integration and / or during system configuration, the dual-mode device can be locked or unlocked by the host device, application.

[0066] When a dual-mode device detects the start of an SSC, it may enter an idle state 702. In the idle state 702, the hybrid bus is idle, or the dual-mode device is waiting for the hybrid bus to become idle and / or remain idle for a minimum duration. The bus management protocol typically defines a minimum duration for a bus to qualify as an idle condition. The dual-mode device may process the SSC and associated commands, or may effectively discard the command based on the dual-mode device's operating state. The dual-mode device may discard the command by ignoring the SSC and the datagram following the SSC until an idle period is detected on the serial bus. If the dual-mode device is in the unlocked state, the dual-mode device will read the command and respond if addressed by the command. If the dual-mode device is in the dual-wire locked state, the dual-mode device will process the SSC and associated commands when directed to a dual-wire device, and will discard the command when directed to a single-wire device. If the dual mode device is in the single wire locked state, the dual mode device will process the SSC and associated command when directed to a single wire device and will discard the command when directed to a dual wire device.

[0067] Therefore, at block 704, the dual-mode device determines whether it is locked and proceeds to block 706 if unlocked, or to block 720 if locked. At block 706, the unlocked dual-mode device enables its clock generator and a counter, which can be configured to count cycles of an internal clock signal provided by the clock generator. At block 708, the counter increments with each cycle of the internal clock signal. The internal clock signal can have a frequency that is a multiple of the frequency of the transmitter clock in the host device. For the purposes of this description, a threshold counter value "N" is used to distinguish between single-wire SSC and dual-wire SSC. In one example, N can correspond to a counter value that is not reached before the dual-wire SSC terminates. In another example, N can correspond to a counter value that is not exceeded before the dual-wire SSC terminates. In the illustrated example, at block 710, after the SSC has terminated, the counter value is compared to N. If the counter value does not exceed N, the dual-mode device proceeds to block 712, and if the counter value exceeds N, the dual-mode device proceeds to block 714. At block 712, the dual-mode device disables its internal clock and participates in the dual-wire transaction. At block 714, the dual-mode device uses its internal clock for data decoding purposes and participates in the single-wire transaction. After completing or abandoning the transaction, the dual-mode device can re-enter the idle state 702.

[0068] At block 720, the locked dual-mode device determines which mode is locked. When dual-wire lock is enabled, the dual-mode device proceeds to block 722, and when single-wire lock is enabled, the dual-mode device proceeds to block 724. At block 722, the dual-mode device determines whether the incoming command is directed to the dual-wire device based on the duration of the SSC. If the incoming command is directed to the dual-wire device, the dual-mode device processes the transaction at block 728 and discards the incoming command directed to the single-wire device at block 726. At block 724, the dual-mode device determines whether the incoming command is directed to the single-wire device based on the duration of the SSC. If the incoming command is directed to the single-wire device, the dual-mode device processes the transaction at block 728 and discards the incoming command directed to the dual-wire device at block 726. Upon discarding the incoming command at block 726 or processing the transaction at block 728, the dual-mode device may re-enter the idle state 702.

[0069] According to certain aspects of the present disclosure, a host device coupled to a hybrid serial bus can maintain separate addressing schemes for devices configured for two-wire mode transactions and devices configured for single-wire mode transactions. The ability to independently assign addresses for different modes of operating the hybrid bus provides greater flexibility and increases the number of devices that can access the hybrid bus. In some examples, when the hybrid bus is shared by two-wire devices and single-wire RFFE devices, using separate addressing schemes can double the number of addressable devices on a single RFFE bus.

[0070] Figure 8 Certain aspects of addressing on a serial bus configured according to certain aspects of the present disclosure are illustrated. In a first configuration 800, up to 15 RFFE devices configured for two-wire communication can be coupled to a data line 802 and a clock line 804 provided by the serial bus. In a second configuration 820, up to 15 RFFE devices configured for single-wire communication can be coupled to a data line 822 provided by the serial bus. In both configurations 800, 820, each RFFE device is configured with a unique device ID, and the host device can maintain a single table associating each RFFE device with its assigned device ID.

[0071] In a third configuration 840, up to 15 RFFE devices configured for two-wire communication can be coupled to a data line 842 and a clock line 844 provided by the serial bus, and up to 15 RFFE devices configured for single-wire communication can be coupled to the data line 842 of the serial bus. In this configuration 840, the device ID assigned to each RFFE device can be assigned to one other RFFE device operating in a different mode. The host device can maintain a table for each operating mode. One table can associate each RFFE device configured for two-wire operating mode with its assigned device ID, which is unique among the two-wire RFFE devices, and a second table can associate each RFFE device configured for single-wire operating mode with its assigned device ID, which is unique among the single-wire RFFE devices. In one example, two RFFE devices 846, 848 sharing the same device ID can be configured to always operate in different operating modes. The two RFFE devices 846, 848 do not need to have the same assigned device ID.

[0072] In one aspect of the present disclosure, an RFFE device 846 configured for dual-wire operation may also be configured for single-wire operation. A host device may assign two different addresses to the dual-mode RFFE device 846. For example, the dual-mode RFFE device 846 may be configured with a first device ID for dual-wire mode that matches the device ID assigned to the single-wire RFFE device 848, and a second device ID for single-wire mode that is different from the first device ID. In some instances, the dual-mode RFFE device 846 may be assigned two device IDs with the same value, such that the dual-mode RFFE device 846 responds to the same address in both dual-wire transactions and single-wire transactions.

[0073] The flexibility provided to host devices by using different addressing schemes for different operating modes can yield a number of advantages. In one example, a host device maintaining separate addresses for different operating modes in accordance with certain aspects of the present disclosure can designate a specific 4-bit address for use by two-wire devices, single-wire devices, or both. In another example, a single RFFE device can be assigned different priorities in different operating modes. In the latter example, the different priorities can result in different behavior and outcomes of the address arbitration process performed in the different operating modes. In another example, the number of addressable devices that can be coupled to a single RFFE bus can be doubled.

[0074] An RFFE host device configured according to certain aspects of the present disclosure may maintain separate address and input / output (I / O) buffer spaces to manage communications with dual-wire and single-wire RFFE devices sharing a hybrid RFFE bus. Circuitry in the RFFE host device may provide automatic data traffic routing to and from the dual-wire or single-wire buffer spaces on the host based on the communication mode enabled for the hybrid RFFE bus.

[0075] Figure 9 1 illustrates certain features of a host device 900 configured to manage communications over a hybrid serial bus according to certain aspects of the present disclosure. The host device 900 includes a set of two-wire transaction buffers 902 and a set of single-wire transaction buffers 904. The transmit buffer 912a in the two-wire transaction buffer 902 can be configured to provide a data stream to be transmitted in a two-wire communication mode. The receive buffer 912b in the two-wire transaction buffer 902 can be configured to receive and / or assemble data received in a transaction conducted in the two-wire communication mode.

[0076] Mode detection logic 910 can determine the operating mode. Mode detection logic 910 can set the operating mode in response to SSC signaling detected on SDATA 916. In some implementations, mode detection logic 910 can set the operating mode in response to input or commands from a higher level of the communication protocol implemented in the host device. For example, a component of the bus interface can set the two-wire operating mode when it determines that the destination of data provided by an application corresponds to a two-wire device. The two-wire transaction buffer 902 is enabled during the two-wire operating mode, and the path selector circuit 906 is configured to direct data flow between the two-wire transaction buffer 902 and circuitry in the transmit and receive circuitry 908 for two-wire transmission. In some implementations, the transmit and receive circuitry 908 can respond to mode detection logic 910 by, for example, enabling a driver circuit to transmit a clock signal via SCLK 918.

[0077] The transmit buffer 914a in the single-wire transaction buffer 904 may be configured to provide a data stream to be transmitted in the single-wire communication mode. The receive buffer 914b in the single-wire transaction buffer 904 may be configured to receive and / or assemble data received in a transaction conducted in the single-wire communication mode.

[0078] The mode detection logic 910 can set the operating mode in response to SSC signaling detected on SDATA 916. In some implementations, the mode detection logic 910 can set the operating mode in response to input or commands from a higher level of the communication protocol implemented in the host device. For example, a component of the bus interface can set the single-wire operating mode when it determines that the destination of data provided by the application corresponds to a single-wire device. The single-wire transaction buffer 904 is enabled during the single-wire operating mode, and the path selector circuit 906 is configured to direct the flow of data between the single-wire transaction buffer 904 and circuits in the transmit and receive circuit 908 for single-wire transmission. In some implementations, the transmit and receive circuit 908 can respond to the mode detection logic 910 by, for example, disabling the driver circuit to prevent the transmission of the clock signal via SCLK 918.

[0079] In some implementations, the transmit and receive circuitry 908 can include encoding circuitry that can be used in single-wire mode to provide a pulse width modulated data signal, a Manchester encoded data signal, or other encoded signal to be transmitted via SDATA 916 .

[0080] Host device 900 may include multiple address tables 922, 924 that can be used to identify devices coupled to a hybrid serial bus. In the illustrated example, a first address table 922 relates a device ID to a corresponding device that can be configured to operate in dual-wire mode, and a second address table 924 relates a device ID to a corresponding device that can be configured to operate in single-wire mode. One or more devices can be referenced in the two address tables 922, 924. Address tables 922, 924 can be dynamically configured by the host device 900 during manufacturing, system integration, and system initialization by commands issued by an application and / or by the host device 900. The use of multiple address tables 922, 924 can provide secure dual addressing for those devices that can support both dual-wire mode and single-wire mode. In some specific implementations, a dual-mode device can have the same or different device IDs for two modes. A dual-mode device can be configured to dynamically change the operating mode and simultaneously change its active device ID.

[0081] A change in the operating mode of a slave device's bus interface may be triggered by the duration of an SSC detected on the data lines of a hybrid RFFE bus. Slave devices configured according to certain aspects of the present disclosure may be configured to prevent the detection of erroneous SSCs caused by bit sequences transmitted over the data lines of the hybrid RFFE bus in single-wire mode. Slave devices operating in single-wire mode may be configured to ignore apparent SSCs that are not preceded by a bus idle period exceeding a maximum length of zeros when the hybrid bus is operating in dual-wire mode. Devices operating in dual-wire mode are expected to ignore erroneous SSCs when a clock signal is not present on the hybrid RFFE bus.

[0082] Figure 10 1000 is a timing diagram illustrating an erroneous single-line SSC 1012 transmitted on a data line of a serial bus configured according to certain aspects of the present disclosure. In the illustrated example, a host device initially transmits a two-line SSC 1006 on SDATA line 1004 to initiate a two-line transaction. A clock signal is provided on SCLK 1002, which begins after the transmission of two-line SSC 1006. During the transaction, a byte with a value of 0x00 is transmitted. A parity bit 1010 provides odd parity, resulting in a 9-bit transmission 1008 in which SDATA line 1004 is low for at least 8 clock cycles before transitioning to a high state. The 8-bit 0x00 transmission meets or exceeds the minimum duration specified for a pulse on SDATA to qualify as an SSC according to conventional RFFE protocols. Following parity bit 1010, the next 9-bit transmission begins with a bit pattern 1014 consisting of at least two bits with a value of "1" followed by a bit with a value of "0." The combined parity bit 1010 and bit pattern 1014 may be considered or referred to as an erroneous single-line SSC 1012 .

[0083] In some implementations, a single-wire slave device can be configured or adapted according to certain aspects of the present disclosure to ignore transmissions of a single-wire SSC on the SDATA line 1004 that are not preceded by a predefined number of clock cycles. In one example, the number of clock cycles corresponds to a 10-bit transmission interval for a two-wire datagram. The number of clock cycles can be selected based on specific implementation details and other factors. In one example, the number of cycles can be increased or decreased based on the expected accuracy of the internal clock signal used by the single-wire slave device to measure the duration of idle periods or SSC pulses. In another example, the number of cycles can be increased when certain fields can be sent in a two-wire datagram without parity. In another example, the number of cycles can be increased when even parity is used in the two-wire datagram.

[0084] Figure 11 Illustrated are datagrams 1100, 1120 that may conform to or be compatible with conventional RFFE protocols and be sent in both single-wire datagrams and dual-wire datagrams. The datagrams 1100, 1120 represent Write commands that may be sent in datagrams defined by the RFFE protocol.

[0085] First datagram 1100 corresponds to a Register 0 Write command with limited data payload capacity. Datagram 1100 begins with the transmission of a two-bit SSC 1102, followed by a slave address 1104 or other device identifier. In first datagram 1100, slave address 1104 has four bits. Next, an 8-bit command field 1106 is transmitted, with the first bit 1112 set to indicate that the command is a Register 0 Write command. Command field 1106 also carries a seven-bit data payload. In first datagram 1100, command field 1106 may include a parity bit 1108 and may be followed by bus-resident signaling 1110.

[0086] Datagram 1120 represents a generic Write command that can be sent in a datagram defined by the RFFE protocol. Datagram 1120 begins with the transmission of a two-bit SSC 1122, followed by a four-bit slave address 1124 or another device identifier. Next, an 8-bit command code 1126 is sent. Command code 1126 may be followed by a parity bit 1128. An address field 1130 is sent, which may be 8 bits in length or 11 bits in length (for extended register write commands). Address field 1130 may be followed by a parity bit 1132. One or more data frames 1134 may be sent, each with an accompanying parity bit 1136. A bus presence condition (BPC 1138) terminates datagram 1120. Each of data frames 1134 may include an 8-bit byte with parity 1136.

[0087] Examples of Processing Circuits and Methods

[0088] Figure 1212 is a diagram illustrating an example of a hardware implementation of device 1200. In some examples, device 1200 can perform one or more functions disclosed herein. According to various aspects of the present disclosure, processing circuitry 1202 can be used to implement an element, any portion of an element, or any combination of elements as disclosed herein. Processing circuitry 1202 may include one or more processors 1204 controlled by some combination of hardware modules and software modules. Examples of processors 1204 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic components, discrete hardware circuits, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. One or more processors 1204 may include special-purpose processors that perform specific functions and may be configured, enhanced, or controlled by one of software modules 1216. One or more processors 1204 may be configured by a combination of software modules 1216 loaded during initialization, and may also be configured by loading or unloading one or more software modules 1216 during operation.

[0089] In the illustrated example, processing circuit 1202 may be implemented using a bus architecture, generally represented by bus 1210. Depending on the specific application of processing circuit 1202 and the overall design constraints, bus 1210 may include any number of interconnecting buses and bridges. Bus 1210 links various circuits together, including one or more processors 1204 and storage 1206. Storage 1206 may include memory devices and mass storage devices and may be referred to herein as computer-readable media and / or processor-readable media. Bus 1210 may also link various other circuits, such as timing sources, timers, peripherals, voltage regulators, and power management circuits. Bus interface 1208 may provide an interface between bus 1210 and one or more transceivers 1212a, 1212b. A transceiver 1212a, 1212b may be provided for each networking technology supported by the processing circuit. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in transceivers 1212a, 1212b. Each transceiver 1212a, 1212b provides a means for communicating with various other devices via a transmission medium. In one example, transceiver 1212a can be used to couple device 1200 to a multi-wire bus. In another example, transceiver 1212b can be used to connect device 1200 to a radio access network. Depending on the nature of device 1200, a user interface 1218 (e.g., a keypad, display, speaker, microphone, joystick) may also be provided and communicatively coupled to bus 1210 directly or via bus interface 1208.

[0090] The processor 1204 may be responsible for managing the bus 1210 and for general processing, which may include executing software stored in a computer-readable medium, which may include a storage device 1206. In this regard, the processing circuit 1202 (including the processor 1204) may be used to implement any of the methods, functions, and techniques disclosed herein. The storage device 1206 may be used to store data that is manipulated by the processor 1204 when executing the software, and the software may be configured to implement any of the methods disclosed herein.

[0091] One or more processors 1204 in the processing circuit 1202 can execute software. Software should be interpreted broadly to mean instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. The software may reside in computer-readable form in the storage device 1206 or in an external computer-readable medium. The external computer-readable medium and / or the storage device 1206 may include non-transitory computer-readable media. For example, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips), optical disks (e.g., compact disks (CDs) or digital versatile disks (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM, including EEPROM), registers, removable disks, and any other suitable medium for storing software and / or instructions that can be accessed and read by a computer. Computer-readable media and / or storage 1206 may also include, for example, carrier waves, transmission lines, and any other suitable medium for transmitting software and / or instructions that can be accessed and read by a computer. Computer-readable media and / or storage 1206 may reside in processing circuit 1202, in processor 1204, external to processing circuit 1202, or distributed across multiple entities including processing circuit 1202. Computer-readable media and / or storage 1206 may be embodied in a computer program product. For example, a computer program product may include a computer-readable medium in packaging material. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.

[0092] Storage device 1206 may maintain software maintained and / or organized in loadable code segments, modules, applications, programs, and the like, which may be referred to herein as software modules 1216. Each of software modules 1216 may include instructions and data that, when installed or loaded into processing circuitry 1202 and executed by one or more processors 1204, facilitates a runtime image 1214 that controls the operation of one or more processors 1204. Certain instructions, when executed, may cause processing circuitry 1202 to perform functions according to certain methods, algorithms, and processes described herein.

[0093] Some of the software modules 1216 may be loaded during initialization of the processing circuit 1202, and these software modules 1216 may configure the processing circuit 1202 to perform the various functions disclosed herein. For example, some of the software modules 1216 may configure the internal devices and / or logic circuits 1222 of the processor 1204 and may manage access to external devices such as the transceivers 1212a, 1212b, the bus interface 1208, the user interface 1218, timers, math coprocessors, and the like. The software modules 1216 may include a control program and / or operating system that interacts with interrupt handlers and device drivers and controls access to various resources provided by the processing circuit 1202. Resources may include memory, processing time, access to the transceivers 1212a, 1212b, the user interface 1218, and the like.

[0094] The one or more processors 1204 of the processing circuitry 1202 can be multifunctional, whereby some of the software modules 1216 are loaded and configured to perform different functions or different instances of the same function. The one or more processors 1204 can also be adapted to manage background tasks initiated in response to inputs from, for example, the user interface 1218, the transceivers 1212a, 1212b, and device drivers. To support the execution of multiple functions, the one or more processors 1204 can be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks serviced by the one or more processors 1204 as needed or desired. In one example, the multitasking environment can be implemented using a time-sharing program 1220 that transfers control of the processors 1204 between different tasks, whereby each task returns control of the one or more processors 1204 to the time-sharing program 1220 upon completion of any pending operations and / or in response to inputs such as interrupts. When a task has control of the one or more processors 1204, the processing circuitry is effectively dedicated to the purpose addressed by the function associated with the control task. The time sharing program 1220 may include an operating system, a main loop that transmits control on a cycle basis, a function that allocates control of one or more processors 1204 based on functional prioritization, and / or an interrupt-driven main loop that responds to external events by providing control of one or more processors 1204 to processing functions.

[0095] The method for optimizing virtual GPIO latency may include the act of parsing various input sources, including sources of GPIO signal states, parameters, and / or messages to be sent. The input sources may include hardware events, configuration data, mask parameters, and register addresses. A packet-specific latency estimator may be used to estimate the latency of the corresponding packet type based on the parsed parameters. The packet type to be sent may be selected based on the minimum latency calculated or determined for the available packet types. The selected packet type may be identified using a command code, which may be provided to the packetizer along with the payload to be sent. The command code may also reflect the protocol to be used to send the payload. In some implementations, the physical link used to send the payload may operate according to different protocols or different variants of one or more protocols. The protocol to be used to send the payload may be selected based on the latency associated with the various available protocols or protocol variants.

[0096] Figure 13 1300 is a flow chart of a method that may be performed by a host device coupled to a serial bus. One or more single-wire slave devices and one or more two-wire slave devices may be coupled to the serial bus.

[0097] At block 1302, a host device may configure each slave device in a first plurality of slave devices with a device identifier that is unique within the first plurality of slave devices. At block 1304, the host device may configure each slave device in a second plurality of slave devices with a device identifier that is unique within the second plurality of slave devices. At block 1306, the host device may transmit a sequence start condition via a data line of a serial bus, the sequence start condition indicating whether clock pulses will be provided in a clock signal on a clock line of the serial bus concurrently with a transaction initiated by the sequence start condition. At block 1308, when the sequence start condition indicates that clock pulses will be provided concurrently in the clock signal, the host device may transmit a first datagram via the serial bus to one of the first plurality of slave devices using the device identifier associated with the first plurality of slave devices. At block 1310, when the sequence start condition indicates that no clock pulses will be provided concurrently in the clock signal, the host device may transmit a second datagram via the serial bus to one of the second plurality of slave devices using the device identifier associated with the second plurality of slave devices. In some instances, a slave device in the first plurality of slave devices and a slave device in the second plurality of slave devices have the same device identifier.

[0098] In some examples, the dual-mode slave device is included in a first plurality of slave devices and a second plurality of slave devices. The host device may configure a first device identifier for the dual-mode slave device, the first device identifier being associated with the first plurality of slave devices and being used by the dual-mode slave device to communicate over the serial bus when a sequence start condition indicates that a clock pulse will be provided concurrently in the clock signal. The host device may configure a second device identifier for the dual-mode slave device, the second device identifier being associated with the second plurality of slave devices and being used by the dual-mode slave device to communicate over the serial bus when a sequence start condition indicates that no clock pulse will be provided concurrently in the clock signal. In some examples, the first device identifier has the same value as the second device identifier. In some examples, the first device identifier and the second device identifier have different values.

[0099] In some implementations, the sequence start condition has a first duration when indicating that clock pulses are to be provided concurrently in the clock signal, and has a second duration longer than the first duration when indicating that no clock pulses are to be provided concurrently in the clock signal.

[0100] In some implementations, the master device can configure each slave device in the second plurality of slave devices to ignore a sequence start condition unless the sequence start condition is preceded by an idle period having a minimum duration calculated based on a transmission time of a data byte transmitted over the serial bus.

[0101] Figure 14 1408, and a processor 1416. FIGURE 1409 is a diagram illustrating a simplified example of a hardware implementation of an apparatus 1400 employing a processing circuit 1402. The processing circuit typically has a controller or processor 1416, which may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. Processing circuit 1402 may be implemented using a bus architecture, generally represented by bus 1410. Bus 1410 may include any number of interconnecting buses and bridges, depending on the specific application of processing circuit 1402 and the overall design constraints. Bus 1410 links together various circuits, including one or more processors and / or hardware modules, represented by controller or processor 1416, modules or circuits 1404, 1406, and 1408, and processor-readable storage media 1418. One or more physical layer circuits and / or modules 1414 may be provided to support communications via a communication link implemented using a multi-wire bus 1412, communications via an antenna or antenna array 1422 (e.g., to a radio access network), and the like. The bus 1410 may also link various other circuits such as timing sources, peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further.

[0102] Processor 1416 is responsible for general processing, including executing software, code, and / or instructions stored on processor-readable storage medium 1418. The processor-readable storage medium may include non-transitory storage media. When executed by processor 1416, the software causes processing circuit 1402 to perform the various functions described above for any particular device. The processor-readable storage medium may be used to store data manipulated by processor 1416 when executing the software. Processing circuit 1402 also includes at least one of modules 1404, 1406, and 1408. Modules 1404, 1406, and 1408 may be software modules running on processor 1416, resident / stored in processor-readable storage medium 1418, one or more hardware modules coupled to processor 1416, or some combination thereof. Modules 1404, 1406, and 1408 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0103] In one configuration, the apparatus 1400 includes a module and / or circuit 1404 adapted to provide an SSC indicating whether a single-wire transaction or a two-wire transaction will be conducted over the serial bus. The apparatus 1400 may include a module and / or circuit 1406 adapted to encode, decode, transmit, and receive data, and a module and / or circuit 1408 adapted to manage a plurality of address tables that maintain device IDs and enable device IDs to be assigned to single-wire slave devices and two-wire slave devices.

[0104] In one example, the apparatus 1400 includes physical layer circuitry and / or modules 1414 that implement interface circuitry adapted to couple the apparatus 1400 to two lines of a serial bus. Apparatus 1400 may have a protocol controller configured to configure each slave device in a first plurality of slave devices with a device identifier that is unique within the first plurality of slave devices, and to configure each slave device in a second plurality of slave devices with a device identifier that is unique within the second plurality of slave devices; to send a sequence start condition over a data line of the serial bus, the sequence start condition indicating whether a clock pulse will be provided in a clock signal on a clock line of the serial bus concurrently with a transaction initiated by the sequence start condition; to send a first datagram over the serial bus to one of the slave devices in the first plurality of slave devices using the device identifier associated with the first plurality of slave devices when the sequence start condition indicates that a clock pulse will be provided concurrently in the clock signal; and to send a second datagram over the serial bus to one of the slave devices in the second plurality of slave devices using the device identifier associated with the second plurality of slave devices when the sequence start condition indicates that no clock pulse will be provided concurrently in the clock signal.

[0105] In one example, a slave device in the first plurality of slave devices and a slave device in the second plurality of slave devices have the same device identifier.

[0106] In some examples, the dual-mode slave device is included in a first plurality of slave devices and a second plurality of slave devices. The protocol controller may also be configured to: configure a first device identifier for the dual-mode slave device, the first device identifier being associated with the first plurality of slave devices and used by the dual-mode slave device to communicate over the serial bus when a sequence start condition indicates that a clock pulse is to be provided concurrently in the clock signal; and configure a second device identifier for the dual-mode slave device, the second device identifier being associated with the second plurality of slave devices and used by the dual-mode slave device to communicate over the serial bus when the sequence start condition indicates that no clock pulse is to be provided concurrently in the clock signal. The first device identifier may have the same value as the second device identifier, or may have a different value.

[0107] In some implementations, the sequence start condition has a first duration when indicating that clock pulses are to be provided concurrently in the clock signal, and has a second duration longer than the first duration when indicating that no clock pulses are to be provided concurrently in the clock signal.

[0108] In some implementations, the protocol controller is further configured to configure each slave device in the second plurality of slave devices to ignore a sequence start condition unless the sequence start condition is preceded by an idle period having a minimum duration calculated based on a transmission time of a data byte transmitted over the serial bus.

[0109] The processor-readable storage medium 1418 may include a transitory or non-transitory storage device configured to store code, instructions, and / or parameters for implementing one or more methods or processes disclosed herein. The processor-readable storage medium 1418 may include code for: configuring each slave device in a first plurality of slave devices with a device identifier that is unique within the first plurality of slave devices; configuring each slave device in a second plurality of slave devices with a device identifier that is unique within the second plurality of slave devices; sending a sequence start condition over a data line of a serial bus, the sequence start condition indicating whether a clock pulse will be provided in a clock signal on a clock line of the serial bus concurrently with a transaction initiated by the sequence start condition; when the sequence start condition indicates that a clock pulse will be provided in the clock signal concurrently, sending a first datagram over the serial bus to one of the first plurality of slave devices using the device identifier associated with the first plurality of slave devices; and when the sequence start condition indicates that no clock pulse will be provided in the clock signal concurrently, sending a second datagram over the serial bus to one of the second plurality of slave devices using the device identifier associated with the second plurality of slave devices.

[0110] In some embodiments, the processor-readable storage medium 1418 includes code for: configuring a first device identifier to the dual-mode slave device, the first device identifier being associated with a first plurality of slave devices and being used by the dual-mode slave device to communicate over the serial bus when a sequence start condition indicates that clock pulses will be provided concurrently in the clock signal; and configuring a second device identifier to the dual-mode slave device, the second device identifier being associated with a second plurality of slave devices and being used by the dual-mode slave device to communicate over the serial bus when the sequence start condition indicates that no clock pulses will be provided concurrently in the clock signal.

[0111] In some implementations, the processor-readable storage medium 1418 includes code for configuring each slave device in the second plurality of slave devices to ignore a sequence start condition unless the sequence start condition is preceded by an idle period having a minimum duration calculated based on a transmit time of a data byte transmitted over the serial bus.

[0112] Figure 151500 is a flow chart of a method that can be performed by a dual-mode slave device coupled to a serial bus. At least one host device is coupled to the serial bus. One or more single-wire slave devices and one or more dual-wire slave devices can be coupled to the serial bus.

[0113] At block 1502, a dual-mode slave device may receive a first sequence start condition from a data line of a serial bus, the first sequence start condition indicating a first operating mode of the serial bus, wherein a first datagram transmitted after the first sequence start condition is transmitted concurrently with a clock pulse in a clock signal transmitted on a clock line of the serial bus. At block 1504, the dual-mode slave device may receive a second sequence start condition from the data line, the second sequence start condition indicating a second operating mode of the serial bus, wherein a second datagram transmitted after the second sequence start condition is transmitted with embedded clock information in the data signal. At block 1506, when a first command included in the first datagram is transmitted to an address corresponding to a first device identifier associated with the slave device, the dual-mode slave device may respond to the first command. At block 1508, when a second command included in the second datagram is transmitted to an address corresponding to a second device identifier associated with the slave device, the dual-mode slave device may respond to the second command. In one example, the first device identifier has the same value as the second device identifier. In another example, the first device identifier and the second device identifier have different values.

[0114] In some implementations, the dual-mode slave device can ignore the third sequence start condition when the third sequence start condition is preceded by an idle period having a duration less than a transmission time of a data byte transmitted over the serial bus.

[0115] In some implementations, the dual-mode slave device can receive a lock command that restricts the slave device to the first operating mode and can discard a third command included in a third datagram sent when the serial bus operates in the second operating mode.

[0116] In some implementations, the dual-mode slave device can receive a lock command that restricts the slave device to the second operating mode and can discard a fourth command included in a fourth datagram sent when the serial bus operates in the first operating mode.

[0117] In some implementations, the sequence start condition has a first duration when indicating that clock pulses are to be provided concurrently in the clock signal, and has a second duration longer than the first duration when indicating that no clock pulses are to be provided concurrently in the clock signal.

[0118] Figure 1616 is a diagram illustrating a simplified example of a hardware implementation of an apparatus 1600 employing processing circuitry 1602. The processing circuitry typically has a controller or processor 1616, which may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. Processing circuitry 1602 may be implemented using a bus architecture, generally represented by bus 1610. Bus 1610 may include any number of interconnecting buses and bridges, depending on the specific application of processing circuitry 1602 and the overall design constraints. Bus 1610 links together various circuits, including one or more processors and / or hardware modules, represented by controller or processor 1616, modules or circuits 1604, 1606, and 1608, and processor-readable storage media 1618. One or more physical layer circuits and / or modules 1614 may be provided to support communications links implemented using multi-wire bus 1612, communications via antenna or antenna array 1622 (e.g., to a radio access network), and the like. The bus 1610 may also link various other circuits such as timing sources, peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further.

[0119] Processor 1616 is responsible for general processing, including executing software, code, and / or instructions stored on processor-readable storage medium 1618. The processor-readable storage medium may include non-transitory storage media. When executed by processor 1616, the software causes processing circuit 1602 to perform the various functions described above for any particular device. The processor-readable storage medium may be used to store data manipulated by processor 1616 when executing the software. Processing circuit 1602 also includes at least one of modules 1604, 1606, and 1608. Modules 1604, 1606, and 1608 may be software modules running on processor 1616, resident / stored on processor-readable storage medium 1618, one or more hardware modules coupled to processor 1616, or some combination thereof. Modules 1604, 1606, and 1608 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0120] In one configuration, the apparatus 1600 includes a module and / or circuit 1604 adapted to detect an SSC that indicates whether a single-wire transaction or a dual-wire transaction will be conducted over the serial bus based on the duration of the SSC. The apparatus 1600 may include a module and / or circuit 1606 adapted to manage addresses used when participating in single-wire transactions and dual-wire transactions, and a module and / or circuit 1608 adapted to determine an operating mode (including single-wire and dual-wire operating modes).

[0121] In one example, apparatus 1600 includes physical layer circuitry and / or modules 1614 implementing interface circuitry adapted to couple apparatus 1600 to a serial bus. Apparatus 1600 may include a protocol controller. Processor 1616 may be configured to receive a first sequence start condition from a data line of the serial bus, the first sequence start condition indicating a first operating mode of the serial bus, in which a first datagram transmitted after the first sequence start condition is transmitted concurrently with a clock pulse in a clock signal transmitted on a clock line of the serial bus; receive a second sequence start condition from the data line, the second sequence start condition indicating a second operating mode of the serial bus, in which a second datagram transmitted after the second sequence start condition is transmitted with embedded clock information in the data signal; respond to a first command included in the first datagram when the first command is sent to an address corresponding to a first device identifier associated with the slave device; and respond to a second command included in the second datagram when the second command is sent to an address corresponding to a second device identifier associated with the slave device. The first device identifier may have the same value as the second device identifier, or the first device identifier and the second device identifier may have different values.

[0122] In some implementations, the processor 1616 is further configured to ignore the third sequence start condition when the third sequence start condition is preceded by an idle period, the idle period having a duration less than a transmission time of a data byte transmitted over the serial bus.

[0123] In some implementations, the processor 1616 is further configured to receive a lock command to restrict the slave device to the first operating mode; and discard a third command included in a third datagram sent when the serial bus operates in the second operating mode.

[0124] In some implementations, the processor 1616 is further configured to receive a lock command to restrict the slave device to the second operating mode; and discard a fourth command included in a fourth datagram sent when the serial bus operates in the first operating mode.

[0125] In some implementations, the sequence start condition has a first duration when indicating that clock pulses are to be provided concurrently in the clock signal, and has a second duration longer than the first duration when indicating that no clock pulses are to be provided concurrently in the clock signal.

[0126] The processor-readable storage medium 1618 may include a transient or non-transitory storage device configured to store code, instructions, and / or parameters for implementing one or more methods or processes disclosed herein. The processor-readable storage medium 1618 may include code for: receiving a first sequence start condition from a data line of a serial bus, the first sequence start condition indicating a first operating mode of the serial bus, in which a first datagram sent after the first sequence start condition is sent concurrently with a clock pulse in a clock signal sent on a clock line of the serial bus; receiving a second sequence start condition from the data line, the second sequence start condition indicating a second operating mode of the serial bus, in which a second datagram sent after the second sequence start condition is sent with embedded clock information in the data signal; responding to a first command included in the first datagram when the first command is sent to an address corresponding to a first device identifier associated with the slave device; and responding to a second command included in the second datagram when the second command is sent to an address corresponding to a second device identifier associated with the slave device.

[0127] In some implementations, the processor-readable storage medium 1618 includes code for ignoring the third sequence start condition when the third sequence start condition is preceded by an idle period having a duration less than a transmission time of a data byte transmitted over the serial bus.

[0128] In some implementations, the processor-readable storage medium 1618 includes code for: receiving a lock command to restrict the slave device to a first operating mode; and discarding a third command included in a third datagram sent when the serial bus operates in a second operating mode.

[0129] In some implementations, the processor-readable storage medium 1618 includes code for: receiving a lock command to restrict the slave device to a second operating mode; and discarding a fourth command included in a fourth datagram sent when the serial bus operates in the first operating mode.

[0130] It should be understood that the specific order or hierarchy of steps in the disclosed processes is illustrative of exemplary methods. It should be understood that the specific order or hierarchy of steps in these processes may be rearranged based on design preferences. Furthermore, some steps may be combined or omitted. The accompanying method claims present elements of various steps in a sample order and are not meant to be limited to the specific order or hierarchy presented.

[0131] Some specific implementation examples are described in the following numbered clauses:

[0132] 1. A method for performing data communication at a host device, the method comprising: configuring each slave device in a first plurality of slave devices with a device identifier that is unique within the first plurality of slave devices; configuring each slave device in a second plurality of slave devices with a device identifier that is unique within the second plurality of slave devices; sending a sequence start condition over a data line of a serial bus, the sequence start condition indicating whether a clock pulse will be provided in a clock signal on a clock line of the serial bus concurrently with a transaction initiated by the sequence start condition; when the sequence start condition indicates that the clock pulse will be provided concurrently in the clock signal, sending a first datagram to one of the first plurality of slave devices over the serial bus using the device identifier associated with the first plurality of slave devices; and when the sequence start condition indicates that no clock pulse will be provided concurrently in the clock signal, sending a second datagram to one of the second plurality of slave devices over the serial bus using the device identifier associated with the second plurality of slave devices.

[0133] 2. The method of clause 1, wherein a slave device in the first plurality of slave devices and a slave device in the second plurality of slave devices have the same device identifier.

[0134] 3. The method of clause 1 or clause 2, wherein a dual-mode slave device is included in the first plurality of slave devices and in the second plurality of slave devices.

[0135] 4. The method as described in clause 3 further includes: configuring a first device identifier to the dual-mode slave device, the first device identifier being associated with the first plurality of slave devices and being used by the dual-mode slave device to communicate through the serial bus when the sequence start condition indicates that the clock pulses will be provided concurrently in the clock signal; and configuring a second device identifier to the dual-mode slave device, the second device identifier being associated with the second plurality of slave devices and being used by the dual-mode slave device to communicate through the serial bus when the sequence start condition indicates that no clock pulses will be provided concurrently in the clock signal.

[0136] 5. The method of clause 4, wherein the first device identifier has the same value as the second device identifier.

[0137] 6. The method of clause 4, wherein the first device identifier and the second device identifier have different values.

[0138] 7. A method as described in any of clauses 1 to 6, wherein the sequence start condition has a first duration when indicating that the clock pulses will be provided concurrently in the clock signal, and has a second duration longer than the first duration when indicating that no clock pulses will be provided concurrently in the clock signal.

[0139] 8. A method as described in any one of clauses 1 to 7, further comprising: configuring each slave device in the second plurality of slave devices to ignore the sequence start condition unless the sequence start condition is preceded by an idle period, the idle period having a minimum duration calculated based on the transmission time of data bytes sent through the serial bus.

[0140] 9. A data communication device, comprising: an interface circuit adapted to couple the data communication device to two lines of a serial bus; and a protocol controller configured to: configure a device identifier unique within a first plurality of slave devices to each slave device in a first plurality of slave devices; and configure a device identifier unique within a second plurality of slave devices to each slave device in a second plurality of slave devices;

[0141] sending a sequence start condition over a data line of the serial bus, the sequence start condition indicating whether a clock pulse will be provided in a clock signal on a clock line of the serial bus concurrently with a transaction initiated by the sequence start condition; sending a first datagram over the serial bus to one of the first plurality of slave devices using a device identifier associated with the first plurality of slave devices when the sequence start condition indicates that the clock pulse will be provided concurrently in the clock signal; and sending a second datagram over the serial bus to one of the second plurality of slave devices using a device identifier associated with the second plurality of slave devices when the sequence start condition indicates that no clock pulse will be provided concurrently in the clock signal.

[0142] 10. The data communication apparatus of clause 9, wherein a slave device in the first plurality of slave devices and a slave device in the second plurality of slave devices have the same device identifier.

[0143] 11. The data communication apparatus of clause 9 or clause 10, wherein dual-mode slave devices are included in the first plurality of slave devices and in the second plurality of slave devices.

[0144] 12. A data communication device as described in claim 11, wherein the protocol controller is further configured to: configure a first device identifier to the dual-mode slave device, the first device identifier being associated with the first plurality of slave devices and being used by the dual-mode slave device to communicate over the serial bus when the sequence start condition indicates that the clock pulses are to be provided concurrently in the clock signal; and configure a second device identifier to the dual-mode slave device, the second device identifier being associated with the second plurality of slave devices and being used by the dual-mode slave device to communicate during the sequence start condition.

[0145] A start condition indicates that communication over the serial bus is to proceed when no clock pulses are to be concurrently provided in the clock signal.

[0146] 13. The data communication apparatus of clause 12, wherein the first device identifier has the same value as the second device identifier.

[0147] 14. The data communication apparatus of clause 12, wherein the first device identifier and the second device identifier have different values.

[0148] 15. A data communication device as described in any of clauses 9 to 14, wherein the sequence start condition has a first duration when indicating that the clock pulses will be provided concurrently in the clock signal, and has a second duration longer than the first duration when indicating that no clock pulses will be provided concurrently in the clock signal.

[0149] 16. A data communication device as described in any one of clauses 9 to 15, wherein the protocol controller is further configured to: configure each slave device in the second plurality of slave devices to ignore the sequence start condition unless the sequence start condition is preceded by an idle period, the idle period having a minimum duration calculated based on the transmission time of the data bytes sent through the serial bus.

[0150] 17. A method for data communication at a slave device, the method comprising: receiving a first sequence start condition from a data line of a serial bus, the first sequence start condition indicating a first operating mode of the serial bus, in which a first datagram sent after the first sequence start condition will be sent concurrently with a clock pulse in a clock signal sent on a clock line of the serial bus; receiving a second sequence start condition from the data line, the second sequence start condition indicating a second operating mode of the serial bus, in which a second datagram sent after the second sequence start condition will be sent together with embedded clock information in the data signal; responding to the first command when a first command included in the first datagram is sent to an address corresponding to a first device identifier associated with the slave device; and responding to the second command when a second command included in the second datagram is sent to an address corresponding to a second device identifier associated with the slave device.

[0151] 18. The method of clause 17, wherein the first device identifier has the same value as the second device identifier.

[0152] 19. The method of clause 17, wherein the first device identifier and the second device identifier have different values.

[0153] 20. The method of any of clauses 17 to 19, further comprising ignoring a third sequence start condition when the third sequence start condition is preceded by an idle period, the idle period having a duration less than a transmission time of a data byte transmitted over the serial bus.

[0154] 21. The method of any one of clauses 17 to 20, further comprising: receiving a lock command to restrict the slave device to the first operating mode; and discarding a third command included in a third datagram sent when the serial bus operates in the second operating mode.

[0155] 22. The method of any one of clauses 17 to 20, further comprising: receiving a lock command to restrict the slave device to the second operating mode; and discarding a fourth command included in a fourth datagram sent when the serial bus operates in the first operating mode.

[0156] 23. The method of any of clauses 17 to 22, wherein the first sequence start condition has a first duration and the second sequence start condition has a second duration that is longer than the first duration.

[0157] 24. An apparatus, comprising: an interface circuit adapted to couple the apparatus to a serial bus; and a processor configured to: receive a first sequence start condition from a data line of the serial bus, the first sequence start condition indicating a first operating mode of the serial bus, in which a first datagram sent after the first sequence start condition will be sent concurrently with a clock pulse in a clock signal sent on a clock line of the serial bus; receive a second sequence start condition from the data line, the second sequence start condition indicating a second operating mode of the serial bus, in which a second datagram sent after the second sequence start condition will be sent together with embedded clock information in the data signal; respond to the first command when a first command included in the first datagram is sent to an address corresponding to a first device identifier associated with the apparatus; and respond to the second command when a second command included in the second datagram is sent to an address corresponding to a second device identifier associated with the apparatus.

[0158] 25. The apparatus of clause 24, wherein the first device identifier has the same value as the second device identifier.

[0159] 26. The apparatus of clause 24, wherein the first device identifier and the second device identifier have different values.

[0160] 27. An apparatus as described in any of clauses 24 to 26, wherein the processor is further configured to: ignore the third sequence start condition when there is an idle period before the third sequence start condition, the idle period having a duration less than the transmission time of a data byte sent over the serial bus.

[0161] 28. An apparatus as described in any of clauses 24 to 27, wherein the processor is further configured to: receive a lock command to restrict the apparatus to the first operating mode; and discard a third command included in a third datagram sent when the serial bus operates in the second operating mode.

[0162] 29. An apparatus as described in any of clauses 24 to 27, wherein the processor is further configured to: receive a lock command to restrict the apparatus to the second operating mode; and discard a fourth command included in a fourth datagram sent when the serial bus operates in the first operating mode.

[0163] 30. The apparatus of any of clauses 24 to 29, wherein the first sequence start condition has a first duration and the second sequence start condition has a second duration that is longer than the first duration.

[0164] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but rather to the full scope consistent with the language claims, wherein elements mentioned in the singular are not intended to mean "one and only one" unless specifically stated otherwise, but rather "one or more". Unless otherwise specified, the term "some" refers to one or more. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or will later be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly stated in the claims. No claim element can be interpreted as a component plus function unless the element is explicitly stated using the phrase "component for..."

Claims

1. A method for performing data communication at a host device, the method comprising: configuring each slave device in a first plurality of slave devices with a device identifier that is unique within the first plurality of slave devices; configuring each slave device in a second plurality of slave devices with a device identifier that is unique within the second plurality of slave devices; sending a sequence start condition over a data line of a serial bus, the sequence start condition indicating whether clock pulses are to be provided in a clock signal on a clock line of the serial bus concurrently with a transaction initiated by the sequence start condition; sending a first datagram to a slave device of the first plurality of slave devices over the serial bus using a device identifier associated with the first plurality of slave devices when the sequence start condition indicates that the clock pulses are to be provided concurrently in the clock signal; as well as When the sequence start condition indicates that no clock pulses are to be concurrently provided in the clock signal, a second datagram is sent over the serial bus to a slave device of the second plurality of slave devices using a device identifier associated with the second plurality of slave devices. 2 . The method of claim 1 , wherein a slave device in the first plurality of slave devices and a slave device in the second plurality of slave devices have the same device identifier. 3 . The method of claim 1 , wherein a dual-mode slave device is included in the first plurality of slave devices and in the second plurality of slave devices.

4. The method according to claim 3, further comprising: configuring a first device identifier to the dual-mode slave device, the first device identifier being associated with the first plurality of slave devices and used by the dual-mode slave device to communicate over the serial bus when the sequence start condition indicates that the clock pulses are to be provided concurrently in the clock signal; as well as The dual mode slave device is configured with a second device identifier associated with the second plurality of slave devices and used by the dual mode slave device to communicate over the serial bus when the sequence start condition indicates that no clock pulses are to be concurrently provided in the clock signal. The method of claim 4 , wherein the first device identifier has the same value as the second device identifier. The method of claim 4 , wherein the first device identifier and the second device identifier have different values.

7. The method of claim 1 , wherein the sequence start condition has a first duration when indicating that the clock pulses are to be provided concurrently in the clock signal, and has a second duration longer than the first duration when indicating that no clock pulses are to be provided concurrently in the clock signal.

8. The method according to claim 1, further comprising: Each slave device in the second plurality of slave devices is configured to ignore the sequence start condition unless the sequence start condition is preceded by an idle period having a minimum duration calculated based on a transmission time of a data byte transmitted over the serial bus.

9. A data communication device, comprising: an interface circuit adapted to couple the data communication device to two lines of a serial bus; and A protocol controller, the protocol controller being configured to: configuring each slave device in a first plurality of slave devices with a device identifier that is unique within the first plurality of slave devices; configuring each slave device in a second plurality of slave devices with a device identifier that is unique within the second plurality of slave devices; sending a sequence start condition over a data line of the serial bus, the sequence start condition indicating whether clock pulses are to be provided in a clock signal on a clock line of the serial bus concurrently with a transaction initiated by the sequence start condition; sending a first datagram to a slave device of the first plurality of slave devices over the serial bus using a device identifier associated with the first plurality of slave devices when the sequence start condition indicates that the clock pulses are to be provided concurrently in the clock signal; as well as When the sequence start condition indicates that no clock pulses are to be concurrently provided in the clock signal, a second datagram is sent over the serial bus to a slave device of the second plurality of slave devices using a device identifier associated with the second plurality of slave devices. 10 . The data communication apparatus of claim 9 , wherein a slave device in the first plurality of slave devices and a slave device in the second plurality of slave devices have the same device identifier.

11. The data communication apparatus according to claim 9, wherein dual-mode slave devices are included in the first plurality of slave devices and in the second plurality of slave devices.

12. The data communication device according to claim 11, wherein the protocol controller is further configured to: configuring the dual-mode slave device with a first device identifier, the first device identifier being associated with the first plurality of slave devices and used by the dual-mode slave device to communicate over the serial bus when the sequence start condition indicates that the clock pulses are to be provided concurrently in the clock signal; and The dual mode slave device is configured with a second device identifier associated with the second plurality of slave devices and used by the dual mode slave device to communicate over the serial bus when the sequence start condition indicates that no clock pulses are to be concurrently provided in the clock signal. 13 . The data communication apparatus according to claim 12 , wherein the first device identifier has the same value as the second device identifier. The data communication apparatus according to claim 12 , wherein the first device identifier and the second device identifier have different values.

15. The data communication device of claim 9, wherein the sequence start condition has a first duration when indicating that the clock pulses are to be provided concurrently in the clock signal, and has a second duration longer than the first duration when indicating that no clock pulses are to be provided concurrently in the clock signal.

16. The data communication device according to claim 9, wherein the protocol controller is further configured to: Each slave device in the second plurality of slave devices is configured to ignore the sequence start condition unless the sequence start condition is preceded by an idle period having a minimum duration calculated based on a transmission time of a data byte transmitted over the serial bus.

17. A method for performing data communication at a slave device, the method comprising: receiving a first sequence start condition from a data line of a serial bus, the first sequence start condition indicating a first operating mode of the serial bus in which a first datagram sent after the first sequence start condition is to be sent concurrently with a clock pulse in a clock signal sent on a clock line of the serial bus; receiving a second sequence start condition from the data line, the second sequence start condition indicating a second operating mode of the serial bus, wherein in the second operating mode, a second datagram sent after the second sequence start condition is sent with embedded clock information in the data signal; responding to a first command included in the first datagram when the first command is sent to an address corresponding to a first device identifier associated with the slave device; as well as When a second command included in the second datagram is sent to an address corresponding to a second device identifier associated with the slave device, the second command is responded to. The method of claim 17 , wherein the first device identifier has the same value as the second device identifier. The method of claim 17 , wherein the first device identifier and the second device identifier have different values.

20. The method according to claim 17, further comprising: The third sequence start condition is ignored when it is preceded by an idle period having a duration less than a transmission time of a data byte transmitted over the serial bus.

21. The method according to claim 17, further comprising: receiving a lock command to restrict the slave device to the first operating mode; as well as A third command included in a third datagram transmitted when the serial bus operates in the second operation mode is discarded.

22. The method according to claim 17, further comprising: receiving a lock command to restrict the slave device to the second operating mode; as well as A fourth command included in a fourth datagram transmitted when the serial bus operates in the first operation mode is discarded.

23. The method of claim 17, wherein the first sequence start condition has a first duration and the second sequence start condition has a second duration that is longer than the first duration.

24. A device comprising: an interface circuit adapted to couple the apparatus to a serial bus; and A processor configured to: receiving a first sequence start condition from a data line of the serial bus, the first sequence start condition indicating a first operating mode of the serial bus, in which a first datagram sent after the first sequence start condition is to be sent concurrently with a clock pulse in a clock signal sent on a clock line of the serial bus; receiving a second sequence start condition from the data line, the second sequence start condition indicating a second operating mode of the serial bus, wherein in the second operating mode, a second datagram sent after the second sequence start condition is sent with embedded clock information in the data signal; responding to a first command included in the first datagram when the first command is sent to an address corresponding to a first device identifier associated with the apparatus; as well as When a second command included in the second datagram is sent to an address corresponding to a second device identifier associated with the apparatus, the second command is responded to.

25. The apparatus of claim 24, wherein the first device identifier has the same value as the second device identifier.

26. The apparatus of claim 24, wherein the first device identifier and the second device identifier have different values.

27. The apparatus of claim 24, wherein the processor is further configured to: The third sequence start condition is ignored when it is preceded by an idle period having a duration less than a transmission time of a data byte transmitted over the serial bus.

28. The apparatus of claim 24, wherein the processor is further configured to: receiving a lock command to restrict the device to the first operating mode; and A third command included in a third datagram transmitted when the serial bus operates in the second operation mode is discarded.

29. The apparatus of claim 24, wherein the processor is further configured to: receiving a lock command to restrict the device to the second operating mode; and A fourth command included in a fourth datagram transmitted when the serial bus operates in the first operation mode is discarded.

30. The apparatus of claim 24, wherein the first sequence start condition has a first duration and the second sequence start condition has a second duration that is longer than the first duration.

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