Capacitance detection circuit based on practical differential and peak detection

Abstract

The invention relates to the technical field of capacitance detection circuits, in particular to a capacitance detection circuit based on practical differential and peak detection. According to the circuit, a practical differentiating circuit model is constructed, a capacitance value to be measured is converted into a sinusoidal signal output by a differentiating circuit, then the sinusoidal signal is converted into stable direct-current voltage by utilizing a peak holding circuit, and finally the voltage is read by a single chip microcomputer and the capacitance value is calculated. The whole circuit is simply designed, a practical differentiating circuit and a peak holding circuit serve as cores, linear conversion from weak capacitance to direct-current voltage is achieved, and a complex circuit structure of traditional capacitance detection is avoided. Through circuit structure optimization, stray capacitance interference is effectively suppressed, the detection anti-interference capability is improved, through experimental test verification, a thought and a theoretical model are provided for reading the capacitance value of the capacitance sensor, and the method has certain engineering value for application of a weak capacitance sensor.

Description

Technical Field

[0001] The present invention relates to the technical field of capacitance detection circuits, and in particular to a capacitance detection circuit based on practical differentiation and peak value detection. Background Art

[0002] In fields such as precision measurement and industrial testing, the changes in capacitance to be measured are extremely small, potentially reaching the picofarad level or even lower. Therefore, capacitance detection circuits are needed to capture these tiny capacitance changes. Capacitance detection technology converts capacitance values into observable and measurable signal forms, such as voltage, charge, or frequency, to achieve precise capacitance detection. To accurately reflect tiny capacitance changes, a biased AC signal is usually introduced as a reference. Currently, micro-capacitive sensors (millimeter or micron level) have been widely used in aerospace, medical, and mechanical manufacturing. At the same time, micro-capacitance detection circuits are also widely used in various sensors, such as micro-accelerometers, micro-gyroscopes, and micro-pressure sensors. Therefore, the development of more accurate and low-noise capacitance detection circuits has far-reaching scientific and practical significance. Summary of the Invention

[0003] The purpose of the present invention is to provide a capacitance detection circuit based on practical differentiation and peak detection to solve the problem that the existing capacitance detection circuit fails to detect small capacitance changes due to insufficient sensitivity, stray capacitance interference and nonlinear errors.

[0004] To achieve the above object, a capacitance detection circuit based on practical differentiation and peak detection is provided, comprising a practical differentiation circuit and a peak hold circuit, and also comprising a single-chip microcomputer, wherein a digital-to-analog conversion module of the single-chip microcomputer is connected to the input end of the practical differentiation circuit, an output end of the practical differentiation circuit is connected to the input end of the peak hold circuit, and an output end of the peak hold circuit is connected to the analog-to-digital conversion module of the single-chip microcomputer, wherein:

[0005] The digital-to-analog conversion module of the single-chip microcomputer outputs a sinusoidal excitation signal UI with a DC bias to a practical differential circuit;

[0006] The practical differential circuit receives the sinusoidal excitation signal UI and is connected to the capacitor to be measured Cx, and converts the variation of the capacitor to be measured Cx into an amplitude-modulated sinusoidal signal Udif;

[0007] The peak hold circuit converts the peak value of the sinusoidal signal Udif into a stable DC voltage Upk' and outputs it to the analog-to-digital conversion module of the single chip microcomputer;

[0008] The single chip microcomputer directly reads the DC voltage Upk' through the analog-to-digital conversion module, and calculates the capacitance value of the capacitor to be measured Cx based on a predetermined algorithm.

[0009] In the above technical solution, a linear mapping relationship between capacitance value and DC voltage is directly established through the cascade architecture of a practical differential circuit and a peak hold circuit, simplifying the signal chain. The single-chip microcomputer outputs a sinusoidal excitation signal UI with a DC bias through the digital-to-analog conversion module to avoid signal loss caused by the DC isolation characteristics of pure AC signals. The practical differential circuit converts the change in the capacitance Cx to be measured into an amplitude-modulated sinusoidal signal Udif, so that its amplitude is linearly related to Cx. The peak hold circuit locks the peak value of the sinusoidal signal to a stable DC voltage, eliminating the impact of signal fluctuations on the detection results and ensuring that the single-chip microcomputer analog-to-digital conversion module directly reads reliable data. The single-chip microcomputer simultaneously undertakes the functions of excitation signal generation, voltage acquisition, and capacitance value solution, forming a complete closed-loop system, avoiding the cumulative errors introduced by discrete components, and achieving improved capacitance detection accuracy and anti-interference optimization without relying on specific circuit details.

[0010] On this basis, the practical differential circuit includes an operational amplifier U1, the inverting input terminal of the operational amplifier U1 is connected to the capacitor to be measured Cx, the capacitor to be measured Cx has an equivalent stray capacitance Cp1 and a stray capacitance Cp2, and the other ends of the stray capacitance Cp1 and the stray capacitance Cp2 are grounded;

[0011] The output end and the inverting input end of the operational amplifier U1 are connected in parallel with a feedback capacitor C1 and a feedback resistor R1. The output end of the operational amplifier U1 is also connected to the anode of a limiting voltage-stabilizing diode D5. The cathode of the limiting voltage-stabilizing diode D5 is connected to the cathode of a limiting voltage-stabilizing diode D4. The anode of the limiting voltage-stabilizing diode D4 is connected to the inverting input end of the operational amplifier U1. The output end of the operational amplifier U1 outputs a sinusoidal signal Udif.

[0012] In this technical solution, feedback capacitor C1 and feedback resistor R1 form a low-pass filter, suppressing high-frequency noise interference on the differential signal. Limiting voltage-stabilizing diodes D4 and D5 clamp the output voltage of operational amplifier U1 to within ±12V, preventing overvoltage damage to the device while ensuring stable output signal amplitude. Combined with a virtual ground design, the charge and discharge paths of stray capacitances Cp1 and Cp2 are symmetrically offset or absorbed. This reduces the error caused by stray capacitance and improves the accuracy of weak capacitance detection.

[0013] In another technical solution, the output terminal of the first-stage operational amplifier U2A is connected to the cathode of the clamping diode D1, and the anode of the clamping diode D1 is connected to the inverting input terminal of the first-stage operational amplifier U2A;

[0014] The output terminal of the first-stage operational amplifier U2A is connected to the anode of the diode D2, the cathode of the diode D2 is connected to the anode of the diode D3, and the cathode of the diode D3 is connected to the non-inverting input terminal of the second-stage operational amplifier U2B;

[0015] The non-inverting input terminal of the second-stage operational amplifier U2B is connected to the peak holding capacitor C2 and the discharge resistor R5, and the other ends of the peak holding capacitor C2 and the discharge resistor R5 are grounded.

[0016] In this technical solution, the first-stage operational amplifier U2A forms a negative feedback loop through clamping diode D1, rapidly shutting off on the falling edge of the input signal to prevent reverse current interference. Diodes D2 and D3 are connected in series, and the feedback path of the second-stage operational amplifier U2B is used to equalize the potential across diode D3, eliminating the diode voltage drop and leakage current, reducing the voltage decay rate of peak-holding capacitor C2 to the picoampere level. The non-inverting input of the second-stage operational amplifier U2B is connected to discharge resistor R5, which controls the discharge rate of capacitor C2 and ensures voltage stability during periodic sampling by the microcontroller ADC. This solves the signal attenuation problem caused by leakage in traditional peak detection circuits.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. In this capacitance detection circuit based on practical differentiation and peak detection, the practical differentiation circuit converts the measured capacitance Cx into a sinusoidal signal Udif containing the capacitance parameters. The peak hold circuit converts the sinusoidal signal Udif output by the practical differentiation circuit into a DC voltage Upk' with its amplitude. The capacitance value is then calculated using analog-to-digital conversion by a single-chip microcomputer. This linear conversion of the capacitance value into a DC voltage, which the microcontroller then reads to obtain the capacitance value, simplifies the circuit complexity of capacitance detection, enabling detection of weak capacitance even with a small number of components. This approach provides high accuracy and is suitable for stable operating conditions.

[0019] 2. In this capacitance detection circuit based on practical differentiation and peak detection, the input sinusoidal signal equally charges and discharges the stray capacitance Cp1 without generating any charge on the feedback resistor R1. Throughout the circuit's operation, capacitor Cp2 remains connected to the operational amplifier's virtual ground, without affecting the amplifier's output. The resulting output is insensitive to stray capacitances Cp1 and Cp2, providing excellent engineering benefits for accurate capacitance sensor measurement.

[0020] 3. In the capacitance detection circuit based on practical differentiation and peak detection, the peak holding circuit adopts a structure of a combination of dual operational amplifiers and diodes. The output potential of the second-stage operational amplifier U2B is matched with the potential at both ends of the diode D3 to make the diode voltage drop zero, eliminating the influence of nanoampere leakage current, and only discharges through the second-stage operational amplifier U2B to avoid interference with the first-stage operational amplifier U2A. At the same time, the picoampere bias current characteristics of the operational amplifier are utilized to greatly improve the peak voltage holding accuracy, follow the rising edge of the input signal in real time, and lock the peak voltage on the falling edge to ensure stable output under high-frequency signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the structure of the practical differential circuit of the present invention;

[0022] Figure 2 Schematic diagram of the structure of the peak holding circuit of the present invention;

[0023] Figure 3 Schematic diagram of a stray capacitance model of a capacitive sensor according to the present invention;

[0024] Figure 4 This is a diagram of the experimental test platform architecture for the capacitance detection circuit of the present invention;

[0025] Figure 5 This is a block diagram of the capacitance detection circuit experimental test platform architecture of the present invention;

[0026] Figure 6 The results of the input signal, practical differential output signal, and peak hold output voltage when the capacitance to be measured is 96.37pF in the present invention;

[0027] Figure 7 This is the result of the input signal, practical differential output signal, and peak hold output voltage when the capacitance to be measured is 173.64 pF. DETAILED DESCRIPTION

[0028] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0029] The present embodiment aims to provide a capacitance detection circuit based on practical differentiation and peak detection. For a capacitance sensor, the capacitance value is detected using a combination of practical differentiation and peak detection circuit, specifically including:

[0030] For capacitance sensors, a capacitance detection circuit based on a practical differential and peak hold combination circuit is designed. Figure 1 and Figure 2 As shown. Connect the capacitor Cx to the practical differential circuit, and the DC power input passes through the charge pump chip SGM3209 to obtain the corresponding negative voltage, providing dual power supply for the operational amplifier. The digital-to-analog conversion module of the microcontroller STM32F103ZET6 is used to generate a sinusoidal excitation signal UI with an offset voltage. The input sinusoidal excitation signal UI is

[0031] U I =V S sin2πft;

[0032] Among them, U I It is the instantaneous value of the input voltage (unit: V), which represents the AC voltage signal that changes with time;

[0033] V S is the amplitude of the sinusoidal voltage (unit: V), that is, the maximum value of the voltage waveform (half the peak-to-peak value);

[0034] f is the frequency of the sinusoidal signal (unit: Hz), which is generated by the microcontroller and determines how fast the voltage changes;

[0035] t is the time variable (unit: s), which represents the instantaneous time point of the signal.

[0036] like Figure 1 As shown, one end of the capacitance sensor to be measured is connected to the offset sinusoidal excitation signal UI, and the other end of the capacitance to be measured Cx is connected to the inverting input of the operational amplifier U1. The output and inverting input of the operational amplifier U1 are connected in parallel with the feedback capacitor C1 and the feedback resistor R1. The output end is also connected to the anode of the limiting voltage zener diode D5, the cathode of the limiting voltage zener diode D5 is connected to the cathode of the limiting voltage zener diode D4, and the anode of the limiting voltage zener diode D4 is connected to the inverting input of the operational amplifier U1.

[0037] Operational amplifier U1 is in deep negative feedback, with its inverting and non-inverting inputs virtually shorted and disconnected, both at zero potential. The input is a sinusoidal excitation signal UI with an offset. Since operational amplifier U1 is virtually shorted and disconnected, according to KCL's current law (Kirchhoff's current law, which states that in a lumped parameter circuit, the sum of the currents flowing into any node or closed surface at any time is equal to the sum of the currents flowing out of the node):

[0038]

[0039] Where iR1 is the current flowing through resistor R1 (unit: A);

[0040] iCx is the current flowing through the capacitor Cx to be measured (unit: A);

[0041] C is the capacitance of the capacitor to be measured (unit: F), which is Cx in the formula, usually in picofarads;

[0042] dUI / dt is the differential of the input voltage UI with respect to time t (unit: V / s).

[0043]

[0044] Where R1 is the feedback resistor of the differential circuit (unit: Ω), which is used to adjust the output voltage amplitude. The typical value is 205kΩ.

[0045] Cx is the capacitance value of the capacitive sensor to be measured (unit: F), usually in the picofarad level (such as 96.37pF);

[0046] UI is the input offset sinusoidal excitation signal, generated by the microcontroller DAC, where Vs is the signal amplitude;

[0047] f is the frequency of the sinusoidal excitation signal (unit: Hz), which is set by the microcontroller (e.g. 1kHz). The higher the frequency, the greater the output amplitude.

[0048] t is the time variable (unit: s), which represents the instantaneous time of the signal;

[0049] Udif is the output voltage of the differentiator (V). It is a sinusoidal signal with a Cx parameter. Its amplitude is proportional to Cx, and the negative sign indicates that the output is out of phase with the input.

[0050] The capacitance sensor spurious model is as follows Figure 3 As shown in the figure. In weak capacitance detection, the actual value of the measured capacitance Cx is often contaminated by stray capacitance. This stray capacitance is caused by circuit layout, sensor electrode-to-ground coupling, or parasitic parameters between signal traces, and manifests as equivalent distributed stray capacitance Cp1 and Cp2. The inverting input of operational amplifier U1 is connected to the measured capacitance Cx. Equivalent stray capacitances Cp1 and Cp2 exist across the measured capacitance Cx, with the other ends of these capacitances connected to ground. The input sinusoidal excitation signal UI charges and discharges stray capacitance Cp1 equally without generating any charge on feedback resistor R1. Throughout the circuit's operation, stray capacitance Cp2 remains connected to the virtual ground of operational amplifier U1 and has no effect on its output. The final output is insensitive to stray capacitances Cp1 and Cp2, providing excellent engineering benefits for accurate capacitance sensor measurement.

[0051] like Figure 2 As shown, in the peak hold circuit, the output terminal of the first-stage operational amplifier U2A is connected to the cathode of the clamping diode D1, the anode of the diode D1D1 is connected to the inverting input terminal of the first-stage operational amplifier U2A, the output terminal of the first-stage operational amplifier U2A is connected to the anode of the diode D2, the cathode of the diode D2 is connected to the anode of the diode D3, the cathode of the diode D3 is connected to the non-inverting input terminal of the second-stage operational amplifier U2B, the non-inverting input terminal of the second-stage operational amplifier U2B is connected to the peak holding capacitor C2 and the discharge resistor R5, the capacitor C2 and the resistor R5 are connected in parallel and then grounded, the output terminal of the second-stage operational amplifier U2B is connected to the current limiting resistor R3 and the resistor R4, the other end of the resistor R3 is connected to the anode of the clamping diode D1, and the other end of the resistor R4 is connected to the connection point of the diode D2 and the diode D3.

[0052] The capacitance value to be measured is converted into a sinusoidal signal Udif containing the capacitance value. Diode D2, diode D3 and capacitor C2 are the core components of peak hold, forming a voltage follower circuit, which solves the problem that the output load extracts charge and causes the peak value stored on the capacitor to decrease. A diode D3 is added to the feedback loop of the first-stage operational amplifier U2A. The node between diode D2 and diode D3 is connected to the output end of the second-stage operational amplifier U2B. The output potential of the second-stage operational amplifier U2B is equal to the node potential of diode D3 and capacitor C2. Therefore, the voltage drop across diode D3 is zero. At this time, the leakage current of diode D3 is eliminated. The factors affecting the discharge of capacitor C2 in the entire circuit are the bias current of the first-stage operational amplifier U2A and the second-stage operational amplifier U2B. The leakage current of diode D3 has the greatest impact, which can reach 100 nanoamperes (1 nanoampere = 10 -9 Ampere) level, while the bias current of the first stage operational amplifier U2A and the second stage operational amplifier U2B is only picoampere (1 picoampere = 10 -12 ampere) level. Through this improvement, the accuracy of maintaining the peak voltage on capacitor C2 has been significantly improved. The negative feedback point of the first-stage operational amplifier U2A is changed from the node of diode D3 and capacitor C2 to the output of the second-stage operational amplifier U2B, and the output of the second-stage operational amplifier U2B is fed back to the output of the first-stage operational amplifier U2A through diode D1. The discharge path of capacitor C2 is only the second-stage operational amplifier U2B, eliminating the discharge to the first-stage operational amplifier U2A. When the input signal reaches its peak and falls back, the potential of the non-inverting input of the first-stage operational amplifier U2A is lower than the potential of the inverting input, pulling the output voltage down toward the negative power rail. The output of the second-stage operational amplifier U2B is still at the peak potential, so the diode D3 between the first-stage operational amplifier U2A and the second-stage operational amplifier U2B will conduct, and the inverting input of the first-stage operational amplifier U2A is approximately 0.5V higher than the output. In the case of deep negative feedback of the operational amplifier, the potentials of the non-inverting input and the inverting input are nearly equal, that is, a virtual short. During the process of the potential drop at the output of the first-stage operational amplifier U2A, it does not drop to the negative power rail, because at that time the potential of the inverting input is not consistent with the potential of the non-inverting input. It only drops to the peak potential minus the voltage drop of diode D3. This design makes the low potential of the output of the first-stage operational amplifier U2A only one diode voltage drop lower than the high potential, allowing the peak hold circuit to more accurately detect the peak value of the signal. The output of the peak hold circuit is

[0053] U pk =2πfR1C X V S ;

[0054] Where Upk is the DC voltage output by the peak hold circuit (unit: V), which is equal to the peak absolute value of the output signal of the differentiator circuit;

[0055] The meanings of R1, Cx, Vs, and f are consistent with the above formula.

[0056] Using the MCU analog-to-digital conversion module, the MCU reads the peak hold circuit as Upk' and calculates the capacitance value to be

[0057]

[0058] Wherein, Cx is the final calculated capacitance value to be measured (unit: F), which is obtained by reverse deduction by reading Upk′ (measured value) by the microcontroller.

[0059] Upk′ is the peak hold voltage (unit: V) actually read by the microcontroller. Due to circuit losses (such as diode voltage drop), there may be a slight error between the theoretical value Upk and the actual value.

[0060] The meanings of R1, Vs, and f are consistent with the above formula.

[0061] The following experimental tests verify the effectiveness of the proposed practical differential and peak hold combination circuit, which is applicable to weak capacitance sensors. This method does not require control. The differential circuit converts the measured capacitance Cx into a sinusoidal signal Udif containing the capacitance value parameter. The peak hold circuit converts the sinusoidal signal Udif into a DC voltage Upk' with the same amplitude. The DC voltage Upk' is read by the microcontroller and the value of the measured capacitance Cx is calculated.

[0062] In order to verify the effectiveness of the capacitance detection circuit based on practical differentiation and peak hold provided by the present invention, a capacitance detection circuit platform based on practical differentiation and peak hold was built. Figure 4 and Figure 5 As shown, the detection results of the capacitance detection circuit based on practical differentiation and peak hold are given; among them, the experimental parameters are shown in Table 1.

[0063] Table 1 Experimental parameters

[0064]

[0065] Figure 6 Given that when the capacitance to be measured is 96.37pF, the output voltage of the differential circuit is 1.066V, and the output voltage of the peak hold circuit is 1.071V. The calculated output voltage of the peak hold circuit should be 1.065V, with an error of 0.56%. The proposed practical differential and peak hold circuit is accurate and reliable in detecting weak capacitance. The main reasons for the error are:

[0066] 1. The operational amplifier has zero offset, and there is output when there is no input signal;

[0067] 2. The capacitance sensor has a shunt resistor, and the output of the practical differential circuit becomes larger;

[0068] Figure 7 It is given that when the capacitance to be measured is 173.64pF, the output voltage of the differential circuit is 1.921V, and the output voltage of the peak holding circuit is 1.928V. It is calculated that the output voltage of the peak holding circuit should be 1.919V, and the error is 0.47%. Therefore, the capacitance detection circuit based on practical differentiation and peak holding proposed in the present invention is very effective.

[0069] Working principle: First, analyze the current path of the practical differential circuit and determine that the output of the differential circuit is a sinusoidal signal containing the capacitance parameters to be measured; utilize the unidirectional conductivity of the peak holding circuit diode and the diode clamping function to ensure that the output DC voltage of the peak holding circuit will not drop too much when the input signal drops, so that it can work normally under relatively high frequency input signals. Then, read the output DC voltage through the single-chip microcomputer and calculate the capacitance value to be measured.

[0070] The working process of the practical differential and peak hold combination circuit is:

[0071] Step 1: Determine the appropriate feedback resistor for the differential circuit so that the output voltage can be read by the microcontroller. The microcontroller sends an offset sinusoidal excitation signal through the digital-to-analog converter module. The differential circuit converts the capacitance to be measured into a sinusoidal signal containing the capacitance parameter.

[0072] Step 2: The peak hold circuit sets the output to follow mode when the input signal rises. When the input signal drops from its peak value, the diode's unidirectional conductivity and the capacitor's voltage retention capability keep the capacitor voltage at its peak value, barely decreasing. When the input signal reaches a higher peak, the output voltage continues to follow.

[0073] Step 3: The microcontroller reads the output voltage of the peak hold circuit and calculates the capacitance value.

[0074] Based on the above theory, the practical differentiation and peak hold combination circuit can be summarized into the following steps:

[0075] 1. Determine the appropriate feedback resistor for the differential circuit so that the output voltage can be read by the microcontroller. The microcontroller sends an offset sinusoidal excitation signal through the digital-to-analog converter module. When the operational amplifier is in deep negative feedback, the non-inverting input and the reverse input become virtually shorted and disconnected, and the potential approaches zero. Due to the KCL law, the practical differential circuit converts the measured capacitance value into a sinusoidal signal containing the capacitance parameter.

[0076] 2. The peak hold circuit outputs a follower mode when the input signal rises. When the input signal drops from its peak value, the diode's unidirectional conductivity and the capacitor's voltage retention capability keep the capacitor voltage at its peak value with little drop. When the input signal reaches a higher peak, the output voltage continues to follow.

[0077] 3. The microcontroller reads the output voltage of the peak hold circuit and calculates the capacitance value.

[0078] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely preferred examples of the present invention and are not intended to limit the present invention. Various changes and improvements may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and improvements fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. A capacitance detection circuit based on practical differentiation and peak detection, comprising a practical differentiation circuit and a peak hold circuit, characterized in that: It also includes a single-chip microcomputer, wherein the digital-to-analog conversion module of the single-chip microcomputer is connected to the input end of the practical differential circuit, the output end of the practical differential circuit is connected to the input end of the peak holding circuit, and the output end of the peak holding circuit is connected to the analog-to-digital conversion module of the single-chip microcomputer, wherein: The digital-to-analog conversion module of the single-chip microcomputer outputs a sinusoidal excitation signal UI with a DC bias to a practical differential circuit; The practical differential circuit receives the sinusoidal excitation signal UI and is connected to the capacitor to be measured Cx, and converts the variation of the capacitor to be measured Cx into an amplitude-modulated sinusoidal signal Udif; The peak hold circuit converts the peak value of the sinusoidal signal Udif into a stable DC voltage Upk' and outputs it to the analog-to-digital conversion module of the single chip microcomputer; The single chip microcomputer directly reads the DC voltage Upk' through the analog-to-digital conversion module, and calculates the capacitance value of the capacitor to be measured Cx based on a predetermined algorithm.

2. The capacitance detection circuit based on practical differentiation and peak detection according to claim 1, characterized in that: The circuit also includes a charge pump chip connected to all operational amplifiers in the practical differential circuit and the peak hold circuit, for generating a negative power supply voltage to provide dual power supply for all operational amplifiers.

3. The capacitance detection circuit based on practical differentiation and peak detection according to claim 1, characterized in that: The practical differential circuit includes an operational amplifier U1, an inverting input terminal of the operational amplifier U1 is connected to a capacitor to be measured Cx, and the capacitor to be measured Cx has an equivalent stray capacitance Cp1 and a stray capacitance Cp2, and the other ends of the stray capacitance Cp1 and the stray capacitance Cp2 are grounded.

4. The capacitance detection circuit based on practical differentiation and peak detection according to claim 3, characterized in that: The other end of the capacitor Cx to be measured is connected to the current limiting resistor R2, and the other end of the current limiting resistor R2 is connected to the digital-to-analog conversion module of the single-chip microcomputer. The non-inverting input end of the operational amplifier U1 is connected to the resistor R', and the other end of the resistor R' is grounded.

5. The capacitance detection circuit based on practical differentiation and peak detection according to claim 4, characterized in that: The output end and the inverting input end of the operational amplifier U1 are connected in parallel with a feedback capacitor C1 and a feedback resistor R1. The output end of the operational amplifier U1 is also connected to the anode of a limiting voltage-stabilizing diode D5. The cathode of the limiting voltage-stabilizing diode D5 is connected to the cathode of a limiting voltage-stabilizing diode D4. The anode of the limiting voltage-stabilizing diode D4 is connected to the inverting input end of the operational amplifier U1. The output end of the operational amplifier U1 outputs a sinusoidal signal Udif.

6. The capacitance detection circuit based on practical differentiation and peak detection according to claim 1, characterized in that: The peak hold circuit includes a first-stage operational amplifier U2A and a second-stage operational amplifier U2B. The first-stage operational amplifier U2A receives a sinusoidal signal Udif at its non-inverting input terminal.

7. The capacitance detection circuit based on practical differentiation and peak detection according to claim 6, characterized in that: The output terminal of the first-stage operational amplifier U2A is connected to the cathode of the clamping diode D1 , and the anode of the clamping diode D1 is connected to the inverting input terminal of the first-stage operational amplifier U2A.

8. The capacitance detection circuit based on practical differentiation and peak detection according to claim 7, characterized in that: The output terminal of the first-stage operational amplifier U2A is connected to the anode of the diode D2, the cathode of the diode D2 is connected to the anode of the diode D3, and the cathode of the diode D3 is connected to the non-inverting input terminal of the second-stage operational amplifier U2B.

9. The capacitance detection circuit based on practical differentiation and peak detection according to claim 8, characterized in that: The non-inverting input terminal of the second-stage operational amplifier U2B is connected to the peak holding capacitor C2 and the discharge resistor R5, and the other ends of the peak holding capacitor C2 and the discharge resistor R5 are grounded.

10. The capacitance detection circuit based on practical differentiation and peak detection according to claim 9, characterized in that: The output end of the second-stage operational amplifier U2B is connected to the inverting input end of the second-stage operational amplifier U2B. The output end of the second-stage operational amplifier U2B is also connected to the current limiting resistor R3 and the current limiting resistor R4. The other end of the current limiting resistor R3 is connected to the anode of the clamping diode D1. The other end of the current limiting resistor R4 is connected to the cathode of the diode D2 and the anode of the diode D3.

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