Register model and register transfer level generation and test method and device, equipment and medium

Abstract

The invention discloses a register model and register transfer level generation and test method, device, equipment and medium, and relates to the technical field of integrated circuit design verification, and the method comprises the following steps: analyzing a comma separation value table file by using a register generation platform to generate a register model, a register transfer level and a register test vector; the comma separation value table file is a file used for describing register information; generating a general verification methodology environment by using a test environment generation platform, and integrating the general verification methodology environment based on the register model, the register transfer level and the register test vector to obtain a corresponding integrated test environment; and compiling the integrated test environment, if the compiling is successful, running the register test vector in the integrated test environment which is successfully compiled, and outputting a corresponding test result. Therefore, the automation degree of register model verification can be improved, and the verification efficiency of front-end verification is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design verification, and in particular to methods, devices, equipment and media for generating and testing register models and register transfer levels. Background Art

[0002] As integrated circuit (IC) design becomes increasingly complex, register size continues to grow, making register model generation and verification a critical task in front-end verification. Existing technologies, particularly for the tens of thousands of registers that may be contained within a single Internet Protocol (IP), have limitations in automated test vector generation, verification environment setup, and result analysis. Constructing test vectors for these large registers requires manual coding, a tedious and error-prone process that creates a significant workload. Furthermore, manually setting up a verification environment based on the register model and running test vectors can be a significant burden when verifying multiple IPs simultaneously. Given the relatively small differences in register properties across different modules and the large number of registers in large-scale integrated circuits, an automated approach is needed to simultaneously address register generation and verification for different design modules, facilitating unified management and improving verification efficiency. Summary of the Invention

[0003] The purpose of the embodiments of the present invention is to provide a method, apparatus, device, and medium for generating and testing a register model and register transfer level, which can achieve full automation of the register model and register transfer level design and verification process, significantly reducing the need for manual configuration and improving the efficiency and accuracy of register design and verification. The specific solution is as follows:

[0004] In a first aspect, the present invention provides a method for generating and testing a register model and a register transfer level, comprising:

[0005] Using a register generation platform to parse a comma-separated value table file to generate a register model, a register transfer level, and a register test vector; the comma-separated value table file is a file used to describe register information;

[0006] Generate a general verification methodology environment using a test environment generation platform, integrate the general verification methodology environment based on a register model, a register transfer level, and register test vectors, and obtain a corresponding integrated test environment;

[0007] The post-integration test environment is compiled. If the compilation is successful, the register test vector is run in the post-integration test environment after the compilation is successful, and the corresponding test results are output.

[0008] Optionally, before parsing the comma-separated value table file using the register generation platform, the following steps are also included:

[0009] The comma-separated value table file is determined according to the requirements of the register generation platform; the comma-separated value table file includes the name, domain segment, path, access method, address and default value of the register.

[0010] Optionally, the general verification methodology environment includes a virtual IP configuration file, a general verification methodology verification environment component, a test case file, and a compilation control script file;

[0011] Among them, the virtual IP configuration file is used to define the interface and behavior of the bus protocol; the general verification methodology verification environment component is used to mount the environment component of the advanced high-performance bus virtual IP, the virtual IP configuration information and the adapter component of the register model and the predictor component used to verify whether the actual behavior of the design under test meets the expectations; among them, the design under test includes the register model and the register transfer level.

[0012] Optionally, integrate a common verification methodology environment based on register models, register transfer levels, and register test vectors, including:

[0013] Integrate register models into common verification methodology verification environment components and virtual sequence controllers;

[0014] Mount the adapter component and the predictor component in the general verification methodology environment, and perform corresponding instantiation, connection, and configuration operations on the adapter component and the predictor component;

[0015] Generate test cases for basic test classes and mounted register test vectors based on preset test templates;

[0016] Extract the signals in the register transfer level and instantiate the signals into the test case file to obtain the test envelope;

[0017] Generate register model packages, verification environment packages, and test case packages based on register transfer levels, register test vectors, and test cases; the register model package is used to centrally manage register models and adapter components; the verification environment package is used to encapsulate the general verification methodology verification environment components; and the test case package is used to encapsulate basic test classes and test cases into the general verification methodology environment.

[0018] Generate a compilation control script according to the preset template, the name and path of the register model and the compilation control script file;

[0019] The general verification methodology environment is integrated based on the test envelope, register model package, verification environment package and test cases.

[0020] Optionally, compile the post-integration test environment, including:

[0021] Compile the post-integration test environment based on the compilation control script;

[0022] Correspondingly, after compiling the integrated test environment, it also includes:

[0023] If the integration test environment fails to compile, an error message is sent so that the integration test environment can be modified according to the error message and the compilation log, and the corresponding modified test environment can be compiled.

[0024] Optionally, the register model and register transfer level generation and testing method further includes:

[0025] Generate a tool command language file and run the target test environment according to the tool command language file; the target test environment is the post-integration test environment after successful compilation.

[0026] Optionally, the register model and register transfer level generation and testing method further includes:

[0027] During the operation of the target test environment, monitor the operation log of the target test environment, collect error information, and generate corresponding test logs;

[0028] After the target test environment is finished running, the test log is output.

[0029] In a second aspect, the present invention provides a register model and a register transfer level generation and testing device, comprising:

[0030] A file parsing module is used to parse a comma-separated value table file using a register generation platform to generate a register model, a register transfer level, and a register test vector; the comma-separated value table file is a file used to describe register information;

[0031] A test environment integration module is used to generate a general verification methodology environment using a test environment generation platform, integrate the general verification methodology environment based on a register model, a register transfer level, and register test vectors, and obtain a corresponding integrated test environment;

[0032] The test result output module is used to compile the post-integration test environment. If the compilation is successful, the register test vector is run in the post-integration test environment after the compilation is successful, and the corresponding test results are output.

[0033] In a third aspect, the present invention provides an electronic device, comprising:

[0034] memory for storing computer programs;

[0035] A processor is used to execute a computer program to implement the aforementioned register model and register transfer level generation and testing method.

[0036] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the aforementioned register model and register transfer level generation and testing method.

[0037] In the present invention, a register generation platform is used to parse a comma-separated value table file to generate a register model, a register transfer level, and a register test vector; the comma-separated value table file is a file used to describe register information; a test environment generation platform is used to generate a general verification methodology environment, and the general verification methodology environment is integrated based on the register model, the register transfer level, and the register test vector to obtain a corresponding integrated test environment; the integrated test environment is compiled, and if the compilation is successful, the register test vector is run in the integrated test environment after the compilation is successful, and the corresponding test results are output.

[0038] Beneficial effects: The present invention generates a register model and a register transfer level through a comma-separated value table file. The register transfer level, as an actual register circuit, can be integrated into the design to be tested, facilitating the centralized management of register settings, access, and verification, reducing the register design workload of designers, improving maintenance efficiency, and facilitating unified register verification by verification personnel. At the same time, a general verification methodology environment can be generated. The verification environment will automatically compile the integrated test environment according to the register model and the register transfer level, run the test vector, and finally output the test results. In this way, a register model is automatically generated based on any register information file in the comma-separated value table file format that meets the platform requirements, and mounted to the test environment for operation and test result output. This greatly improves the degree of automation of register model verification, saves register verification time, and improves the verification efficiency of front-end verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1 A flow chart of a register model and register transfer level generation and testing method provided by an embodiment of the present invention;

[0041] Figure 2A flow chart of a specific register model and register transfer level generation and testing method provided by an embodiment of the present invention;

[0042] Figure 3 A schematic diagram of the structure of a register model and register transfer level generation and testing device provided by an embodiment of the present invention;

[0043] Figure 4 A structural diagram of an electronic device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0045] The terms "including" and "having," as used in the present description and accompanying drawings, and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements and may include steps or elements that are not listed.

[0046] In order to enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0047] Some methods improve verification efficiency by automating register model construction, parsing bit-field attributes, constructing test vectors, and using UVM (Universal Verification Methodology) components for test vector driving and result comparison. However, they lack detailed descriptions of register model construction, test vector generation, test environment setup, and automated implementation. Furthermore, they do not automatically generate the register module's RTL (Register-Transfer Level), resulting in a unclear integration between the test environment and the DUT (Device Under Test) that instantiates the register RTL. For example, when building a register model, specific register information or format is input, resulting in specific register-related components output; how to ensure the universality of the test environment to verify any register model; how to construct test vectors for registers with different access methods; how to verify individual registers; and the test execution process are all unclear. In order to solve the above technical problems, the present invention discloses a method, device, equipment and medium for generating and testing a register model and a register transfer level, which can realize the full process automation of register model and register transfer level design verification, significantly reduce the need for manual configuration, and improve the efficiency and accuracy of register design and verification.

[0048] See also Figure 1 As shown, an embodiment of the present invention provides a register model and a register transfer level generation and testing method, including:

[0049] Step S11 , using a register generation platform to parse a comma-separated value table file to generate a register model, a register transfer level, and a register test vector; the comma-separated value table file is a file used to describe register information.

[0050] In an embodiment of the present invention, a register model file CSV (Comma-Separated Values) file, also called a CSV file, is first prepared. A register model file in CSV format is prepared according to the requirements of platform B (register generation platform), which contains all necessary information of the register, such as name, domain, access method, address and default value; at the same time, the test case name is extracted as an environment variable to provide parameter input for subsequent automated processes. It should be noted that the operation of the present invention is carried out in an environment that integrates the automatic generation of a brief test environment platform A and the automatic generation of a register model platform B. Therefore, before parsing the comma-separated value table file, the comma-separated value table file is first determined according to the requirements of the register generation platform; the comma-separated value table file includes the name, domain, path, access method, address and default value of the register.

[0051] Furthermore, by inputting the register information CSV file, calling platform B, the CSV file is automatically parsed and the following files are generated: reg_model (register model), register_top_wrapper (register interface register transfer level), reg_access_seq, reg_reset_seq, reg_bit_bash_seq (register test vector). At the same time, reg_hdl (register path) and reg_info (register information) are also generated; the reg_model file is based on the UVM methodology and defines all registers and register blocks; the register_top_wrapper file is a register interface module for designers and can be instantiated into the design RTL module. It has an AHB (Advanced High Performance Bus) bus interface for external access and a register port directly connected to other modules. As a register module, it is also the target RTL for register testing; reg_hdl and reg_info are auxiliary files. The reg_hdl file defines the register path and can help users perform backdoor access to registers. The reg_info file is the register information in the test vector and needs to be used in conjunction with the reg_access_seq, reg_reset_seq, and reg_bit_bash_seq files to flexibly control the behavior of a single register, such as mirror operations, mask operations, ignore checks, etc. The three test vectors reg_access_seq, reg_reset_seq, and reg_bit_bash_seq define the test process for registers with different access methods. The reg_reset_seq file tests whether the register value read is equal to the register's mirror value. The reg_access_seq file performs random front-door writes to RW (Read-Write) registers, reads and checks the read value with the front-door for equality. After each register access, the back-door checks whether the read value of all other registers is equal to the mirror value. The WO (Write Only) registers are randomly written to by the front-door, read and checked by the back-door, and after each register access, the back-door checks whether the read value of all other registers is equal to the mirror value. The RO (Read Only) registers are randomly written to by the back-door, read and checked the read value with the front-door for equality. After each register access, the back-door checks whether the read value of all other registers is equal to the mirror value. The reg_bit_bash_seq file writes 1'b1 to each RW / RO register bit by bit, reads and checks it with the front-door, then writes 1'b0 to each bit, and reads and checks it with the front-door. No check is performed on the WO register.In this way, through automated scripts and tools, you only need to input the register information description file first to generate a register model. At the same time, you can also generate a register interface RTL module with an AHB bus interface. This RTL, as an actual register circuit, can be integrated into the DUT, facilitating centralized management of register settings, access, and verification, reducing the register design workload of designers, improving maintenance efficiency, and facilitating unified register verification for verification personnel.

[0052] Step S12: Generate a universal verification methodology environment using the test environment generation platform, integrate the universal verification methodology environment based on the register model, register transfer level, and register test vectors, and obtain a corresponding integrated test environment.

[0053] In an embodiment of the present invention, a test environment generation platform is used to automatically generate an initial UVM verification environment. The universal verification methodology environment includes a virtual IP configuration file, a universal verification methodology verification environment component, a test case file, and a compilation control script file. The virtual IP configuration file is used to define the interface and behavior of the bus protocol. The universal verification methodology verification environment component is used to mount an environment component of an advanced high-performance bus virtual IP, virtual IP configuration information, and an adapter component of a register model, and a predictor component for verifying whether the actual behavior of the design under test meets expectations. The design under test includes a register model and a register transfer level. Specifically, the environment structure includes the following main components:

[0054] 1. VIP (Virtual IP) configuration files, which define the interfaces and behaviors of bus protocols such as AMBA (Advanced Microcontroller Bus Architecture, an interconnect protocol for communication between blocks or IPs in a system-on-chip).

[0055] 2. The UVM environment component env (represents the UVM verification environment (such as uart_ctrl_env), which is a container class inherited from uvm_env and is used to integrate components such as agent, scoreboard, register model, and configure the verification platform hierarchy) mainly mounts the env component of AHB VIP and VIP configuration information. At the same time, the register model reg_model and adapter (adapter), and the predictor (predictor) component are mounted in it.

[0056] 3. th file (test case file) instantiates the register interface RTL module to be tested generated by platform B in the second step. After automatically extracting the signals of the RTL module, it connects its AHB bus interface and the register input and output port signals so that the output of the test vector can drive the register RTL module.

[0057] 4. Makefile (compilation control script) file, configures the verification environment and verification process to automatically compile the test environment and run the test vectors.

[0058] Furthermore, after generating the general verification methodology environment, the register model is integrated into the general verification methodology verification environment component and the virtual sequence controller; the adapter component and the predictor component are mounted in the general verification methodology environment, and the adapter component and the predictor component are instantiated, connected and configured accordingly; according to the preset test template, the basic test class and the test case for mounting the register test vector are generated; the signal in the register transfer level is extracted, and the signal is instantiated into the test case file to obtain the test envelope; according to the register transfer level, the register test vector and the test case, the register model package, the verification environment package and the test case package are generated; wherein, the register model package is used to centrally manage the register model and the adapter component; the verification environment package is used to encapsulate the general verification methodology verification environment component; the test case package is used to encapsulate the basic test class and the test case into the general verification methodology environment; the compilation control script is generated according to the preset template, the name and path of the register model and the compilation control script file; the general verification methodology environment is integrated based on the test envelope, the register model package, the verification environment package and the test case, and then the corresponding integrated test environment is obtained.

[0059] Step S13: compile the post-integration test environment. If the compilation is successful, run the register test vector in the post-integration test environment after the compilation is successful, and output the corresponding test results.

[0060] In an embodiment of the present invention, after the general verification methodology environment is automatically integrated, the integrated test environment is compiled based on the compilation control script. In addition, after the integrated test environment is compiled, it is detected whether the integrated test environment is compiled successfully. If the integrated test environment fails to compile, an error message is sent so that the integrated test environment can be modified according to the error message and the compilation log, and the corresponding modified test environment is compiled. In other words, after the test environment is integrated, the compilation operation is automatically performed, and the compilation log is monitored at the same time. When the compilation fails, an error message is reported to the user, reminding the user to manually modify the test environment according to the compilation log and compile again.

[0061] In an embodiment of the present invention, if the post-integration test environment is compiled successfully, the register test vector is run in the post-integration test environment after the compilation is successful, that is, 3 test vectors are automatically run. It should be noted that the present invention will generate a tool command language file and run the target test environment according to the tool command language file; the target test environment is the post-integration test environment after successful compilation. In a specific embodiment, a tcl file called simrun.do (TCL (Tool Command Language) script file, used to control the operation process of the simulation tool, including operations such as compilation, loading design, executing tests, recording waveforms, etc.) is generated to control the operation of the test environment during operation. The operation of the target test environment is controlled by the tool command language file.

[0062] After the test environment is integrated and compiled, the integrated test environment can be run after successful compilation. Simultaneously, while running the target test environment, the target test environment's run log is monitored, error information is collected, and a corresponding test log is generated. After the target test environment completes its run, the test log is output. Simply put, the run log is monitored and error information is collected during the run. After the run is complete, the test results are printed and a test log file is provided to the user. This allows the present invention to automatically generate a UVM verification environment and test vectors. The verification environment automatically integrates the generated register model and instantiates the register RTL. It then automatically compiles the integrated test environment, runs the test vectors, and finally outputs the test results. Furthermore, because test vectors are automatically generated from templates and can configure individual registers based on register information to control test behavior, subsequent register modifications and test vector additions require only modifying the register information file or the test vector template, eliminating the need to modify the entire system. This provides excellent flexibility and scalability. Furthermore, the register interface RTL is automatically generated, allowing for centralized modification, management, and verification of registers, improving the efficiency of design and verification personnel.

[0063] In addition, the present invention can also incorporate an automatic test vector generation module, which can input the register type, range, and verification operation to be checked externally at any time. For example, if two related registers A and B change, B should change accordingly within a specified time. After identifying the test requirements, the automatic generation module can automatically generate test vectors and test cases based on the register type, range, and verification operation to be checked externally, and perform incremental compilation and runtime inspection. This further improves flexibility and scalability, not only realizing that when registers are modified and test vectors are added, only the register information file or the test vector template needs to be modified, without modifying the entire system, but also the test vectors can be flexibly determined.

[0064] Beneficial effects: The present invention generates a register model and a register transfer level through a comma-separated value table file. The register transfer level, as an actual register circuit, can be integrated into the design to be tested, facilitating the centralized management of register settings, access, and verification, reducing the register design workload of designers, improving maintenance efficiency, and facilitating unified register verification by verification personnel. At the same time, a general verification methodology environment can be generated. The verification environment will automatically compile the integrated test environment according to the register model and the register transfer level, run the test vector, and finally output the test results. In this way, a register model is automatically generated based on any register information file in the comma-separated value table file format that meets the platform requirements, and mounted to the test environment for operation and test result output. This greatly improves the degree of automation of register model verification, saves register verification time, and improves the verification efficiency of front-end verification.

[0065] See also Figure 2 As shown, in an environment that integrates an automatically generated simplified test environment platform A and an automatically generated register model platform B, the present invention can output the test environment platform and register model-related initialization files by inputting a register information CSV file. After generating test vectors, mounting register components, instantiating register interface modules, and generating a Makefile script for this initialization file, the relevant files generated by the CSV can be integrated into the test environment. The test environment is then automatically compiled, the test vectors are run, and the test results are ultimately output to the user. The following describes the automated test environment integration process in detail.

[0066] Based on the above steps, it can be seen that the present invention can generate a universal verification methodology environment. After the universal verification methodology environment is generated, the test environment is automatically integrated. The specific integration steps are as follows:

[0067] 1. Integrate the register model reg_model generated by platform B into the UVM test environment env and virtualsequencer (a virtual sequence controller used to coordinate multiple physical sequencers (a logical unit used to generate and schedule test transactions) and implement complex scenario verification by dispatching cross-interface collaborative sequences);

[0068] 2. Mount the adapter and predictor in the UVM test environment, and perform related instantiation, connection, and configuration;

[0069] 3. Based on the test template, generate base_test (basic test class, usually used as the base class for all test cases, responsible for environment instantiation, configuration management and common test processes (such as reset initialization)) and three tests for mounting test vectors: reg_access_test, reg_reset_test (a test case for verifying the reset value of the register, calling uvm_reg_hw_reset_seq to check whether the register value after reset is consistent with the model image value), and reg_bit_bash_test (a test case for single-bit control of the register, using uvm_reg_bit_bash_seq to verify the independent read and write functions of each bit);

[0070] 4. Extract the signals in the register interface RTL of the second step: register_top_wrapper (the top-level encapsulation module of the register model, used to map the register model to the physical registers of the DUT) and instantiate them into the th file of the third step to obtain the test envelope; assign initial values to the input signals according to the register information file, connect the output signals to the corresponding signals defined in the th file, and connect the AHB interface signals to the VIP interface signals of the AHB bus for front-door read and write access;

[0071] 5. Generate the file.lst (file list) of the RTL to be tested and the packages related to register test vectors and test cases: reg_pkg (register model package, including definitions of components such as register blocks (reg_block) and adapters, used for centralized management of register-related components), env_pkg (verification environment package, encapsulating component classes such as env, agent, scoreboard, etc. to improve code modularity), and test_pkg (test case package, including definitions and registrations of all test classes (such as base_test and reg_access_test)), which facilitates the integration of the test environment and the use of Makefile for environment compilation and test running;

[0072] 6. Generate a Makefile based on the template, combined with the register model name and path; the Makefile is used to define the compilation process and control the running options;

[0073] 7. Integrate the general verification methodology environment based on test envelope, register model package, verification environment package and test cases.

[0074] Once the test environment is integrated, it automatically compiles and monitors the compilation log. If a compilation failure occurs, the user is prompted to manually modify the test environment based on the compilation log and recompile. After successful compilation, the system automatically runs three test vectors, monitoring the run log and collecting error information. After the run is complete, the test results are printed and a test log file is provided to the user.

[0075] Beneficial Effects: The present invention automatically generates a verification environment that integrates the generated register model and instantiates and connects the register RTL. It then automatically compiles the integrated test environment, runs the test vectors, and finally outputs the test results. This significantly reduces the need for manual configuration and improves the efficiency of register design and verification, providing rapid and accurate feedback on test results. This significantly increases the automation level of register model verification and saves register verification time.

[0076] See also Figure 3 As shown, an embodiment of the present invention provides a register model and a register transfer level generation and testing device, including:

[0077] A file parsing module 11 is used to parse a comma-separated value table file using a register generation platform to generate a register model, a register transfer level, and a register test vector; the comma-separated value table file is a file used to describe register information;

[0078] A test environment integration module 12 is configured to generate a general verification methodology environment using a test environment generation platform, integrate the general verification methodology environment based on a register model, a register transfer level, and register test vectors, and obtain a corresponding integrated test environment;

[0079] The test result output module 13 is used to compile the post-integration test environment. If the compilation is successful, the register test vector is run in the post-integration test environment after the compilation is successful, and the corresponding test result is output.

[0080] Since the embodiments of the device part correspond to the above embodiments, the embodiments of the device part please refer to the description of the embodiments of the method part, and will not be repeated here.

[0081] Beneficial effects: The present invention generates a register model and a register transfer level through a comma-separated value table file. The register transfer level, as an actual register circuit, can be integrated into the design to be tested, facilitating the centralized management of register settings, access, and verification, reducing the register design workload of designers, improving maintenance efficiency, and facilitating unified register verification by verification personnel. At the same time, a general verification methodology environment can be generated. The verification environment will automatically compile the integrated test environment according to the register model and the register transfer level, run the test vector, and finally output the test results. In this way, a register model is automatically generated based on any register information file in the comma-separated value table file format that meets the platform requirements, and mounted to the test environment for operation and test result output. This greatly improves the degree of automation of register model verification, saves register verification time, and improves the verification efficiency of front-end verification.

[0082] Furthermore, an embodiment of the present invention also discloses an electronic device, Figure 4 This is a structural diagram of an electronic device according to an exemplary embodiment. The content in the diagram should not be considered as any limitation on the scope of use of the present invention. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the register model and register transfer level generation and testing method disclosed in any of the aforementioned embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.

[0083] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices. The communication protocol it follows is any communication protocol that can be applied to the technical solution of the present invention and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world. Its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0084] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0085] The operating system 221 is used to manage and control various hardware devices on the electronic device, as well as the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including computer programs capable of implementing the register model and register transfer level generation and testing method disclosed in any of the aforementioned embodiments and executed by the electronic device, the computer program 222 may further include computer programs capable of implementing other specific tasks.

[0086] Furthermore, the present invention also discloses a computer-readable storage medium for storing a computer program; wherein, when executed by a processor, the computer program implements the aforementioned register model and register transfer level generation and testing method. The specific steps of this method can be referred to the corresponding contents disclosed in the aforementioned embodiments and will not be repeated here.

[0087] Furthermore, the present invention also discloses a computer program product, including a computer program / instructions; wherein, when executed by a processor, the computer program / instructions implement the aforementioned register model and register transfer level generation and testing method. The specific steps of this method can be found in the corresponding contents disclosed in the aforementioned embodiments and are not further described here.

[0088] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0089] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0090] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0091] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0092] The technical solution provided by the present invention is introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for generating and testing a register model and a register transfer level, characterized in that: include: Parsing a comma-separated value table file using a register generation platform to generate a register model, a register transfer level, and a register test vector; the comma-separated value table file is a file for describing register information; Generate a universal verification methodology environment using a test environment generation platform, integrate the universal verification methodology environment based on the register model, the register transfer level, and the register test vector, and obtain a corresponding integrated test environment; The post-integration test environment is compiled. If the compilation is successful, the register test vector is run in the post-integration test environment after the compilation is successful, and a corresponding test result is output.

2. The register model and register transfer level generation and testing method according to claim 1, characterized in that: Before parsing the comma separated value table file using the register generation platform, the method further includes: The comma-separated value table file is determined according to the requirements of the register generation platform; the comma-separated value table file includes the name, domain segment, path, access method, address and default value of the register.

3. The register model and register transfer level generation and testing method according to claim 1, characterized in that: The universal verification methodology environment includes a virtual IP configuration file, a universal verification methodology verification environment component, a test case file, and a compilation control script file; Among them, the virtual IP configuration file is used to define the interface and behavior of the bus protocol; the general verification methodology verification environment component is used to mount the environment component of the advanced high-performance bus virtual IP, the virtual IP configuration information, the adapter component of the register model, and the predictor component for verifying whether the actual behavior of the design under test meets the expectations; wherein, the design under test includes the register model and the register transfer level.

4. The register model and register transfer level generation and testing method according to claim 3, characterized in that: The integrating the universal verification methodology environment based on the register model, the register transfer level, and the register test vector includes: Integrating the register model into the general verification methodology verification environment component and virtual sequence controller; Mounting the adapter component and the predictor component in the universal verification methodology environment, and performing corresponding instantiation, connection, and configuration operations on the adapter component and the predictor component; Generate a basic test class and a test case that mounts the register test vector according to a preset test template; Extracting signals in the register transfer level, and instantiating the signals into the test case file to obtain a test envelope; Generate a register model package, a verification environment package, and a test case package according to the register transfer level, the register test vector, and the test case; wherein the register model package is used to centrally manage the register model and the adapter component; the verification environment package is used to encapsulate a universal verification methodology verification environment component; and the test case package is used to encapsulate the basic test class and the test case into the universal verification methodology environment; Generate a compile control script according to a preset template, the name and path of the register model and the compile control script file; The universal verification methodology environment is integrated based on the test envelope, the register model package, the verification environment package, and the test case.

5. The register model and register transfer level generation and testing method according to claim 4, characterized in that: The compiling of the post-integration test environment includes: Compiling the post-integration test environment based on the compilation control script; Correspondingly, after compiling the integrated test environment, the following steps are further included: If the integrated test environment fails to compile, an error message is sent so that the integrated test environment can be modified according to the error message and the compilation log, and the corresponding modified test environment can be compiled.

6. The register model and register transfer level generation and testing method according to any one of claims 1 to 5, characterized in that: Also includes: generating a tool command language file, and running a target test environment according to the tool command language file; The target test environment is the post-integration test environment after successful compilation.

7. The register model and register transfer level generation and testing method according to claim 6, characterized in that: Also includes: During the operation of the target test environment, monitoring the operation log of the target test environment, collecting error information, and generating a corresponding test log; After the target test environment is completed, the test log is output.

8. A device for generating and testing a register model and a register transfer level, characterized in that: include: a file parsing module, configured to parse a comma-separated value table file using a register generation platform to generate a register model, a register transfer level, and a register test vector; the comma-separated value table file is a file for describing register information; a test environment integration module, configured to generate a universal verification methodology environment using a test environment generation platform, integrate the universal verification methodology environment based on the register model, the register transfer level, and the register test vector, and obtain a corresponding integrated test environment; The test result output module is used to compile the post-integration test environment. If the compilation is successful, the register test vector is run in the post-integration test environment after the compilation is successful, and the corresponding test result is output.

9. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the register model and register transfer level generation and testing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the method for generating and testing a register model and a register transfer level according to any one of claims 1 to 7.

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