Self-checking method and device of storage module, chip, medium and product

Abstract

The invention discloses a self-checking method and device for a storage module, a chip, a medium and a product, and the method comprises the steps: obtaining a pre-established first interrupt vector table from a target storage module when a self-checking program is executed on an error-injected storage module and if a trigger instruction error correction error of the error-injected storage module is detected, the target storage module is not injected with errors; and executing an interrupt service program corresponding to the first interrupt vector table. Therefore, when an instruction error correction error occurs, the interrupt vector table is read from the non-error-injected storage module instead of being read from the error-injected memory, so that a CPU (Central Processing Unit) can be prevented from accessing an invalid interrupt vector table to enter a locking state, and a self-checking program can normally run.

Description

Technical Field

[0001] The present application relates to the technical field of computers, and more specifically, to a self-test method, device, chip, medium, and product of a storage module. Background Art

[0002] In related art, the Error Checking and Correcting (ECC) self-check mechanism of a storage module, such as a Random Access Memory (RAM), injects an ECC error through an error injection unit. This error is then triggered by the central processing unit (CPU) accessing any data in the storage module. After the ECC error is triggered, the CPU will run to the exception handler. When executing the exception handler, the CPU first needs to read the interrupt vector table stored in the storage module to enter the interrupt service routine through the interrupt vector table. However, when reading the interrupt vector table at this time, the error injection unit will inject an error into the read data again, causing the CPU to directly enter a locked state. Summary of the Invention

[0003] In view of the above problems, the present application proposes a self-test method, device, chip, medium and product for a storage module, which can reduce the probability of the CPU entering lock when executing the self-test program, so that the self-test program can run normally.

[0004] A first aspect of the present application provides a self-test method for a storage module, the self-test method for the storage module comprising:

[0005] When executing a self-test program on the incorrectly-annotated memory module, if it is detected that the incorrectly-annotated memory module triggers an instruction correction error, obtaining a pre-established first interrupt vector table from a target memory module, wherein the target memory module is not incorrectly-annotated;

[0006] Execute an interrupt service routine corresponding to the first interrupt vector table.

[0007] Optionally, before executing the self-test procedure on the incorrectly injected memory module, the method further includes:

[0008] Creating the first interrupt vector table in the target storage module, and recording the interrupt vector access address as a first storage address, wherein the first storage address is a storage address of the first interrupt vector table in the target storage module;

[0009] Accordingly, the step of obtaining a pre-established first interrupt vector table from the target storage module includes:

[0010] Acquire the first storage address based on the interrupt vector access address;

[0011] The first interrupt vector table is obtained based on the first storage address.

[0012] Optionally, the record interrupt vector access address is a first storage address, including:

[0013] The second storage address originally pointed to by the interrupt vector access address is converted into the first storage address, wherein the second storage address is the storage address of the second interrupt vector table in the non-error-annotated storage module.

[0014] Optionally, the first interrupt vector table is the same as the second interrupt vector table, or the first interrupt vector table points to the entry addresses of all interrupt service routines required by the self-test program, and the second interrupt vector table points to the entry addresses of all interrupt service routines of all applications pre-defined by the system.

[0015] Optionally, the record interrupt vector access address is a first storage address, including:

[0016] The interrupt vector access address is recorded in a designated register as the first storage address.

[0017] Optionally, the method further includes:

[0018] After the self-test program is executed, the address pointed to by the interrupt vector access address is restored to the second storage address.

[0019] Optionally, the method further includes:

[0020] After executing the self-test program, the storage space corresponding to the first storage address in the target storage module is released.

[0021] A second aspect of the present application provides a self-test device for a storage module, comprising:

[0022] an acquisition module configured to, when executing a self-test program on an incorrectly-annotated memory module, acquire a pre-established first interrupt vector table from a target memory module if it is detected that the incorrectly-annotated memory module triggers an instruction correction error, wherein the target memory module is not incorrectly-annotated;

[0023] An execution module is used to execute an interrupt service program corresponding to the first interrupt vector table.

[0024] A third aspect of the present application provides a chip, comprising: a memory and a processor; the memory stores a computer program, and when the computer program is executed by the processor, the steps of the self-test method of the above-mentioned storage module are implemented.

[0025] A fourth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the self-test method of the above-mentioned storage module when the computer program is executed by a processor.

[0026] A fifth aspect of the present application provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, implements the steps of the self-test method of the above-mentioned storage module.

[0027] The memory module self-test method, device, chip, medium, and product provided by the embodiments of the present application are configured such that, when executing a self-test program on an incorrectly annotated memory module, if it is detected that the incorrectly annotated memory module has triggered an instruction correction error, a pre-established first interrupt vector table is retrieved from a target memory module, where the target memory module has not been incorrectly annotated; and an interrupt service routine corresponding to the first interrupt vector table is then executed. Thus, when an instruction correction error occurs, the interrupt vector table is read from the non-incorrectly annotated memory module rather than from the incorrectly annotated memory module, thereby preventing the CPU from accessing an invalid interrupt vector table and entering a lockup state, thereby allowing the self-test program to operate normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following is a brief introduction to the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments and drawings obtained by ordinary technicians in this field without creative work are within the scope of protection of this invention.

[0029] Figure 1 1 is a flow chart of a self-test method for a storage module provided in one embodiment of the present application;

[0030] Figure 2 is a flowchart of a self-test method for a storage module provided in another embodiment of the present application;

[0031] Figure 3 This is a structural block diagram of a self-test device for a storage module provided in an embodiment of the present application;

[0032] Figure 4 This is a structural block diagram of the chip provided in the embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limiting this application. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0034] In the following description, references to "some embodiments" describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. In the following description, the term "plurality" refers to at least two.

[0035] In the following description, the terms "first\second" are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0037] In related art, the Error Checking and Correcting (ECC) self-check mechanism of a storage module, such as a Random Access Memory (RAM), injects an ECC error through an error injection unit. The ECC error is then triggered by the central processing unit (CPU) accessing any data in the storage module. After the ECC error is triggered, the CPU will run to the hard fault exception handler. When executing the exception handler, the CPU first needs to read the interrupt vector table in the storage module to enter the entry address of the interrupt service routine (or interrupt service function) through the interrupt vector table. However, when reading the interrupt vector table at this time, the error injection unit will inject an error into the read data again, causing the CPU to directly enter a locked state.

[0038] To solve the above problems, an embodiment of the present application provides a self-test method for a storage module. The execution subject of the self-test method of the storage module can be an electronic chip, a computer device, a self-test device of the storage module, a processor (i.e., CPU) in the computer device / electronic chip, etc. The self-test method of the storage module of this embodiment is explained below using the CPU as an example of the execution subject.

[0039] See Figure 1 , Figure 1 : is a flowchart of a self-test method for a storage module provided in this embodiment. The self-test method for the storage module includes steps S11 to S12:

[0040] Step S11, when executing a self-test program on the incorrectly-annotated memory module, if it is detected that the incorrectly-annotated memory module triggers an instruction correction error, a pre-established first interrupt vector table is obtained from a target memory module, wherein the target memory module is not incorrectly-annotated.

[0041] In this embodiment, the memory module may be RAM, static random-access memory (SRAM), or dynamic random access memory (DRAM). A self-test program is pre-designed to inject ECC errors into the memory module with the error injection to complete the self-test. The target memory module is any memory module that has not been injected with the error. The target memory module may be RAM, SRAM, SRAM, or other types of memory.

[0042] In this embodiment, the mis-annotated storage module stores an interrupt vector table (i.e., a second interrupt vector table; hereinafter, the interrupt vector table stored in the mis-annotated storage module will be uniformly referred to as the "second interrupt vector table"). Since the mis-annotation mechanism of the mis-annotation unit can cover any location in the mis-annotated storage module, when the CPU mis-annotates the mis-annotated storage module through the mis-annotation unit, the mis-annotation unit will synchronously perform mis-annotation when subsequently reading data at any location in the mis-annotated storage module. Therefore, when the CPU reads the second interrupt vector table, the second interrupt vector table obtained by the CPU has already been mis-annotated. If the CPU obtains an exception handler through the second interrupt vector table, it will fall into an invalid address or error handler, causing the CPU to enter a locked state. To this end, this embodiment prevents the CPU from entering a locked state by pre-creating an interrupt vector table (i.e., a first interrupt vector table; hereinafter, the interrupt vector table in the target storage module will be referred to as the "first interrupt vector table") in the target storage module that has not been mis-annotated, and reading the first interrupt vector table from the target storage module to obtain a valid interrupt vector table.

[0043] Instruction error correction refers to bit-level data corruption that occurs during storage or data transmission in a storage system. The Interrupt Vector Table (IVT) stores the entry points for interrupt service routines. Each interrupt source corresponds to a vector, or address. When the CPU receives an interrupt request, it searches the IVT based on the interrupt number and jumps to the corresponding processing function.

[0044] In some embodiments, the first interrupt vector table may be dynamically or temporarily created before executing a self-test procedure on the memory module with an error, or the first interrupt vector table may be pre-created and permanently stored in the target memory module.

[0045] In some embodiments, the first interrupt vector table may point to entry addresses of all interrupt service routines of all applications predefined by the system, or the first interrupt vector table only defines entry addresses of all interrupt service routines required by the self-test program.

[0046] In an embodiment of the present application, an implementation scheme for obtaining a pre-established first interrupt vector table from a target storage module includes:

[0047] In one embodiment, when it is detected that the error injection module triggers an instruction error correction error, the access address of the interrupt vector table (hereinafter referred to as the "interrupt vector access address") is redirected to the storage address of the first interrupt vector table in the target storage module (i.e., the first storage address, hereinafter collectively referred to as the "first storage address"), and the target storage module is accessed through the first storage address to obtain the first interrupt vector table. Specifically, by default (i.e., the error injection storage module has not caused other operational errors such as an instruction error correction error), the interrupt vector access address is set to the storage address of the second interrupt vector table in the non-error injection storage module (i.e., the second storage address, hereinafter collectively referred to as the "second storage address"). When an instruction error correction error or other error occurs, the CPU automatically redirects the interrupt vector access address to the first storage address.

[0048] In another embodiment, when an error-injected memory module triggers an instruction error correction error, the first memory address is obtained based on the interrupt vector access address, wherein the CPU changes the second memory address pointed to by the interrupt vector access address to the first memory address before the self-test procedure begins. That is, the CPU modifies the interrupt vector access address before the error-injected memory module executes the self-test procedure.

[0049] Step S12: executing the interrupt service routine corresponding to the first interrupt vector table.

[0050] In some embodiments, the first interrupt vector table points to multiple interrupt service programs, and the CPU can execute multiple interrupt service programs in sequence. During the execution of each interrupt service program, the CPU will determine whether the error information reported by the erroneous storage module is consistent with the error information set by the self-test program; if they are consistent, the current exception handling program will be jumped out and the subsequent process of the self-test program will be executed until the self-test program is completed.

[0051] In one embodiment, if the first interrupt vector table points to the entry addresses of all interrupt service routines of all applications pre-defined by the system, the CPU, based on multiple interrupt signals reported by the mis-annotated storage module, then traverses the interrupt service routine entry address corresponding to each interrupt signal in the first interrupt vector table for each interrupt signal, and then finds the corresponding interrupt service routine based on the interrupt service routine entry address and executes the corresponding interrupt service routine.

[0052] In another embodiment, if the first interrupt vector table points to the entry addresses of all interrupt service routines required by the self-test program, the CPU can traverse the entry address of each interrupt service routine in the first interrupt vector table, and obtain the corresponding interrupt service routine based on the entry address of the interrupt service routine, and then execute the corresponding interrupt service routine.

[0053] This embodiment, when executing a self-test program on an incorrectly-annotated memory module, detects that the incorrectly-annotated memory module has triggered an instruction error correction. It then retrieves a pre-established first interrupt vector table from a target memory module, which is not incorrectly-annotated, and then executes an interrupt service routine corresponding to the first interrupt vector table. Thus, when an instruction error correction error occurs, the interrupt vector table is read from the non-incorrectly-annotated memory module rather than from the incorrectly-annotated memory module. This prevents the CPU from accessing an invalid interrupt vector table and potentially locking up, allowing the self-test program to operate normally.

[0054] In order to optimize the storage space of the CPU, this embodiment optimizes the implementation scheme of creating the first interrupt vector table for the target storage module. Specifically, before step S11 of this embodiment, that is, before executing the self-test program for the incorrectly injected storage module, step S10 is also included:

[0055] Step S10: creating a first interrupt vector table in the target storage module, and recording the interrupt vector access address as a first storage address, wherein the first storage address is the storage address of the first interrupt vector table in the target storage module.

[0056] In some embodiments, the CPU can record the interrupt vector access address as the first storage address in a designated register, or the CPU can record the interrupt vector access address as the first storage address in other storage modules, where the other storage modules are other storage modules except the mis-annotated storage module and the target storage module, and the type of the storage module can be RAM, SRAM or other types.

[0057] Accordingly, the above step S11 may include steps S111 to S112:

[0058] Step S111 : obtaining a first storage address based on the interrupt vector access address.

[0059] Specifically, since the interrupt vector access address now points to the first storage address, the CPU can obtain the first storage address by accessing the interrupt vector access address.

[0060] Step S112: Obtain a first interrupt vector table based on the first storage address.

[0061] After obtaining the first storage address, the CPU performs address access based on the first storage address to obtain a first interrupt vector table.

[0062] More specifically, in the above step S10, recording the interrupt vector access address as the first storage address may include:

[0063] The second storage address originally pointed to by the interrupt vector access address is converted into a first storage address, wherein the second storage address is the storage address of the second interrupt vector table in the mis-annotated storage module.

[0064] In this embodiment, the original interrupt vector access address points to the storage address of the second interrupt vector table, namely the second storage address. In order to prevent the CPU from accessing the incorrectly-annotated second interrupt vector table and entering a lock state when executing the self-test program, the CPU changes the address pointed to by the interrupt vector access address from the second storage address to the first storage address before starting to execute the self-test program, so as to change the interrupt vector access address to an address in the target storage module that is not incorrectly annotated.

[0065] In some embodiments, the first interrupt vector table is the same as the second interrupt vector table, or the first interrupt vector table points to the entry addresses of all interrupt service routines required by the self-test program, and the second interrupt vector table points to the entry addresses of all interrupt service routines of all applications pre-defined by the system.

[0066] This embodiment creates a first interrupt vector table in the target storage module that is not incorrectly annotated before the self-test program starts, and sets the interrupt vector access address to the first storage address corresponding to the first interrupt vector table. Therefore, when the CPU enters the interrupt service program, the interrupt vector is read from the target storage module that is not incorrectly annotated, thereby preventing the CPU from entering a deadlock state.

[0067] Based on the above-mentioned implementation scheme, in one embodiment, the self-test method of the storage module provided in this embodiment may further include:

[0068] After the self-test program is executed, the storage space corresponding to the first storage address in the target storage module is released.

[0069] That is, this embodiment temporarily creates a first interrupt vector table in the target storage module before the self-test program starts. After the self-test program is completed, the storage space corresponding to the second interrupt vector table dedicated to the self-test program is cleared. This is to optimize storage space and to prevent subsequent misaccess by other services.

[0070] Based on the above-mentioned implementation scheme, in one embodiment, the self-test method of the storage module provided in this embodiment may further include:

[0071] After the self-test program is executed, the address pointed to by the interrupt vector access address is restored to the second storage address.

[0072] Since the interrupt vector access address is set to the first storage address corresponding to the first interrupt vector table when executing the self-test program, and the first interrupt vector table is specifically used for the self-test program, in order to avoid other subsequent service programs from mistakenly accessing the first storage address, at this time, the interrupt vector access address needs to be restored to the storage address of the second interrupt vector table, that is, the second storage address, so that other subsequent service programs can run normally.

[0073] In order to more clearly illustrate the process of the self-test method of the storage module provided in the embodiment of the present application, please refer to Figure 2 , Figure 2 1 is a flow chart of a self-test method for a storage module according to another embodiment of the present application. The method includes:

[0074] Step S1, before the self-test program starts, the interrupt vector required by the self-test program, ie, the first interrupt vector table, is stored in a target storage module that is not incorrectly annotated, and the interrupt vector access address in the instruction register is modified to the first storage address.

[0075] Step S2, error-annotate the memory module with the error, and after the error-annotation is completed, trigger an instruction error correction by accessing any data in the memory module with the error through the CPU.

[0076] Step S3, running the exception handling program: obtaining the first interrupt vector table in the target storage module by accessing the interrupt vector access address in the designated register, and entering the multiple interrupt service routines pointed to by the first interrupt vector table.

[0077] Step S4, executing multiple interrupt service programs in sequence, and determining during the execution process whether the specific error information reported by the error-annotated storage module is consistent with the error information preset by the self-test program.

[0078] Step S5: When the information is consistent, exit the exception handling program and continue to execute the subsequent self-check program.

[0079] Step S6: After all self-test programs are executed, the storage space of the first interrupt vector table in the target storage module is released, and the interrupt vector access address is restored to the second storage address, and the subsequent application program is continued to be executed.

[0080] In other embodiments, before step S11 above, that is, before executing the self-test program on the memory module with the error, the process may further include: creating a first interrupt vector table in the target memory module, and recording the first interrupt vector access address as the first storage address, and the second interrupt vector access address as the second storage address. The first interrupt vector access address is set to the interrupt vector access address when an instruction error correction error occurs; and the second interrupt vector access address is set to the interrupt vector access address when no instruction error correction error occurs. Thus, step S11 above may include: obtaining the first storage address based on the first interrupt vector access address, and obtaining the first interrupt vector table based on the first storage address.

[0081] Accordingly, the present application also provides a self-test device for a storage module. Figure 3 , Figure 3 3 is a structural block diagram of a self-checking device for a storage module according to an embodiment of the present application. The self-checking device 3 for a storage module according to this embodiment includes an acquisition module 31 and an execution module 32.

[0082] The acquisition module 31 is configured to acquire a pre-established first interrupt vector table from a target memory module if a correction error is detected when a self-test is executed on the memory module with an error, wherein the target memory module is not error-annotated.

[0083] The execution module 32 is configured to execute the interrupt service routine corresponding to the first interrupt vector table.

[0084] In one embodiment, the self-test device 3 of the storage module may further include a creation module, which is used to create a first interrupt vector table in the target storage module before executing the self-test program on the incorrectly injected storage module, and record the interrupt vector access address as the first storage address, wherein the first storage address is the storage address of the first interrupt vector table in the target storage module.

[0085] Correspondingly, the acquisition module 31 is further configured to: acquire a first storage address based on the interrupt vector access address; and acquire a first interrupt vector table based on the first storage address.

[0086] In one embodiment, the creation module is further configured to convert a second storage address originally pointed to by the interrupt vector access address into a first storage address, wherein the second storage address is a storage address of a second interrupt vector table in the target storage module.

[0087] In one embodiment, the first interrupt vector table is the same as the second interrupt vector table, or the first interrupt vector table points to the entry addresses of all interrupt service routines required by the self-test program, and the second interrupt vector table points to the entry addresses of all interrupt service routines of all applications predefined by the system.

[0088] In one embodiment, the creation module is further configured to: record the interrupt vector access address as the first storage address in a designated register.

[0089] In one embodiment, the self-test device of the storage module further includes a restoration module, and the restoration module is used to restore the address pointed to by the interrupt vector access address to the second storage address after executing the self-test program.

[0090] In one embodiment, the self-test device of the storage module further includes a release module, and the release module is used to release the storage space corresponding to the first storage address in the target storage module after executing the self-test program.

[0091] In addition, the present application also provides a chip. Figure 4 , Figure 4 It is a structural block diagram of the chip of an embodiment of the present application. The chip 4 includes a memory 41, a processor 40 and a computer program 42 stored in the memory and runnable on the processor. In addition, the chip 4 also includes an error-annotated storage module and a target storage module, wherein the error-annotated storage module stores a second interrupt vector table. When the computer program 42 is executed by the processor, the steps of the self-test method of the storage module provided in the above embodiment are implemented.

[0092] Since this computer program adopts all the technical solutions of all the aforementioned embodiments when executed by the processor, it has at least all the beneficial effects brought about by all the technical solutions of all the aforementioned embodiments, which will not be described one by one here.

[0093] In addition, an embodiment of the present application further provides a computer-readable storage medium, on which a computer processing program is stored. When the computer processing program is executed by a processor, the steps of the self-test method of the storage module as described above are implemented.

[0094] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0095] The computer-readable storage medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0096] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by an electronic device, the electronic device executes: when executing a self-test program on an incorrectly-annotated storage module, if it is detected that the incorrectly-annotated storage module triggers an instruction correction error, a pre-established first interrupt vector table is obtained from a target storage module, wherein the target storage module is not incorrectly-annotated; and an interrupt service program corresponding to the first interrupt vector table is executed.

[0097] Computer program code for performing the operations of the present application may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages such as Java, Smalltalk, C++, and conventional procedural programming languages such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0098] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0099] Since this computer program adopts all the technical solutions of all the aforementioned embodiments when executed by the processor, it has at least all the beneficial effects brought about by all the technical solutions of all the aforementioned embodiments, which will not be described one by one here.

[0100] In addition, an embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of the self-test method of the storage module provided in the above embodiment are implemented.

[0101] Since this computer program adopts all the technical solutions of all the aforementioned embodiments when executed by the processor, it has at least all the beneficial effects brought about by all the technical solutions of all the aforementioned embodiments, which will not be described one by one here.

[0102] Compared to the prior art, the self-test method, device, chip, medium, and product for a storage module provided in the embodiments of the present application, when executing a self-test program on an incorrectly annotated storage module, if it is detected that the incorrectly annotated storage module triggers an instruction correction error, then obtains a pre-established first interrupt vector table from a target storage module, where the target storage module is not incorrectly annotated; and executes an interrupt service routine corresponding to the first interrupt vector table. Thus, when an instruction correction error occurs, the interrupt vector table is read from the non-incorrectly annotated storage module rather than from the incorrectly annotated memory, which can prevent the CPU from accessing an invalid interrupt vector table and entering a lock state, thereby allowing the self-test program to operate normally.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A self-test method for a storage module, characterized in that: include: When executing a self-test program on the incorrectly-annotated memory module, if it is detected that the incorrectly-annotated memory module triggers an instruction correction error, obtaining a pre-established first interrupt vector table from a target memory module, wherein the target memory module is not incorrectly-annotated; Execute an interrupt service routine corresponding to the first interrupt vector table.

2. The self-test method of the storage module according to claim 1, wherein: Before executing the self-test procedure on the memory module with the error injection, the method further includes: Creating the first interrupt vector table in the target storage module, and recording the interrupt vector access address as a first storage address, wherein the first storage address is a storage address of the first interrupt vector table in the target storage module; Accordingly, the step of obtaining a pre-established first interrupt vector table from the target storage module includes: Acquire the first storage address based on the interrupt vector access address; The first interrupt vector table is obtained based on the first storage address.

3. The self-test method of the storage module according to claim 2, wherein: The recording interrupt vector access address is a first storage address, including: The second storage address originally pointed to by the interrupt vector access address is converted into the first storage address, wherein the second storage address is the storage address of the second interrupt vector table in the non-error-annotated storage module.

4. The self-test method of the storage module according to claim 3, wherein: The first interrupt vector table is the same as the second interrupt vector table, or the first interrupt vector table points to the entry addresses of all interrupt service programs required by the self-test program, and the second interrupt vector table points to the entry addresses of all interrupt service programs of all applications predefined by the system.

5. The self-test method of the storage module according to claim 2, wherein: The recording interrupt vector access address is a first storage address, including: The interrupt vector access address is recorded in a designated register as the first storage address.

6. The self-test method for a storage module according to any one of claims 2 to 5, wherein: The method further comprises: After the self-test program is executed, the address pointed to by the interrupt vector access address is restored to the second storage address.

7. The self-test method for a storage module according to any one of claims 2 to 5, wherein: The method further comprises: After executing the self-test program, the storage space corresponding to the first storage address in the target storage module is released.

8. A self-test device for a storage module, characterized in that: include: an acquisition module configured to, when executing a self-test program on an incorrectly-annotated memory module, acquire a pre-established first interrupt vector table from a target memory module if it is detected that the incorrectly-annotated memory module triggers an instruction correction error, wherein the target memory module is not incorrectly-annotated; An execution module is used to execute an interrupt service program corresponding to the first interrupt vector table.

9. A chip, characterized in that: include: memory and processor; The memory stores a computer program, which, when executed by the processor, implements the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

11. A computer program product, comprising a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

Images