Key integrity verification method and system, medium and program product

Abstract

The invention discloses a secret key integrity verification method and system, a medium and a program product, and belongs to the technical field of secret key verification. The method is used for an SoC security system and comprises the following steps: an initialization stage: electrifying a load board of test equipment, and then releasing external global reset of a chip; in the verification stage, a secret key SM3 verification value programming test sequence is operated, and secret key integrity verification is carried out by using an SM3 algorithm; in the testing stage, a secret key SM3 verification value test is carried out, whether the secret key SM3 verification value test is passed or not is judged, if the secret key SM3 verification value test is passed, it is judged that the chip is a good product, other chip tests continue to be carried out, and if the secret key SM3 verification value test is not passed, it is judged that the chip is a defective product. According to the invention, the secret key stored in the OTP / eFuse component is verified through the SM3 security algorithm, and the verification value is stored in the OTP / eFuse component, so that the algorithm verification of the integrity of the secret key is realized, and the security and the reliability are greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of key verification technology, and in particular to a key integrity verification method, system, medium and program product. Background Art

[0002] With the rapid development of IoT (Internet of Things) and artificial intelligence technologies, the security and reliability of chip data storage are becoming increasingly important. This has led to the widespread application of eFuse or OTP (One-Time Programmable) devices in embedded SoC (System on Chip) chips. OTP, as a non-volatile memory device, is a one-time programmable device with high reliability, strong stability, and radiation resistance. Once programmed, data is permanently stored for the life of the OTP, immune to external interference and tampering.

[0003] However, eFuse or OTP still presents reliability risks. The values read from them may change after long-term aging, exposure to cosmic rays, and other factors. Therefore, redundancy is often implemented, such as mapping a 2-bit physical address to a 1-bit logical address to enhance storage reliability by adding redundant bits. Existing technologies only use simple techniques to reduce reliability risks. They cannot intuitively determine whether a storage bit flip has occurred, cannot perform error correction when a bit flip occurs, and lack security algorithms to guarantee storage reliability. This makes their application in the security chip field insufficiently secure. Summary of the Invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide a key integrity verification method, system, medium and program product.

[0005] The object of the present invention is achieved through the following technical solutions: In a first aspect, the present invention provides: a key integrity verification method for a SoC security system, comprising the following steps: During the initialization phase, the load board of the test equipment is powered on, and then the external global reset of the chip is released; During the verification phase, the key SM3 verification value programming test sequence is run, and the SM3 algorithm is used to verify the key integrity. During the testing phase, the key SM3 check value test is performed to determine whether the key SM3 check value test passes. If the key SM3 check value test passes, the chip is judged to be a good product and other chip tests are continued. If the key SM3 check value test fails, the chip is judged to be a defective product.

[0006] Preferably, the SoC security system includes: CPU component, the CPU component is connected to the AHB2CFG component, the AHB2CFG component is connected to the CFG_ARB component, the CFG_ARB component is connected to the ATE_RW_REG component and the CFG_DEC component; the ATE_RW_REG component is connected to the TAP_CTRL component, the TAP_CTRL component is connected to the JTAG component; the CFG_DEC component is connected to the OTP_CTRL component, the TRNG component and the SM3 component, the OTP_CTRL component is connected to the OTP / eFuse component, the TRNG component and the SM3 component; The CPU component is used to control the operation process, implement security policies and manage keys of the SoC security system; The AHB2CFG component is used to convert the AHB bus into a configuration register bus; The CFG_ARB component is used to perform polling arbitration operations on different register operation masters. In the ATE test scenario, only the ATE_RW_REG component is allowed to read and write SoC registers. The ATE_RW_REG component is used to convert the JTAG bus protocol into a SoC private register read and write control bus. During ATE testing, the registers of the components required for the test are configured through the JTAG component. The CFG_DEC component is used to decode register read and write addresses and route register read and write requests to various target components; The TAP_CTRL component is used to implement the JTAG protocol according to the JTAG signal and communicate with the ATE_RW_REG component; The JTAG component is used to physically connect the JTAG pin to the ATE machine; The OTP_CTRL component is used to implement read and write operations, authority management and CPU command processing on the OTP / eFuse component; The TRNG component is used to generate true random numbers; The SM3 component is used to perform hash operations on data; The OTP / eFuse component is used to store chip PUF value, chip ID information, simulated IP verification value, firmware information and various keys.

[0007] Preferably, the testing equipment is an ATE machine or a CPU.

[0008] Preferably, when the test equipment is an ATE machine, the verification stage includes the following steps: The command configured in the SM3 command register of the ATE machine is a key hash command; The SM3 component reads the key area of the OTP / eFuse component and temporarily stores the read key in the SM3 component; The SM3 component performs a hash operation on the key and temporarily stores the hash value in the SM3 component; The SM3 component triggers the OTP_CTRL component to program the hash value; The OTP_CTRL component programs the hash value of the key into the designated area of the OTP / eFuse component; After the OTP_CTRL component completes the programming operation, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of the successful completion of the command to the SM3 status register; The ATE machine reads the successful completion status value of the SM3 status register, confirming that the hash value of the key has been written to the OTP / eFuse component.

[0009] Preferably, when the test device is a CPU, the verification stage includes the following steps: The command of the CPU configuration SM3 command register is the key verification command; The SM3 component reads the key area of the OTP / eFuse component and temporarily stores the read key in the SM3 component; The SM3 component reads the key verification area of the OTP / eFuse component and temporarily stores the read key verification value in the SM3 component; The SM3 component performs a hash operation on the key to generate a hash value of the key; The SM3 component compares the hash value calculated by the SM3 component with the check value. If the comparison passes, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of successful command completion to the SM3 status register. The CPU reads the returned check status value to confirm that the SM3 check is successful. If the comparison fails, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of failed comparison to the SM3 status register. The CPU reads the returned check status value to confirm that the SM3 check fails.

[0010] Preferably, when the test device is an ATE machine, the verification phase is performed by configuring the SM3 register through the JTAG component; when the test device is a CPU, the verification phase is performed by directly configuring the SM3 register through the CPU.

[0011] A second aspect of the present invention provides: a key integrity verification system, configured to implement any of the above-mentioned key integrity verification methods, comprising: Initialization module, used to power on the load board of the test equipment and then release the external global reset of the chip; Verification module, used to run the key SM3 verification value programming test sequence and use the SM3 algorithm to perform key integrity verification; The test module is used to perform the key SM3 check value test to determine whether the key SM3 check value test passes. If the key SM3 check value test passes, the chip is judged to be a good product and other chip tests are continued. If the key SM3 check value test fails, the chip is judged to be a defective product.

[0012] A third aspect of the present invention provides: a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by a processor, any of the above-mentioned key integrity verification methods is implemented.

[0013] A fourth aspect of the present invention provides: a computer program product comprising instructions, wherein when the computer program product is run on a terminal, the terminal is enabled to execute any one of the above-mentioned key integrity verification methods.

[0014] The beneficial effects of the present invention are: 1) The present invention verifies the key stored in the OTP / eFuse component through the national secret SM3 security algorithm and stores the verification value in the OTP / eFuse component, realizing algorithm verification of key integrity and greatly improving security and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is the functional block diagram of the SoC security system. DETAILED DESCRIPTION

[0016] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work shall fall within the scope of protection of the present invention.

[0017] See Figure 1 The first aspect of the present invention provides: a key integrity verification method for a SoC security system, comprising the following steps: During the initialization phase, the load board of the test equipment is powered on, and then the external global reset of the chip is released; During the verification phase, the key SM3 verification value programming test sequence is run, and the SM3 algorithm is used to verify the key integrity. During the testing phase, the key SM3 check value test is performed to determine whether the key SM3 check value test passes. If the key SM3 check value test passes, the chip is judged to be a good product and other chip tests are continued. If the key SM3 check value test fails, the chip is judged to be a defective product.

[0018] In this embodiment, there are two ways to program the verification value in the verification phase: ATE (Automatic Test Equipment) machine programming and CPU programming. The keys to be verified include root keys and other types of keys.

[0019] In some embodiments, the SoC security system includes: CPU component, the CPU component is connected to the AHB2CFG component, the AHB2CFG component is connected to the CFG_ARB component, the CFG_ARB component is connected to the ATE_RW_REG component and the CFG_DEC component; the ATE_RW_REG component is connected to the TAP_CTRL component, the TAP_CTRL component is connected to the JTAG component; the CFG_DEC component is connected to the OTP_CTRL component, the TRNG component and the SM3 component, the OTP_CTRL component is connected to the OTP / eFuse component, the TRNG component and the SM3 component; The CPU component is used to control the operation process, implement security policies and manage keys of the SoC security system; The AHB2CFG component is used to convert the AHB bus into a configuration register bus; The CFG_ARB component is used to perform polling arbitration operations on different register operation masters. In the ATE test scenario, only the ATE_RW_REG component is allowed to read and write SoC registers. The ATE_RW_REG component is used to convert the JTAG bus protocol into a SoC private register read and write control bus. During ATE testing, the registers of the components required for the test are configured through the JTAG component. The CFG_DEC component is used to decode register read and write addresses and route register read and write requests to various target components; The TAP_CTRL component is used to implement the JTAG protocol according to the JTAG signal and communicate with the ATE_RW_REG component; The JTAG component is used to physically connect the JTAG pin to the ATE machine; The OTP_CTRL component is used to implement read and write operations, authority management and CPU command processing on the OTP / eFuse component; The TRNG component is used to generate true random numbers; The SM3 component is used to perform hash operations on data; The OTP / eFuse component is used to store chip PUF value, chip ID information, simulated IP verification value, firmware information and various keys.

[0020] In some embodiments, the testing equipment is an ATE machine or a CPU.

[0021] In some embodiments, when the test equipment is an ATE machine, the verification phase includes the following steps: The command configured in the SM3 command register of the ATE machine is a key hash command; The SM3 component reads the key area of the OTP / eFuse component and temporarily stores the read key in the SM3 component; The SM3 component performs a hash operation on the key and temporarily stores the hash value in the SM3 component; The SM3 component triggers the OTP_CTRL component to program the hash value; The OTP_CTRL component programs the hash value of the key into the designated area of the OTP / eFuse component; After the OTP_CTRL component completes the programming operation, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of the successful completion of the command to the SM3 status register; The ATE machine reads the successful completion status value of the SM3 status register, confirming that the hash value of the key has been written to the OTP / eFuse component.

[0022] In this embodiment, the process information includes the root key or other keys, hash values, etc. that have been temporarily stored in the hardware. The hash value generation and hash value comparison process of other keys are similar to those of the keys and will not be repeated here.

[0023] In some embodiments, when the test device is a CPU, the verification phase includes the following steps: The command of the CPU configuration SM3 command register is the key verification command; The SM3 component reads the key area of the OTP / eFuse component and temporarily stores the read key in the SM3 component; The SM3 component reads the key verification area of the OTP / eFuse component and temporarily stores the read key verification value in the SM3 component; The SM3 component performs a hash operation on the key to generate a hash value of the key; The SM3 component compares the hash value calculated by the SM3 component with the check value. If the comparison passes, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of successful command completion to the SM3 status register. The CPU reads the returned check status value to confirm that the SM3 check is successful. If the comparison fails, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of failed comparison to the SM3 status register. The CPU reads the returned check status value to confirm that the SM3 check fails.

[0024] In some embodiments, when the test device is an ATE machine, the verification phase is performed by configuring the SM3 register through the JTAG component; when the test device is a CPU, the verification phase is performed by directly configuring the SM3 register through the CPU.

[0025] A second aspect of the present invention provides: a key integrity verification system, configured to implement any of the above-mentioned key integrity verification methods, comprising: Initialization module, used to power on the load board of the test equipment and then release the external global reset of the chip; Verification module, used to run the key SM3 verification value programming test sequence and use the SM3 algorithm to perform key integrity verification; The test module is used to perform the key SM3 check value test to determine whether the key SM3 check value test passes. If the key SM3 check value test passes, the chip is judged to be a good product and other chip tests are continued. If the key SM3 check value test fails, the chip is judged to be a defective product.

[0026] A third aspect of the present invention provides: a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by a processor, any of the above-mentioned key integrity verification methods is implemented.

[0027] A fourth aspect of the present invention provides: a computer program product comprising instructions, wherein when the computer program product is run on a terminal, the terminal is enabled to execute any one of the above-mentioned key integrity verification methods.

[0028] The foregoing description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein and should not be construed as excluding other embodiments. Rather, the present invention can be used in various other combinations, modifications, and environments and can be modified within the scope of the concept described herein through the above teachings or techniques or knowledge in the relevant field. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention are intended to be protected by the appended claims.

Claims

1. A key integrity verification method, characterized in that: For SoC security system, including the following steps: During the initialization phase, the load board of the test equipment is powered on, and then the external global reset of the chip is released; During the verification phase, the key SM3 verification value programming test sequence is run, and the SM3 algorithm is used to verify the key integrity. During the testing phase, the key SM3 check value test is performed to determine whether the key SM3 check value test passes. If the key SM3 check value test passes, the chip is judged to be a good product and other chip tests are continued. If the key SM3 check value test fails, the chip is judged to be a defective product.

2. The key integrity verification method according to claim 1, wherein: The SoC security system includes: CPU component, the CPU component is connected to the AHB2CFG component, the AHB2CFG component is connected to the CFG_ARB component, the CFG_ARB component is connected to the ATE_RW_REG component and the CFG_DEC component; the ATE_RW_REG component is connected to the TAP_CTRL component, the TAP_CTRL component is connected to the JTAG component; the CFG_DEC component is connected to the OTP_CTRL component, the TRNG component and the SM3 component, the OTP_CTRL component is connected to the OTP / eFuse component, the TRNG component and the SM3 component; The CPU component is used to control the operation process, implement security policies and manage keys of the SoC security system; The AHB2CFG component is used to convert the AHB bus into a configuration register bus; The CFG_ARB component is used to perform polling arbitration operations on different register operation masters. In the ATE test scenario, only the ATE_RW_REG component is allowed to read and write SoC registers. The ATE_RW_REG component is used to convert the JTAG bus protocol into a SoC private register read and write control bus. During ATE testing, the registers of the components required for the test are configured through the JTAG component. The CFG_DEC component is used to decode register read and write addresses and route register read and write requests to various target components; The TAP_CTRL component is used to implement the JTAG protocol according to the JTAG signal and communicate with the ATE_RW_REG component; The JTAG component is used to physically connect the JTAG pin to the ATE machine; The OTP_CTRL component is used to implement read and write operations, authority management and CPU command processing on the OTP / eFuse component; The TRNG component is used to generate true random numbers; The SM3 component is used to perform hash operations on data; The OTP / eFuse component is used to store chip PUF value, chip ID information, simulated IP verification value, firmware information and various keys.

3. The key integrity verification method according to claim 1, wherein: The testing equipment is an ATE machine or a CPU.

4. The key integrity verification method according to claim 3, wherein: When the test equipment is an ATE machine, the verification phase includes the following steps: The command configured in the SM3 command register of the ATE machine is a key hash command; The SM3 component reads the key area of the OTP / eFuse component and temporarily stores the read key in the SM3 component; The SM3 component performs a hash operation on the key and temporarily stores the hash value in the SM3 component; The SM3 component triggers the OTP_CTRL component to program the hash value; The OTP_CTRL component programs the hash value of the key into the designated area of the OTP / eFuse component; After the OTP_CTRL component completes the programming operation, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of the successful completion of the command to the SM3 status register; The ATE machine reads the successful completion status value of the SM3 status register, confirming that the hash value of the key has been written to the OTP / eFuse component.

5. The key integrity verification method according to claim 3, wherein: When the test device is a CPU, the verification phase includes the following steps: The command of the CPU configuration SM3 command register is the key verification command; The SM3 component reads the key area of the OTP / eFuse component and temporarily stores the read key in the SM3 component; The SM3 component reads the key verification area of the OTP / eFuse component and temporarily stores the read key verification value in the SM3 component; The SM3 component performs a hash operation on the key to generate a hash value of the key; The SM3 component compares the hash value calculated by the SM3 component with the check value. If the comparison passes, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of successful command completion to the SM3 status register. The CPU reads the returned check status value to confirm that the SM3 check is successful. If the comparison fails, the SM3 component and the OTP_CTRL component will automatically clear the temporarily stored process information and return the result of failed comparison to the SM3 status register. The CPU reads the returned check status value to confirm that the SM3 check fails.

6. The key integrity verification method according to any one of claims 3 to 5, characterized in that: When the test device is an ATE machine, the SM3 register is configured through the JTAG component to execute the verification phase; when the test device is a CPU, the SM3 register is directly configured through the CPU to execute the verification phase.

7. A key integrity verification system, characterized in that: Used to implement the key integrity verification method according to any one of claims 1 to 6, comprising: Initialization module, used to power on the load board of the test equipment and then release the external global reset of the chip; Verification module, used to run the key SM3 verification value programming test sequence and use the SM3 algorithm to perform key integrity verification; The test module is used to perform the key SM3 check value test to determine whether the key SM3 check value test passes. If the key SM3 check value test passes, the chip is judged to be a good product and other chip tests are continued. If the key SM3 check value test fails, the chip is judged to be a defective product.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by the processor, the key integrity verification method according to any one of claims 1 to 6 is implemented.

9. A computer program product comprising instructions, characterized in that: When the computer program product is run on a terminal, the terminal is enabled to execute the key integrity verification method according to any one of claims 1 to 6.

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