Broadband low-delay high-integration transceiver integrated device

Abstract

The invention discloses a broadband low-delay high-integration-level transmitting and receiving integrated device, and belongs to the technical field of information. According to the method, the acquisition frequency of the ADC and the output frequency of the DAC are planned by adopting a multi-clock switching method, a plurality of clocks are switched by adopting a high-speed switch, the speed can reach a nanosecond level, a high-frequency reference signal can be generally obtained through frequency doubling of a crystal oscillator or a high-integration-level frequency synthesizer chip, the amplitude and phase consistency is very good, and the method is suitable for large-scale popularization and application. Reference phase noise generated by direct frequency doubling of a crystal oscillator is superior to that of a frequency sweeping local oscillator, seamless frequency band coverage is carried out by utilizing three Nyquist intervals of a high-speed digital device, the system hardware complexity is greatly reduced, large-scale multi-channel integration is more facilitated, the signal acquisition and signal generation speed is increased, and the system performance is improved. And the path delay of a signal closed loop is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of information technology, and in particular relates to a broadband, low-latency, highly integrated transceiver device. Background Art

[0002] Wide-bandwidth up / down conversion devices are widely used in broadband, high-speed satellite communications, electromagnetic spectrum signal monitoring, electronic countermeasures, and intersatellite communication simulation testing. They achieve low-distortion conversion between broadband microwave and millimeter-wave signals and wide-bandwidth intermediate frequency signals. Up / down conversion devices have relatively high requirements for test frequency bands, instantaneous bandwidth, group delay distortion, phase noise, and in-band flatness. Traditional transceivers are implemented using up / down conversion. Single-stage frequency conversion offers the advantages of simplicity and low parasitic interference, but signals such as local oscillator leakage, intermodulation, and image frequencies are difficult to filter out. Secondary frequency conversion solutions are slightly more complex, but due to their greater frequency flexibility, signals such as local oscillator leakage, intermodulation, and image frequencies are easily filtered out, making them commonly used.

[0003] Figure 1 The segmented filtering and signal conditioning units in the upconversion module primarily include filters, equalizers, low-noise amplifiers, and voltage-controlled attenuators. The frequency conversion unit primarily includes mixers, amplifiers, filters, equalizers, and voltage-controlled attenuators. The filter conditioning unit primarily includes filters, equalizers, amplifiers, and voltage-controlled attenuators. The upconversion channel's primary function is to use the mixer, the fixed-frequency local oscillator (LO), and the swept-frequency local oscillator (LO) signals to shift the intermediate frequency (IF) signal with a defined bandwidth generated by the DAC to the corresponding RF signal channel. Because the mixer operates by exploiting its nonlinearity, filtering the input signal and each stage of the upconversion module is required to prevent spurious signals such as image frequencies and multiple responses from wideband mixing. After filtering, amplitude equalization is performed to compensate for degradation of the link's in-band flatness. A voltage-controlled attenuator is added to the frequency conversion channel to achieve the required controllable gain of the frequency conversion device. Finally, a broadband power amplifier is used at the output to meet the output power requirements of the upconversion device. Similar to the up-conversion device, the down-conversion device is a reverse frequency conversion process of the up-conversion device. The broadband input signal with a certain bandwidth undergoes signal pre-selection and signal conditioning by the segmented filtering and signal conditioning unit. Through two mixings of the swept frequency local oscillator and the point frequency local oscillator, the RF signal is mixed into an intermediate frequency signal suitable for ADC use. After the noise is filtered out by the filtering and conditioning unit, the data is adopted by the ADC and sent to the FPGA for signal processing.

[0004] In recent years, due to the rapid development of technologies such as phased array radar, multi-channel MIMO, and quantum manipulation, large-bandwidth transceiver devices have the requirements of high integration, multi-channel, high speed, low latency, low phase noise, and high amplitude phase consistency.

[0005] However, traditional integrated signal transmitters and receivers generally use a secondary frequency conversion method, requiring two local oscillators: a point frequency and a swept frequency oscillator. The slow tuning speed of the swept frequency oscillator limits the speed and latency characteristics of the transmit and receive link. Furthermore, the swept frequency oscillator generally uses multiple phase-locked loops to suppress spurious signals, resulting in a complex and costly solution. The design of the secondary frequency conversion pathways, such as filtering, amplification, equalization, and attenuation, is also very complex, bulky, and costly, making it difficult to achieve high integration. The number of integrated channels is relatively small. Furthermore, the high-resolution swept frequency oscillator synthesis method, due to the introduction of a phase-locked loop, makes it difficult to ensure phase and amplitude consistency in broadband conditions. Therefore, calibrating and equalizing the amplitude and phase of the entire system is extremely difficult. Furthermore, traditional integrated signal transmitters and receivers consist of two channels: one transmitter and one receiver. However, some situations require a combination of one transmitter and multiple receivers or one receiver and multiple transmitters, resulting in a lack of flexibility in integrating multiple channels. Summary of the Invention

[0006] In response to the above-mentioned technical problems existing in the prior art, the present invention proposes a broadband, low-latency, highly integrated transceiver device with a reasonable design, which overcomes the shortcomings of the prior art and has good effects.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A broadband, low-latency, highly integrated transceiver device includes a segmented filtering and signal conditioning unit, a high-frequency reference signal generation module, a multi-clock distribution unit, a high-speed switch module, an ADC, a DAC, an FPGA module, and a synchronous trigger unit; wherein,

[0009] The segmented filtering and signal conditioning unit is configured to filter and adjust the amplitude and phase of the DAC output signal and the ADC input signal;

[0010] A high-frequency reference signal generating module is configured to generate a high-frequency reference signal;

[0011] a multi-clock distribution unit configured to receive a high-frequency reference signal and generate clock signals of different frequencies;

[0012] A high-speed switch module is configured to switch the sampling clock frequency of the ADC and the output clock frequency of the DAC to achieve frequency band coverage based on the Nyquist frequency interval;

[0013] The ADC and the DAC are configured to perform frequency planning according to the switched clock signal respectively;

[0014] The FPGA module is configured to perform data transmission, reception, and processing, and utilizes a synchronous bus to ensure signal synchronization;

[0015] The synchronization trigger unit is configured to ensure that the received signal and the transmitted signal remain synchronized, multiple receiving channels and multiple transmitting channels remain synchronized, the signals between multiple receiving channels remain synchronized, and the signals between multiple transmitting channels remain synchronized.

[0016] Preferably, the high-frequency reference signal is obtained by crystal oscillator frequency multiplication or frequency synthesizer chip.

[0017] Preferably, the clock distribution unit generates 2-5 clock signals of different frequencies by direct frequency synthesis, and provides a clock for each frequency.

[0018] Preferably, the high-speed switch module uses a switch with a speed reaching nanosecond level.

[0019] Preferably, the switching action of the high-speed switch module is controlled by the FPGA module to achieve dynamic frequency planning and adaptive frequency band matching.

[0020] Preferably, the FPGA module is interconnected with the ADC and DAC via a high-speed interface, and synchronization between the received signal and the transmitted signal, and synchronous triggering between multiple channels are achieved via a synchronous bus.

[0021] Preferably, the device adopts a synchronous bus for flexible expansion, and supports asymmetric configurations of multiple reception and multiple transmission, one transmission and multiple reception, or one reception and multiple transmission.

[0022] The beneficial technical effects brought about by the present invention are:

[0023] 1. The method of the present invention abandons the traditional secondary frequency conversion scheme and replaces the swept frequency local oscillator with several variable local oscillators, which greatly reduces the complexity and the spurious emission of the local oscillator, and speeds up the switching. The multi-clock switching method plans the acquisition frequency of the ADC and the output frequency of the DAC. Multiple clocks are switched using high-speed switches, and the speed can reach the nanosecond level.

[0024] 2. High-frequency reference signals can usually be obtained through crystal oscillator frequency multiplication or highly integrated frequency synthesizer chips. The amplitude and phase consistency are very good. The reference phase noise generated by direct crystal oscillator frequency multiplication is better than that of the swept local oscillator. If a highly integrated frequency synthesizer chip is used, the system integration will be higher and the solution will be simpler.

[0025] 3. The present invention utilizes the three Nyquist intervals of high-speed digital devices ADC and DAC to achieve seamless frequency band coverage, which greatly reduces the complexity of system hardware and is more conducive to large-scale multi-channel integration. At the same time, it improves the speed of signal acquisition and signal generation and reduces the path delay of the signal closed loop.

[0026] 4. Since the present invention abandons the complex secondary frequency conversion circuit, the integration is very high. In conjunction with the synchronous bus, it can flexibly expand multiple channels, and can achieve multiple receptions and multiple transmissions, one transmission and multiple receptions, or one reception and multiple transmissions. Flexible configuration. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of a traditional signal transceiver;

[0028] Figure 2 This is a schematic diagram of a low-latency, highly integrated transceiver device according to the present invention. DETAILED DESCRIPTION

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0030] The technical solution of the present invention is as follows Figure 2 shown.

[0031] The segmented filtering and signal conditioning unit of the present invention mainly consists of a filter, an equalizer, a low-noise amplifier, and a voltage-controlled attenuator. The segmented filtering and signal conditioning of the up-conversion is mainly responsible for filtering the DAC output signal and adjusting the amplitude and phase. The DAC uses a high sampling clock and the output channel frequency covers the second or third Nyquist zone. The segmented filter selects signals in different Nyquist zones. The DAC and the FPGA are interconnected by a high-speed interface and a synchronous bus. The synchronous bus has little effect when the system outputs in one direction, but it is indispensable when forming a transceiver. The synchronization signal is mainly used to ensure that the received signal and the transmitted signal remain synchronized, and that multiple receiving channels and multiple transmitting channels remain synchronized. It can also ensure that the signals between multiple receiving channels and multiple transmitting channels remain synchronized.

[0032] Figure 2 The high-frequency reference can be obtained by frequency doubling and filtering a crystal oscillator, or by using a commercial frequency synthesizer chip. In order to achieve lower phase noise characteristics, it is generally obtained by frequency doubling a crystal oscillator and then using an extremely narrow bandwidth surface acoustic wave filter to suppress broadband noise.

[0033] The clock distribution unit uses direct frequency synthesis to obtain 2-5 clocks of different frequencies from the high-frequency reference signal. If only one clock is used, when the output frequency is close to the Nyquist frequency, the frequency overlap and mirror frequency are too close to the main signal frequency to be filtered out with a filter. Using a high-speed switch to switch the frequencies of different clocks can change the size of the Nyquist frequency interval and solve the problem of seamless frequency band coverage through frequency planning. However, too many clocks will also increase the complexity of the solution and the hardware cost.

[0034] The same principle applies to the ADC signal receiving channel. The input signal is preselected through a segmented filter, and the appropriate ADC clock is selected for signals in different frequency bands. This allows input signals of different frequency bands to be converted into the ADC's first Nyquist zone for calculation. The signal receiving channel and the signal transmitting channel share a common clock, ensuring very high phase consistency of the signal while saving costs.

[0035] Therefore, the method of the present invention uses a 2-5 clock switching method to plan the ADC acquisition frequency and the DAC output frequency. Multiple clocks are switched using high-speed switches, with speeds reaching the nanosecond level. Multiple reference signals can usually be obtained through crystal oscillator frequency multiplication or a highly integrated frequency synthesizer chip, with excellent amplitude and phase consistency. The reference phase noise generated by direct crystal oscillator frequency multiplication is superior to that of a swept local oscillator. The three Nyquist intervals of high-speed digital devices are utilized for seamless frequency band coverage, greatly reducing system hardware complexity and facilitating large-scale multi-channel integration. It also improves the speed of signal acquisition and signal generation and reduces signal closed-loop path delay. Furthermore, because the present invention does not have a complex secondary frequency conversion circuit, it has a very high level of integration. In conjunction with a synchronous bus, it can flexibly expand multiple channels, enabling flexible configurations of multiple receivers and multiple transmitters, one transmitter and multiple receivers, or one receiver and multiple transmitters.

[0036] The key points and protection points of the present invention are:

[0037] 1. The integrated transceiver architecture of the present invention is relatively innovative. It abandons the frequency conversion architecture of traditional technology, performs frequency planning by switching clock frequency, and uses the three Nyquist zones of high-speed digital devices to achieve seamless frequency band coverage. It has fast switching speed and simple hardware design.

[0038] 2. The high-frequency reference signal of the present invention can be obtained in two ways. One is through crystal oscillator frequency doubling, and the amplitude and phase consistency are very good. In addition, the reference phase noise generated by direct crystal oscillator frequency doubling is better than that of the swept local oscillator. The second method uses a highly integrated frequency synthesizer chip, and the system integration will be higher.

[0039] 3. The present invention utilizes a high-speed switch to switch the clock, which greatly accelerates the signal reception and transmission speed compared to traditional technologies. Combined with the synchronous trigger function, the entire signal reception and transmission path has low latency and high-speed operation. The synchronization function is mainly used to ensure that the received signal and the transmitted signal remain synchronized, and multiple receiving channels and multiple transmitting channels remain synchronized. It can also ensure that the signals between multiple receiving channels and multiple transmitting channels remain synchronized.

[0040] 4. The present invention is not limited to symmetric sending and receiving numbers, but can achieve flexible configuration of multiple receiving and multiple sending, one sending and multiple receiving, or one receiving and multiple sending according to different application scenarios.

[0041] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the scope of protection of the present invention.

Claims

1. A broadband, low-latency, highly integrated transceiver device, characterized in that: It includes segmented filtering and signal conditioning unit, high-frequency reference signal generation module, multi-clock distribution unit, high-speed switch module, ADC, DAC, FPGA module and synchronous trigger unit; among them, The segmented filtering and signal conditioning unit is configured to filter and adjust the amplitude and phase of the DAC output signal and the ADC input signal; A high-frequency reference signal generating module is configured to generate a high-frequency reference signal; a multi-clock distribution unit configured to receive a high-frequency reference signal and generate clock signals of different frequencies; A high-speed switch module is configured to switch the sampling clock frequency of the ADC and the output clock frequency of the DAC to achieve frequency band coverage based on the Nyquist frequency interval; The ADC and the DAC are configured to perform frequency planning according to the switched clock signal respectively; The FPGA module is configured to perform data transmission, reception, and processing, and utilizes a synchronous bus to ensure signal synchronization; The synchronization trigger unit is configured to ensure that the received signal and the transmitted signal remain synchronized, multiple receiving channels and multiple transmitting channels remain synchronized, the signals between multiple receiving channels remain synchronized, and the signals between multiple transmitting channels remain synchronized.

2. The broadband, low-latency, highly integrated transceiver device according to claim 1, characterized in that: The high-frequency reference signal is obtained through crystal oscillator frequency multiplication or frequency synthesizer chip.

3. The broadband, low-latency, highly integrated transceiver device according to claim 1, characterized in that: The clock distribution unit generates 2-5 clock signals of different frequencies through direct frequency synthesis and provides a clock for each frequency.

4. The broadband, low-latency, highly integrated transceiver device according to claim 1, characterized in that: High-speed switch modules use switches with speeds reaching nanosecond levels.

5. The broadband, low-latency, highly integrated transceiver device according to claim 1, characterized in that: The switching action of the high-speed switch module is controlled by the FPGA module to achieve dynamic frequency planning and adaptive frequency band matching.

6. The broadband, low-latency, highly integrated transceiver device according to claim 1, characterized in that: The FPGA module is interconnected with the ADC and DAC through a high-speed interface, and synchronization between the received and transmitted signals and synchronous triggering between multiple channels are achieved through a synchronization bus.

7. The broadband, low-latency, highly integrated transceiver device according to claim 1, characterized in that: The device uses a synchronous bus for flexible expansion and supports asymmetric configurations of multiple receive and multiple transmit, one transmit and multiple receive, or one receive and multiple transmit.

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