Off-chip resistance-capacitance detection circuit

Abstract

The invention discloses an off-chip resistance-capacitance detection circuit, and relates to the technical field of resistance-capacitance detection, and the circuit comprises an oscillation circuit module, a resistance recognition module and a capacitance recognition module. The resistance identification module is connected with an external device to be tested, the capacitance identification module and the oscillating circuit module, and the capacitance identification module is connected with the oscillating circuit module; the resistance identification module is used for judging the detected to-be-detected node voltage of the external to-be-detected device and outputting a resistance indication signal; the oscillating circuit module is used for generating an oscillating signal and outputting the oscillating signal serving as a clock signal to the capacitance identification module; and the capacitance identification module is used for carrying out filtering and frequency selection on the oscillation frequency of the oscillation signal to obtain a frequency selection result, and determining a capacitance indication signal according to the frequency selection result so as to judge whether an external to-be-tested device has a resistor or a capacitor or not under the condition that an internal integrating capacitor is not needed.

Description

Technical Field

[0001] The present application relates to the technical field of resistance and capacitance detection, and in particular to an off-chip resistance and capacitance detection circuit. Background Art

[0002] With the prevalence of portable devices, the market is placing increasing demands on the integration and miniaturization of various electronic circuits. Many devices require detecting whether external components contain resistors or capacitors to determine the operating state of internal circuits. However, existing resistance and capacitance detection devices still suffer from large area, low integration, and high cost.

[0003] How to realize the detection of capacitance and resistance values ​​with high integration and low cost is a difficult problem that still needs to be solved urgently. Summary of the Invention

[0004] The main purpose of this application is to provide an off-chip resistance and capacitance detection circuit, aiming to solve the technical problems of existing resistance and capacitance detection devices such as large area, low integration and high cost.

[0005] To achieve the above-mentioned object, the present application proposes an off-chip resistance and capacitance detection circuit, which includes: an oscillation circuit module, a resistance identification module and a capacitance identification module;

[0006] The resistance identification module is connected to the external device under test, the capacitance identification module and the oscillation circuit module respectively, and the capacitance identification module is connected to the oscillation circuit module;

[0007] The resistance identification module is used to determine the voltage of the node to be detected of the external device to be tested and output a resistance indication signal;

[0008] The oscillation circuit module is used to generate an oscillation signal and output the oscillation signal as a clock signal to the capacitance identification module;

[0009] The capacitance identification module is used to filter and select the oscillation frequency of the oscillation signal to obtain a frequency selection result, and determine the capacitance indication signal according to the frequency selection result.

[0010] Optionally, the off-chip resistance-capacitance detection circuit further includes: a logic control module;

[0011] The logic control module is connected to the resistance identification module, the capacitance identification module and the oscillation circuit module respectively;

[0012] The logic control module is configured to send a first control signal to the resistance identification module upon receiving an operation instruction;

[0013] The resistance identification module is configured to perform voltage detection on the node to be detected of the external device to be tested and make a judgment when receiving the first control signal.

[0014] Optionally, the off-chip resistance-capacitance detection circuit further includes: a first current source module and a second current source module;

[0015] The first current source module is respectively connected to the second current source module, the resistance identification module and the capacitance identification module, and the second current source module is respectively connected to the resistance identification module and the capacitance identification module;

[0016] The logic control module is further configured to send a first control signal to the oscillation circuit module upon receiving an operation instruction;

[0017] The oscillation circuit module is further configured to send a third control signal and a second control signal to the first current source module and the second current source module respectively upon receiving the first control signal;

[0018] The first current source module is configured to charge the node to be detected and output a charging signal to the oscillation circuit module when receiving a third control signal;

[0019] The second current source module is configured to discharge the node to be detected and output a discharge signal to the oscillation circuit module when receiving a second control signal;

[0020] The oscillation circuit module is further configured to generate an oscillation signal when receiving a charging signal and a discharging signal.

[0021] Optionally, the resistance identification module includes: a resistance determination unit and a resistance identification unit;

[0022] The decision resistor unit is connected to the capacitance identification module, the oscillation circuit module, the resistance identification unit and the logic control module respectively, and the resistance identification unit is connected to the capacitance identification module, the oscillation circuit module and the logic control module respectively;

[0023] The decision resistor unit is configured to, upon receiving a first control signal, make a decision on the voltage of the detected node of the external device under test and output a decision signal to the resistance identification unit;

[0024] The resistance identification unit is used to output a resistance indication signal when receiving a judgment signal.

[0025] Optionally, the capacitance identification module includes: a filtering unit and a capacitance identification unit;

[0026] The filtering unit is connected to the oscillation circuit module, the resistance identification module and the capacitance identification unit;

[0027] The filtering unit is configured to filter the oscillation signal upon receiving the oscillation signal and send the filtered oscillation signal to the capacitance identification unit;

[0028] The capacitance identification unit is used to filter and select the oscillation frequency of the oscillation signal to obtain a frequency selection result, and determine the capacitance indication signal according to the frequency selection result.

[0029] Optionally, the decision resistor unit includes: a decision resistor and a first switch;

[0030] The first end of the decision resistor is connected to the first current source module, the second end of the decision resistor is connected to the first end of the first switch, the second end of the first switch is connected to the external device under test and the oscillation circuit module, and the control end of the first switch is connected to the resistance identification module, the capacitance identification module and the logic control module.

[0031] Optionally, the second current source module includes: a second current source and a second switch;

[0032] The positive electrode of the second current source is connected to the second end of the second switch, the negative electrode of the second current source is grounded, the first end of the second switch is connected to the first current source module, the external device under test, the resistance identification module and the oscillation circuit module, and the control end of the second switch is connected to the oscillation circuit module.

[0033] Optionally, the first current source module includes: a first current source and a third switch;

[0034] The positive electrode of the first current source is connected to the resistance identification module, the negative electrode of the first current source is connected to the first end of the third switch, the second end of the third switch is connected to the second current source module, the external device under test, the resistance identification module and the oscillation circuit module, and the control end of the third switch is connected to the oscillation circuit module.

[0035] Optionally, the input end of the inverter is connected to the decision resistor unit, the external device to be tested and the oscillation circuit module, the output end of the inverter is connected to the data input end of the trigger, and the clock input end of the trigger is connected to the logic control module, the oscillation circuit module, the capacitance identification module and the decision resistor unit.

[0036] Optionally, the non-inverting input terminal of the first comparator and the inverting input terminal of the second comparator are respectively connected to the resistance identification module and the external device under test, the inverting input terminal of the first comparator is connected to the first reference voltage source, the output terminal of the first comparator is connected to the reset terminal of the latch, the non-inverting input terminal of the second comparator is connected to the second reference voltage source, the output terminal of the second comparator is connected to the set terminal of the latch, the non-inverting output terminal of the latch is connected to the capacitance identification module and the first current source module, and the inverting output terminal of the latch is connected to the second current source module.

[0037] One or more technical solutions proposed in this application have at least the following effects:

[0038] The present application discloses an off-chip resistance and capacitance detection circuit, which includes: an oscillation circuit module, a resistance identification module, and a capacitance identification module; the resistance identification module is respectively connected to an external device under test, a capacitance identification module, and an oscillation circuit module, and the capacitance identification module is connected to the external device under test and the oscillation circuit module; the resistance identification module is used to judge the voltage of the detected node of the external device under test and output a resistance indication signal; the oscillation circuit module is used to generate an oscillation signal and output the oscillation signal as a clock signal to the capacitance identification module; the capacitance identification module is used to filter and select the oscillation frequency of the oscillation signal to obtain a frequency selection result, and determine the capacitance indication signal based on the frequency selection result. In this way, it is possible to judge whether the external device under test has resistance or capacitance without the need for an internal integral capacitor, solving the technical problems of large area, low integration, and high cost of existing resistance and capacitance detection devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1 This is a schematic structural diagram of a first embodiment of an off-chip resistance-capacitance detection circuit proposed in an embodiment of the present application;

[0041] Figure 2 This is a flow chart of a second embodiment of the off-chip RC detection circuit proposed in the present application;

[0042] Figure 3 A circuit schematic diagram of a second embodiment of an off-chip RC detection circuit proposed in an embodiment of the present application;

[0043] Figure 4A circuit schematic diagram of the filter unit and capacitance identification unit of the second embodiment of the off-chip resistance-capacitance detection circuit proposed in an embodiment of the present application;

[0044] Figure 5 This is an internal voltage waveform diagram of the second embodiment of the off-chip RC detection circuit proposed in the embodiment of the present application;

[0045] Figure 6 A circuit schematic diagram of a third embodiment of an off-chip RC detection circuit proposed in an embodiment of the present application;

[0046] Figure 7 This is an internal voltage waveform diagram of the third embodiment of the off-chip RC detection circuit proposed in the embodiments of the present application.

[0047] Description of Figure Numbers:

[0048]

[0049]

[0050] The purpose, features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0051] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not intended to limit the present application.

[0052] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0053] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0054] In addition, the descriptions of "first", "second", etc. in this application are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0055] The main solution of the embodiment of the present application is: the chip (logic control module 4) introduces a weak internal pull-up at the node to be detected, and by detecting the voltage of the node to be detected, it is determined whether there is an external pull-down resistor. According to different external resistance / capacitance values, the internal oscillation circuit generates periodic oscillation signals of different frequencies. And by filtering this signal, the frequency screening effect is achieved, thereby determining whether a capacitor is connected outside the chip. Based on the results of the above detection, the chip is configured to operate in different modes.

[0056] The present application provides a solution, and discloses an off-chip resistance and capacitance detection circuit, which includes: an oscillation circuit module 1, a resistance identification module 2 and a capacitance identification module 3; the resistance identification module 2 is respectively connected to the external device to be tested, the capacitance identification module 3 and the oscillation circuit module 1, and the capacitance identification module 3 is connected to the external device to be tested and the oscillation circuit module 1; the resistance identification module 2 is used to judge the voltage of the detected node to be detected of the external device to be tested and output a resistance indication signal; the oscillation circuit module 1 is used to generate an oscillation signal and output the oscillation signal as a clock signal to the capacitance identification module 3; the capacitance identification module 3 is used to filter and select the vibration frequency of the oscillation signal to obtain a frequency selection result, and determine the capacitance indication signal according to the frequency selection result, thereby judging whether the external device to be tested has resistance or capacitance without the need for an internal integral capacitor, solving the technical problems of large area, low integration and high cost of existing resistance and capacitance detection devices.

[0057] Based on this, an embodiment of the present application provides an off-chip resistance-capacitance detection circuit.

[0058] refer to Figure 1 , Figure 1 This is a structural diagram of the first embodiment of the off-chip RC detection circuit proposed in the embodiments of the present application.

[0059] Considering the technical problems of large area, low integration and high cost of current resistance and capacitance detection devices, in order to judge whether the external device under test has resistance or capacitance without the need for internal integration capacitors, Figure 1As shown, the off-chip resistance and capacitance detection circuit of this embodiment includes: an oscillation circuit module 1, a resistance identification module 2 and a capacitance identification module 3;

[0060] The resistance identification module 2 is connected to the external device under test, the capacitance identification module 3 and the oscillation circuit module 1 respectively, and the capacitance identification module 3 is connected to the oscillation circuit module 1;

[0061] The resistance identification module 2 is used to determine the voltage of the node to be detected of the external device under test and output a resistance indication signal;

[0062] The oscillation circuit module 1 is used to generate an oscillation signal and output the oscillation signal as a clock signal to the capacitance recognition module 3;

[0063] The capacitance identification module 3 is configured to filter and select the oscillation frequency of the oscillation signal to obtain a frequency selection result, and determine a capacitance indication signal according to the frequency selection result.

[0064] It should be noted that the node to be detected between the external device under test and the oscillation circuit module 1 is Ncomp, and the first reference voltage can be set according to actual needs, which is not limited in this embodiment.

[0065] It can be understood that the voltage of the node to be detected is judged: if the voltage of the node to be detected is less than the logic flip voltage of the inverter, there is a pull-down resistor in the external device to be tested, and the resistance identification module 2 outputs a resistance indication signal of a logic high level; if the voltage of the node to be detected is greater than the logic flip voltage of the inverter, there is no pull-down resistor in the external device to be tested, and the resistance identification module 2 outputs a resistance indication signal of a logic low level. The oscillation circuit module 1 generates an oscillation signal (filtering out the third control signal of 2 oscillation cycles), and the oscillation signal after the third control signal is filtered by the filtering unit 31 (2 oscillation cycles need to be filtered out) is used as a clock signal. If the vibration period of the oscillation signal is greater than the preset delay time, there is a capacitor in the external device to be tested, and the capacitance identification module 3 outputs a capacitance indication signal; if the vibration period of the oscillation signal is less than the preset delay time, there is no capacitor in the external device to be tested. The preset delay time is set by the rising delay circuit.

[0066] In a specific implementation, the resistance identification module 2 is used to judge the detected voltage of the node to be detected of the external device under test and output a resistance indication signal; the oscillation circuit module 1 is used to generate an oscillation signal and output the oscillation signal as a clock signal to the capacitance identification module 3; the capacitance identification module 3 is used to filter and select the oscillation frequency of the oscillation signal to obtain a frequency selection result, and determine the capacitance indication signal based on the frequency selection result, which solves the technical problems of large area, low integration and high cost of the current resistance and capacitance detection devices, and judges whether the external device under test has resistance or capacitance without the need for an internal integral capacitor, and configures the chip to work in different modes based on the results of the above detection and judgment.

[0067] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the first embodiment can be referred to the above introduction and will not be described in detail later. Figure 2 , Figure 2 This is a structural diagram of the second embodiment of the off-chip RC detection circuit proposed in the embodiments of the present application.

[0068] Considering that the circuit enters the external resistance judgment stage when it starts working. Figure 2 As shown, the off-chip RC detection circuit of this embodiment further includes: a logic control module 4;

[0069] The logic control module 4 is connected to the resistance identification module 2, the capacitance identification module 3 and the oscillation circuit module 1 respectively;

[0070] The logic control module 4 is configured to send a first control signal to the resistance identification module 2 upon receiving an operation instruction;

[0071] The resistance identification module 2 is configured to perform voltage detection on the node to be detected of the external device under test and make a decision when receiving the first control signal.

[0072] It should be noted that if Figure 3 As shown, Figure 3 This is a circuit schematic diagram of the second embodiment of the off-chip resistance-capacitance detection circuit proposed in the embodiment of the present application. The oscillation circuit module 1 in this embodiment is composed of a first comparator, a second comparator and an RS latch. The logic control module 4 receives an operation instruction, which means that the circuit is in an operating state, and the EN or RSTB signal is low, so that the first control signal Ctrl1 becomes a logic high level, closes the first switch S1, and opens the remaining switches (S2 and S3), resets the filter unit 31, the capacitance identification unit 32 and the oscillation circuit module 1, and enters the external resistance judgment stage.

[0073] In a specific implementation, the logic control module 4 is used to send a first control signal to the resistance identification module 2 when receiving an operation instruction; the resistance identification module 2 is used to perform voltage detection and judgment on the node to be detected of the external device to be tested when receiving the first control signal, thereby entering the external resistance judgment stage.

[0074] Furthermore, the off-chip resistance-capacitance detection circuit further includes: a first current source module 5 and a second current source module 6;

[0075] The first current source module 5 is respectively connected to the second current source module 6, the resistance identification module 2 and the capacitance identification module 3, and the second current source module 6 is respectively connected to the resistance identification module 2 and the capacitance identification module 3;

[0076] The logic control module 4 is further configured to send a first control signal to the oscillation circuit module 1 upon receiving an operation instruction;

[0077] The oscillation circuit module 1 is further configured to send a third control signal and a second control signal to the first current source module 5 and the second current source module 6 respectively upon receiving the first control signal;

[0078] The first current source module 5 is configured to charge the node to be detected and output a charging signal to the oscillation circuit module 1 when receiving a third control signal;

[0079] The second current source module 6 is configured to discharge the node to be detected and output a discharge signal to the oscillation circuit module 1 when receiving a second control signal;

[0080] The oscillation circuit module 1 is further configured to generate an oscillation signal when receiving a charging signal and a discharging signal.

[0081] It should be noted that if Figure 3 As shown, if an external pull-down resistor is present, the detected node Ncomp will be pulled down to a lower voltage. The logic inverter in the resistance identification module 2 will identify this voltage as a logic low level, causing the inverter to output a logic high voltage. Subsequently, the logic control unit causes the first control signal Ctrl1 to become a logic low level. At the falling edge of the control signal Ctrl1, the D flip-flop in the resistance identification module 2 will output a logic high, that is, the resistance indication signal EXT_RES = 1, and will remain unchanged until the next falling edge of the control signal Ctrl1.

[0082] In another case, if there is no external pull-down resistor, the node Ncomp to be detected will be pulled up to the power supply voltage, and the logic inverter in the resistance identification module 2 will identify the voltage as a logic high level, so that the inverter outputs a logic low voltage. Subsequently, the logic control unit causes the first control signal Ctrl1 to become a logic low level. At the falling edge of the control signal Ctrl1, the D flip-flop in the resistance identification module 2 will output a logic low, that is, the resistance indication signal EXT_RES=0, and remains unchanged until the next falling edge of the control signal Ctrl1. Therefore, the EXT_RES signal can correctly indicate whether there is an external pull-down resistor, and the internal working mode can be configured differently according to the indication signal EXT_RES. After the first control signal Ctrl1 becomes low, the external resistance judgment stage ends. At the same time, the circuit enters the external capacitance judgment stage. Reference Figure 4 , Figure 4 This is a schematic diagram of the filter unit 31 and capacitance identification unit 32 of the second embodiment of the off-chip RC detection circuit proposed in this application. As the control signal Ctrl1 goes low, the RS latch in the oscillation circuit module 1 enters normal operation, and the oscillation circuit begins normal operation. At this point, the oscillation circuit has two different startup states, depending on whether an external pull-down resistor is present.

[0083] It is understandable that if Figure 3 As shown, if an external pull-down resistor is present, the voltage at the detection node Ncomp is lower than the second reference voltage VREFL during startup. Under this condition, the output of the first comparator in the oscillation circuit module 1 is 0, and the output of the second comparator is 1. At this time, the RS latch operates in the set state, i.e., the non-inverting output terminal Q is logic 1, and the inverting output terminal ~Q is logic 0. This means that the second control signal Ctrl2 is low and the third control signal Ctrl3 is high. At this time, the first current source is turned on to charge the detection node Ncomp (equivalent to sending a charging signal). The voltage at the detection node Ncomp gradually increases until it exceeds the first reference voltage VREFH. At this time, the output of the first comparator in the oscillation circuit module 1 is 1, and the output of the second comparator is 0. The RS latch operates in a reset state, with the non-inverting output terminal Q at a logic 0 and the inverting output terminal ~Q at a logic 1. This means the third control signal Ctrl3 is low and the second control signal Ctrl2 is high. At this point, the second current source is turned on to discharge the detection node Ncomp (equivalent to sending a discharge signal). The voltage at the detection node Ncomp gradually decreases until it falls below the second reference voltage VREFL, causing the RS latch to operate in a set state again. This cycle repeats, resulting in oscillation. Because the voltage at the detection node Ncomp may be very low at the start of oscillation, unlike subsequent oscillations, the first oscillation period may be longer. Therefore, the oscillation signal Ctrl3 is fed into the filter unit 31, which filters out the initial two periods before obtaining the true periodic oscillation signal CLK.

[0084] Alternatively, if there is no external pull-down resistor, the voltage at the detection node Ncomp reaches the power supply voltage during startup, exceeding the first reference voltage VREFH. Under this condition, the output of the first comparator in the oscillation circuit module 1 is 1, and the output of the second comparator is 0. At this point, the RS latch operates in a reset state, with the non-inverting output terminal Q at logic 0 and the inverting output terminals ~Q at logic 1. This also means that the third control signal Ctrl3 is low and the second control signal Ctrl2 is high. At this point, the second current source is turned on to discharge the detection node Ncomp. The voltage at the detection node Ncomp gradually decreases until it falls below the second reference voltage VREFL. At this point, the output of the first comparator in the oscillation circuit module 1 is 0, and the output of the second comparator is 1. This means that the non-inverting output terminal Q is logic 1 and the inverting output terminals ~Q are logic 0. The RS latch operates in a set state, with the third control signal Ctrl3 being high and the second control signal Ctrl2 being low. At this point, the second current source is turned on to charge the detection node Ncomp. The voltage at the detection node Ncomp gradually increases until it exceeds the first reference voltage VREFH, causing the RS latch to reset again. This cycle repeats, resulting in oscillation. Because the voltage at the detection node Ncomp is very high at the start of oscillation, unlike subsequent oscillations, the first oscillation cycle is longer. Therefore, the oscillation signal Ctrl3 is fed into the filter unit 31, which filters out the initial two cycles before obtaining the true periodic oscillation signal CLK.

[0085] In a specific implementation, the logic control module 4 is further used to send a first control signal to the oscillation circuit module 1 when receiving an operation instruction; the oscillation circuit module 1 is further used to send a third control signal and a second control signal to the first current source module 5 and the second current source module 6 respectively when receiving the first control signal; the first current source module 5 is used to charge the node to be detected when receiving the third control signal, and output a charging signal to the oscillation circuit module 1; the second current source module 6 is used to discharge the node to be detected when receiving the second control signal, and output a discharge signal to the oscillation circuit module 1; the oscillation circuit module 1 is also used to generate an oscillation signal when receiving a charging signal and a discharging signal, thereby using the filtered oscillation signal as an internal clock signal.

[0086] Furthermore, the resistance identification module 2 includes: a resistance determination unit and a resistance identification unit;

[0087] The decision resistor unit is respectively connected to the capacitance identification module 3, the oscillation circuit module 1, the resistance identification unit and the logic control module 4, and the resistance identification unit is respectively connected to the capacitance identification module 3, the oscillation circuit module 1 and the logic control module 4;

[0088] The decision resistor unit is configured to, upon receiving a first control signal, make a decision on the voltage of the detected node of the external device under test and output a decision signal to the resistance identification unit;

[0089] The resistance identification unit is used to output a resistance indication signal when receiving a judgment signal.

[0090] It should be noted that the decision signal may be a voltage signal or a current signal, which is not limited in this embodiment.

[0091] In a specific implementation, the judgment resistance unit is used to judge the detected voltage of the node to be detected of the external device under test and output a judgment signal to the resistance identification unit when receiving a first control signal; the resistance identification unit is used to output a resistance indication signal when receiving a judgment signal, thereby judging whether there is resistance in the external device under test.

[0092] Furthermore, the capacitance recognition module 3 includes: a filtering unit 31 and a capacitance recognition unit 32;

[0093] The filtering unit 31 is connected to the oscillation circuit module 1, the resistance identification module 2 and the capacitance identification unit 32;

[0094] The filtering unit 31 is configured to filter the oscillation signal upon receiving the oscillation signal and send the filtered oscillation signal to the capacitance identification unit 32;

[0095] The capacitance identification unit 32 is configured to filter and select the oscillation frequency of the oscillation signal to obtain a frequency selection result, and determine a capacitance indication signal according to the frequency selection result.

[0096] It should be noted that if Figure 4 and Figure 5 As shown, Figure 4 This is a circuit schematic diagram of the filtering unit 31 and the capacitance identification unit 32 of the second embodiment of the off-chip resistance-capacitance detection circuit proposed in an embodiment of the present application. Figure 5This is the internal voltage waveform diagram of the second embodiment of the off-chip resistance and capacitance detection circuit proposed in the embodiment of the present application. The filtering unit 31 is composed of three D flip-flops and an AND gate, and the capacitance identification unit 32 is composed of an OR gate, a rise delay circuit and two D flip-flops. The (periodic) oscillation signal CLK enters the capacitance identification module 3. At this time, if there is an external capacitor and the oscillation period of the oscillation signal is greater than the preset delay time of the rise delay circuit, the clock port of the capacitance identification module 3 can receive a periodic square wave signal, and thus the capacitance indication signal EXT_CAP will output a high level. At this time, the internal time configuration uses the periodic oscillation signal CLK as the clock. If there is no external capacitor and the oscillation period is less than the delay time of the first rise delay circuit, the clock port of the capacitance identification module 3 cannot receive the periodic square wave signal, and thus the indication signal EXT_CAP will output a low level. At this time, the internal time configuration does not use the periodic oscillation signal CLK as the clock. The capacitance identification module 3 also filters out one oscillation period. This is to prevent the rising edge that may be introduced when the reset state is released from causing misjudgment.

[0097] In a specific implementation, the filtering unit 31 is used to filter the oscillation signal when receiving the oscillation signal and send the filtered oscillation signal to the capacitance identification unit 32; the capacitance identification unit 32 is used to filter and select the oscillation frequency of the oscillation signal to obtain a frequency selection result, and determine the capacitance indication signal based on the frequency selection result, so as to judge whether there is capacitance in the external device under test.

[0098] It should be noted that the present invention can correctly provide an external resistance indication signal EXT_RES, whose high level indicates the presence of an external pull-down resistor. The present invention can also provide an external capacitance indication signal EXT_CAP, whose high level indicates the presence of an external off-chip capacitor. In addition, the present invention also provides a periodic square wave signal CLK whose oscillation period is determined by the external resistance and capacitance values, which can be used as an internal time reference. Its oscillation period when both off-chip resistance and off-chip capacitance exist is formula (1):

[0099]

[0100] Its oscillation period when only external capacitors are connected and no external resistors are connected is as follows:

[0101]

[0102] When no external capacitor is connected, the square wave signal CLK is not used as the internal time reference because the oscillation frequency is too fast.

[0103] Furthermore, considering the specific operation mode of the off-chip RC detection circuit, such as Figure 3 As shown, the decision resistor unit in this embodiment includes: a decision resistor and a first switch;

[0104] The first end of the decision resistor is connected to the first current source module 5, the second end of the decision resistor is connected to the first end of the first switch, the second end of the first switch is connected to the external device under test and the oscillation circuit module 1, and the control end of the first switch is connected to the resistance identification module 2, the capacitance identification module 3 and the logic control module 4.

[0105] In a specific implementation, the logic control module 4 receives an operation instruction, which means that the circuit is in a working state, and the EN or RSTB signal is low, so that the first control signal Ctrl1 becomes a logic high level, closes the first switch S1, and opens the remaining switches (S2 and S3), and enters the external resistance judgment stage.

[0106] Furthermore, the second current source module 6 includes: a second current source and a second switch;

[0107] The positive electrode of the second current source is connected to the second end of the second switch, the negative electrode of the second current source is grounded, the first end of the second switch is connected to the first current source module 5, the external device under test, the resistance identification module 2 and the oscillation circuit module 1, and the control end of the second switch is connected to the oscillation circuit module 1.

[0108] The first current source module 5 includes: a first current source and a third switch;

[0109] The positive electrode of the first current source is connected to the resistance identification module 2, the negative electrode of the first current source is connected to the first end of the third switch, the second end of the third switch is connected to the second current source module, the external device under test, the resistance identification module 2 and the oscillation circuit module 1, and the control end of the third switch is connected to the oscillation circuit module 1.

[0110] In the specific implementation, Figure 3As shown, if an external pull-down resistor is present, the voltage at the detection node Ncomp is lower than the second reference voltage VREFL during startup. Under this condition, the output of the first comparator in the oscillation circuit module 1 is 0, and the output of the second comparator is 1. At this time, the RS latch operates in the set state, with the non-inverting output terminal Q at logic 1 and the inverting output terminals ~Q at logic 0. This means that the second control signal Ctrl2 is low (the second switch S2 is open) and the third control signal Ctrl3 is high (the third switch S3 is closed). The first current source is turned on to charge the detection node Ncomp, gradually increasing the voltage at the detection node Ncomp until it exceeds the first reference voltage VREFH. At this point, the output of the first comparator in the oscillation circuit module 1 is 1, and the output of the second comparator is 0. The RS latch operates in the reset state, with the non-inverting output terminal Q at logic 0 and the inverting output terminals ~Q at logic 1. This means that the third control signal Ctrl3 is low (the third switch S3 is open) and the second control signal Ctrl2 is high (the second switch S2 is closed). The second current source is turned on to discharge the detection node Ncomp.

[0111] Furthermore, the resistance identification unit includes: an inverter and a trigger;

[0112] The input end of the inverter is connected to the decision resistor unit, the external device under test and the oscillation circuit module 1, the output end of the inverter is connected to the data input end of the trigger, and the clock input end of the trigger is connected to the logic control module 4, the oscillation circuit module 1, the capacitance identification module 3 and the decision resistor unit.

[0113] It should be noted that the trigger is a D trigger.

[0114] In a specific implementation, if an external pull-down resistor is present, the detected node Ncomp will be pulled down to a lower voltage. The logic inverter in the resistance identification unit will identify this voltage as a logic low, causing the inverter to output a logic high voltage. Subsequently, the logic control module 4 causes the first control signal Ctrl1 to become a logic low. At the falling edge of the control signal Ctrl1, the D flip-flop in the resistance identification unit will output a logic high, i.e., the resistance indication signal EXT_RES = 1, which remains unchanged until the next falling edge of the control signal Ctrl1.

[0115] Furthermore, the oscillation circuit module 1 includes: a first comparator, a second comparator and a latch;

[0116] The non-inverting input terminal of the first comparator and the inverting input terminal of the second comparator are respectively connected to the resistance identification module and the external device under test, the inverting input terminal of the first comparator is connected to the first reference voltage source, the output terminal of the first comparator is connected to the reset terminal of the latch, the non-inverting input terminal of the second comparator is connected to the second reference voltage source, the output terminal of the second comparator is connected to the set terminal of the latch, the non-inverting output terminal of the latch is connected to the capacitance identification module and the first current source module, and the inverting output terminal of the latch is connected to the second current source module.

[0117] It should be noted that the latch is an RS latch. The first reference voltage source and the second reference voltage source provide a first reference voltage and a second reference voltage respectively.

[0118] In the specific implementation, Figure 3 As shown, if an external pull-down resistor is present, the voltage at the detection node Ncomp is lower than the second reference voltage VREFL during startup. Under this condition, the output of the first comparator in the oscillation circuit module 1 is 0, and the output of the second comparator is 1. At this time, the RS latch operates in the set state, with the non-inverting output terminal Q at logic 1 and the inverting output terminals ~Q at logic 0. This means that the second control signal Ctrl2 is low and the third control signal Ctrl3 is high. At this time, the first current source is turned on to charge the detection node Ncomp, gradually increasing the voltage at the detection node Ncomp until it exceeds the first reference voltage VREFH. At this point, the output of the first comparator in the oscillation circuit module 1 is 1, and the output of the second comparator is 0. The RS latch operates in the reset state, with the non-inverting output terminal Q at logic 0 and the inverting output terminals ~Q at logic 1. This means that the third control signal Ctrl3 is low and the second control signal Ctrl2 is high. At this time, the second current source is turned on to discharge the detection node Ncomp.

[0119] Based on the third embodiment of the present application, in the fourth embodiment of the present application, the same or similar contents as those in the third embodiment can be referred to the above introduction and will not be described in detail later. Figure 6 , Figure 6 This is a circuit schematic diagram of the third embodiment of the off-chip RC detection circuit proposed in the embodiments of the present application.

[0120] Considering that the oscillation circuit module 1 is composed of two comparators, a NOR gate, an OR gate and an RS latch and has no decision resistor unit, as shown in FIG. Figure 6 and Figure 7 As shown, Figure 7This is the internal voltage waveform diagram of the third embodiment of the off-chip RC detection circuit proposed in this application. When the circuit of this embodiment begins operation, the EN or RSTB signal is first set low, causing the first control signal Ctrl1 to reach a logic high level. This resets the filter unit 31 and the capacitance identification unit 32, and sets the RS latch, causing the third control signal Ctrl3 to reach a logic high level and the second control signal Ctrl2 to reach a logic low level. This enters the external resistance determination phase.

[0121] It should be noted that if there is an external pull-down resistor, the node to be detected Ncomp will be pulled down to a lower voltage, and its value I P ·R ext , I p is the current value of the first current source, R ext is the resistance value, which can be set according to actual needs. The logic inverter in the resistance identification module 2 will identify this voltage as a logic low level, so that the inverter outputs a logic high voltage. Subsequently, the logic control unit causes Ctrl1 to become a logic low level. At the falling edge of the first control signal Ctrl1, the D flip-flop in the resistance identification module 2 will output a logic high, that is, the resistance indication signal EXT_RES = 1, and will remain unchanged until the next falling edge of the first control signal Ctrl1 arrives.

[0122] In another case, if there is no external pull-down resistor, the node to be detected Ncomp will be pulled up to the power supply voltage. The logic inverter in the resistance identification module 2 will recognize this voltage as a logic high level, so that the inverter outputs a logic low voltage. Subsequently, the logic control unit causes Ctrl1 to become a logic low level. At the falling edge of the first control signal Ctrl1, the D flip-flop in the resistance identification module 2 will output a logic low, that is, the resistance indication signal EXT_RES = 0, and it will remain unchanged until the next falling edge of the first control signal Ctrl1 arrives. Therefore, the EXT_RES signal can correctly indicate whether there is an external pull-down resistor. The internal operating mode can be configured differently according to the indication signal EXT_RES.

[0123] It is understandable that after the first control signal Ctrl1 becomes low, the external resistance determination phase ends. At the same time, the circuit enters the external capacitance determination phase. Figure 6 As the first control signal Ctrl1 becomes low, the RS latch in the oscillation circuit module 1 is released from the set state, and its state is determined by the output of the first comparator and the second comparator, and the oscillation circuit starts to work normally. P ·R AXT> VREFH to ensure the normal operation of the oscillator circuit. Therefore, in this embodiment, regardless of whether there is an external pull-down resistor, the startup state of the oscillator circuit is the same. It should be noted that the flip threshold of the inverter in the resistance identification module 2 must be greater than the first reference voltage VREFH.

[0124] When the oscillation circuit module 1 starts oscillating, the voltage at the detection node Ncomp is greater than the first reference voltage VREFH. Under this condition, the outputs of the first and second comparators in the oscillation circuit module 1 are both 0. At this point, the RS latch operates in a reset state, with the non-inverting output terminal Q at a logic 0 and the inverting output terminals ~Q at a logic 1. This also means that the third control signal Ctrl3 is low and the second control signal Ctrl2 is high. At this point, the second current source is turned on to discharge the detection node Ncomp. The voltage at the detection node Ncomp gradually decreases until it falls below the second reference voltage VREFL. At this point, the outputs of the first and second comparators in the oscillation circuit module 1 are both 1. The first RS latch operates in a set state, with the non-inverting output terminal Q at a logic 1 and the inverting output terminals ~Q at a logic 0. This also means that the third control signal Ctrl3 is high and the second control signal Ctrl2 is low. At this point, the first current source is turned on to charge the detection node Ncomp. The voltage at the detection node Ncomp gradually increases until it exceeds the first reference voltage VREFH again, causing the RS latch to operate in a reset state again. This cycle repeats, resulting in oscillation. Since the voltage of the node to be detected Ncomp is very high at the beginning of oscillation, which is different from the subsequent oscillation process, the first oscillation period will be longer. Therefore, the oscillation signal Ctrl3 is sent to the filtering unit 31, and the first two periods are filtered out before the real periodic oscillation signal CLK is obtained.

[0125] It should be noted that if Figure 4 As shown, the periodic oscillation signal CLK enters the capacitor identification unit 32. At this time, if there is an external capacitor, the oscillation period of the (periodic) oscillation signal is greater than the preset delay time of the bilateral delay circuit, then the clock port of the capacitor identification unit 32 can receive the periodic square wave signal, and thus the capacitor indication signal EXT_CAP will output a high level. At this time, the internal time configuration uses the (periodic) oscillation signal CLK as the clock. If there is no external capacitor, the oscillation period of the (periodic) oscillation signal is less than the preset delay time of the bilateral delay circuit, then the clock port of the capacitor identification unit 32 cannot receive the periodic square wave signal, and thus the capacitor indication signal EXT_CAP will output a low level. At this time, the internal time configuration does not use the periodic oscillation signal CLK as the clock. The capacitor identification unit 32 also filters out one oscillation period, which is to prevent the rising edge that may be introduced when the reset state is released from causing judgment errors.

[0126] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An off-chip resistance and capacitance detection circuit, characterized in that: The off-chip resistance and capacitance detection circuit includes: an oscillation circuit module, a resistance identification module and a capacitance identification module; The resistance identification module is connected to the external device under test, the capacitance identification module and the oscillation circuit module respectively, and the capacitance identification module is connected to the oscillation circuit module; The resistance identification module is used to determine the voltage of the node to be detected of the external device to be tested and output a resistance indication signal; The oscillation circuit module is used to generate an oscillation signal and output the oscillation signal as a clock signal to the capacitance identification module; The capacitance identification module is used to filter and select the oscillation frequency of the oscillation signal to obtain a frequency selection result, and determine the capacitance indication signal according to the frequency selection result.

2. The off-chip resistance-capacitance detection circuit according to claim 1, wherein: The off-chip resistance-capacitance detection circuit further includes: a logic control module; The logic control module is connected to the resistance identification module, the capacitance identification module and the oscillation circuit module respectively; The logic control module is configured to send a first control signal to the resistance identification module upon receiving an operation instruction; The resistance identification module is configured to perform voltage detection on the node to be detected of the external device to be tested and make a judgment when receiving the first control signal.

3. The off-chip resistance-capacitance detection circuit according to claim 2, wherein: The off-chip resistance-capacitance detection circuit further includes: a first current source module and a second current source module; The first current source module is respectively connected to the second current source module, the resistance identification module and the capacitance identification module, and the second current source module is respectively connected to the resistance identification module and the capacitance identification module; The logic control module is further configured to send a first control signal to the oscillation circuit module upon receiving an operation instruction; The oscillation circuit module is further configured to send a third control signal and a second control signal to the first current source module and the second current source module respectively upon receiving the first control signal; The first current source module is configured to charge the node to be detected and output a charging signal to the oscillation circuit module when receiving a third control signal; The second current source module is configured to discharge the node to be detected and output a discharge signal to the oscillation circuit module when receiving a second control signal; The oscillation circuit module is further configured to generate an oscillation signal when receiving a charging signal and a discharging signal.

4. The off-chip resistance-capacitance detection circuit according to claim 3, wherein: The resistance identification module includes: a resistance determination unit and a resistance identification unit; The decision resistor unit is connected to the capacitance identification module, the oscillation circuit module, the resistance identification unit and the logic control module respectively, and the resistance identification unit is connected to the capacitance identification module, the oscillation circuit module and the logic control module respectively; The decision resistor unit is configured to, upon receiving a first control signal, make a decision on the voltage of the detected node of the external device under test and output a decision signal to the resistance identification unit; The resistance identification unit is used to output a resistance indication signal when receiving a judgment signal.

5. The off-chip resistance-capacitance detection circuit according to claim 1, wherein: The capacitance recognition module includes: a filtering unit and a capacitance recognition unit; The filtering unit is connected to the oscillation circuit module, the resistance identification module and the capacitance identification unit; The filtering unit is configured to filter the oscillation signal upon receiving the oscillation signal and send the filtered oscillation signal to the capacitance identification unit; The capacitance identification unit is used to filter and select the oscillation frequency of the oscillation signal to obtain a frequency selection result, and determine the capacitance indication signal according to the frequency selection result.

6. The off-chip resistance-capacitance detection circuit according to claim 4, wherein: The decision resistor unit includes: a decision resistor and a first switch; The first end of the decision resistor is connected to the first current source module, the second end of the decision resistor is connected to the first end of the first switch, the second end of the first switch is connected to the external device under test and the oscillation circuit module, and the control end of the first switch is connected to the resistance identification module, the capacitance identification module and the logic control module.

7. The off-chip resistance-capacitance detection circuit according to claim 3, wherein: The second current source module includes: a second current source and a second switch; The positive electrode of the second current source is connected to the second end of the second switch, the negative electrode of the second current source is grounded, the first end of the second switch is connected to the first current source module, the external device under test, the resistance identification module and the oscillation circuit module, and the control end of the second switch is connected to the oscillation circuit module.

8. The off-chip resistance-capacitance detection circuit according to claim 3, wherein: The first current source module includes: a first current source and a third switch; The positive electrode of the first current source is connected to the resistance identification module, the negative electrode of the first current source is connected to the first end of the third switch, the second end of the third switch is connected to the second current source module, the external device under test, the resistance identification module and the oscillation circuit module, and the control end of the third switch is connected to the oscillation circuit module.

9. The off-chip resistance-capacitance detection circuit according to claim 4, wherein: The resistance identification unit includes: an inverter and a trigger; The input end of the inverter is connected to the decision resistor unit, the external device under test and the oscillation circuit module, the output end of the inverter is connected to the data input end of the trigger, and the clock input end of the trigger is connected to the logic control module, the oscillation circuit module, the capacitance identification module and the decision resistor unit.

10. The off-chip resistance-capacitance detection circuit according to claim 3, wherein: The oscillation circuit module includes: a first comparator, a second comparator and a latch; The non-inverting input terminal of the first comparator and the inverting input terminal of the second comparator are respectively connected to the resistance identification module and the external device under test, the inverting input terminal of the first comparator is connected to the first reference voltage source, the output terminal of the first comparator is connected to the reset terminal of the latch, the non-inverting input terminal of the second comparator is connected to the second reference voltage source, the output terminal of the second comparator is connected to the set terminal of the latch, the non-inverting output terminal of the latch is connected to the capacitance identification module and the first current source module, and the inverting output terminal of the latch is connected to the second current source module.

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