Post-simulation method of integrated circuit, electronic equipment and storage medium

Abstract

The invention provides a post-simulation method of an integrated circuit, electronic equipment and a storage medium, and relates to the technical field of chip design. The method comprises the following steps: based on a static time sequence analysis STA environment, obtaining a static time sequence analysis result of a physical implementation PR netlist corresponding to a register transfer level RTL module in a target integrated circuit; according to a static time sequence analysis result, obtaining an average clock network delay corresponding to an interface register in the PR netlist, a target establishment time and a target retention time of each input interface signal and a target output delay of each output interface signal, and constructing an interface signal delay model corresponding to the RTL module according to the average clock network delay, the target establishment time and the target retention time of each input interface signal and the target output delay of each output interface signal; according to the interface signal delay model and the RTL module, post-simulation processing is carried out, the interface signal delay model matched with the RTL module in time sequence can be constructed, in addition, the interface signal delay model can be combined with the RTL module to reduce the verification scale of a whole chip, the verification efficiency is improved, and the verification process is simplified.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a post-simulation method for integrated circuits, an electronic device, and a storage medium. Background Art

[0002] In digital integrated circuit design, compared to static timing analysis of digital integrated circuits, which focuses on path timing checking, post-simulation of digital integrated circuits focuses on verifying the timing functional characteristics of the chip after considering the delays of logic gate units and interconnect lines. Therefore, many designers regard it as a necessary sign-off step before chip tape-out.

[0003] Related technologies primarily employ full-chip post-emulation. Due to the large scale of the design, each round of verification and regression takes a very long time, making it virtually impossible to complete verification of relevant functional points within the limited chip design signoff window. To accelerate function point verification and regression, existing techniques often replace certain frequently instantiated modules within the full chip with RTL.

[0004] However, due to the mismatch in data and clock phase between the RTL and the gate-level netlist with delay, setup timing or hold timing violations are likely to occur between paths. In order to resolve these timing violations, other complex processing procedures are often required. Therefore, existing post-simulation methods have the problems of long verification time and complex verification process. Summary of the Invention

[0005] The purpose of this application is to address the deficiencies in the above-mentioned prior art and provide a post-simulation method, electronic device and storage medium for integrated circuits, which can solve the problem of timing mismatch between gate-level netlists with delays and RTL in the prior art, reduce the verification scale of the entire chip, improve verification efficiency and simplify the verification process.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0007] In a first aspect, the present invention provides a post-simulation method for an integrated circuit, the method comprising:

[0008] Based on the static timing analysis STA environment, obtain the static timing analysis results of the physical implementation PR netlist corresponding to the register transfer level RTL module in the target integrated circuit;

[0009] According to the static timing analysis results, obtain the average clock network delay corresponding to the interface register in the PR netlist, the target setup time and target hold time of each input interface signal, and the target output delay of each output interface signal;

[0010] Constructing an interface signal delay model corresponding to the RTL module according to the average clock network delay, the target setup time and target hold time of each input interface signal, and the target output delay of each output interface signal;

[0011] Post-simulation processing is performed according to the interface signal delay model and the RTL module.

[0012] In an optional embodiment, obtaining the target setup time and target hold time of each input interface signal in the PR netlist according to the static timing analysis result includes:

[0013] For each input interface signal, obtaining, based on the static timing analysis result, a first timing parameter set under the timing path where the input interface signal is located, the first timing parameter set including: a maximum setup timing margin, a minimum setup timing margin, a maximum hold timing margin, and a minimum hold timing margin;

[0014] According to the first timing parameter set and the clock cycle corresponding to the input interface signal, the setup time and hold time of the nearest level fan-out register corresponding to the input interface signal are calculated, and the target setup time and the target hold time are used as the target setup time and the target hold time respectively.

[0015] In an optional embodiment, constructing an interface signal delay model corresponding to the RTL module based on the average clock network delay, the target setup time and the target hold time of each input interface signal, and the target output delay of each output interface signal includes:

[0016] According to the average clock network delay, setting the clock source delay of the virtual clock in the external delay of the interface signal delay model;

[0017] Setting each input interface of the interface signal delay model according to the target setup time and the target hold time of each input interface;

[0018] Each output interface of the interface signal delay model is set according to the target output delay of each output interface signal.

[0019] In an optional embodiment, the target setup time includes: a maximum target setup time and a minimum target setup time; the maximum target setup time is calculated based on the clock cycle and the minimum setup timing margin corresponding to the input interface signal; the minimum target setup time is calculated based on the clock cycle and the maximum setup timing margin corresponding to the input interface signal;

[0020] The target hold time includes: a maximum target hold time and a minimum target hold time; the maximum target hold time is determined according to a maximum hold timing margin corresponding to the input interface signal, and the minimum target hold time is determined according to a minimum hold timing margin corresponding to the input interface signal.

[0021] In an optional implementation manner, setting the virtual clock source delay in the interface signal delay model according to the average clock network delay includes:

[0022] The clock source delay of the virtual clock in the interface signal delay model is set to a positive number of the average clock network delay.

[0023] In an optional implementation manner, obtaining, based on the static timing analysis result, an average clock network delay corresponding to an interface register in the PR netlist includes:

[0024] Obtaining the clock network delay of each interface register in the PR netlist;

[0025] According to the clock network delay of each interface register, an average clock network delay corresponding to the interface register is calculated.

[0026] In an optional embodiment, obtaining a target output delay of an output interface in the PR netlist according to the static timing analysis result includes:

[0027] According to the static timing analysis result, obtaining a second timing parameter set under the timing path where the output interface signal is located, the second timing parameter set including: a minimum setup timing margin and a minimum hold timing margin;

[0028] According to the second timing parameter set and the clock cycle corresponding to the output interface signal, the output delay of the nearest level fan-in register corresponding to the output interface signal is calculated and used as the target output delay.

[0029] In an optional embodiment, the target output delay includes: a maximum target output delay and a minimum target output delay, the maximum target output delay being a maximum signal delay corresponding to the output interface signal, the maximum signal delay being calculated based on the clock period and a minimum setup timing margin corresponding to the output interface signal;

[0030] The minimum target output delay is a minimum signal delay corresponding to the output interface signal, and the minimum signal delay is calculated based on a minimum hold timing margin corresponding to the output interface signal.

[0031] In an optional embodiment, the step of obtaining a static timing analysis result of a physical implementation PR netlist corresponding to a register transfer level (RTL) module in a target integrated circuit based on a static timing analysis (STA) environment includes:

[0032] Based on the static timing analysis STA environment, according to the standard parasitic parameter exchange format file and standard timing constraint file of the PR netlist corresponding to the RTL module, static timing analysis is performed on the PR netlist to obtain static timing analysis results.

[0033] In a second aspect, the present invention provides an electronic device comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of the post-simulation method of the integrated circuit as described in any of the aforementioned embodiments.

[0034] In a third aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, executes the steps of the post-simulation method of an integrated circuit as described in any of the aforementioned embodiments.

[0035] The beneficial effects of this application are:

[0036] In the post-simulation method, electronic device, and storage medium of an integrated circuit provided in an embodiment of the present application, the method includes: obtaining, based on a static timing analysis (STA) environment, a static timing analysis result of a physical implementation (PR) netlist corresponding to a register transfer level (RTL) module in a target integrated circuit; obtaining, based on the static timing analysis result, an average clock network delay, a target setup time and a target hold time of each input interface signal, and a target output delay of each output interface signal corresponding to the interface register in the PR netlist; constructing an interface signal delay model corresponding to the RTL module based on the average clock network delay, the target setup time and target hold time of each input interface signal, and the target output delay of each output interface signal; performing post-simulation processing based on the interface signal delay model and the RTL module to construct an interface signal delay model that matches the timing of the RTL module, and subsequently, when performing post-simulation processing based on this, the problem of timing mismatch between the gate-level netlist with delay and the RTL in the prior art can be solved; in addition, the constructed interface signal delay model can be reused as a whole in the post-simulation process, which can reduce the verification scale of the entire chip, improve verification efficiency, and simplify the verification process. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 A schematic flow chart of a post-simulation method for an integrated circuit provided in an embodiment of the present application;

[0039] Figure 2 A schematic flow chart of another integrated circuit post-simulation method provided in an embodiment of the present application;

[0040] Figure 3 A schematic flow chart of another integrated circuit post-simulation method provided in an embodiment of the present application;

[0041] Figure 4 A schematic flow chart of another integrated circuit post-simulation method provided in an embodiment of the present application;

[0042] Figure 5 A schematic flow chart of another integrated circuit post-simulation method provided in an embodiment of the present application;

[0043] Figure 6 A schematic diagram of the functional modules of a post-simulation device for an integrated circuit provided in an embodiment of the present application;

[0044] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0047] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0048] In existing technologies, full-chip post-simulation requires extremely long regression times for each round of verification due to the massive design scale, making it virtually impossible to complete verification of relevant functional points within the limited chip design signoff window. A common approach is to replace certain multi-instantiated modules in the full chip with RTL to accelerate regression time for functional point verification. However, due to data and clock phase mismatches between the RTL and the gate-level netlist with delays, setup and hold timing violations are common between paths.

[0049] The following methods are often used to solve the above-mentioned timing violations: First, chip logic verification personnel usually use multiple rounds of verification iterations to adjust the input and output signals and clock phases of the gate-level netlist boundary to solve the problem. Since multiple rounds of iterations are required, the time overhead is very long; second, the back-end sees the timing violations of the boundary signal-related paths through the STA environment of the netlist module, and then repairs them through virtual timing ECO, by changing the unit or line delay of the corresponding interface logic in the SDF to meet the interface timing requirements. Although this method saves multiple rounds of verification iteration time, it is relatively complicated due to the additional virtual timing ECO process.

[0050] In view of this, the present application provides a post-simulation method for integrated circuits, which can solve the problem of timing mismatch between gate-level netlists with delays and RTL, and at the same time can be combined with RTL to reduce the verification scale of the entire chip, improve verification efficiency, and simplify the verification process.

[0051] Figure 1 This is a flow chart of a post-simulation method for an integrated circuit provided in an embodiment of the present application. The execution subject of the method can be a computer, server, processor and other electronic devices. The method can be applied to the post-simulation process of a chip. Figure 1 As shown, the method includes:

[0052] Step 101: Based on a static timing analysis (STA) environment, obtain a static timing analysis result of a physical implementation (PR) netlist corresponding to a register transfer level (RTL) module in a target integrated circuit.

[0053] Among them, for the register transfer level (RTL) module in the target integrated circuit, a static timing analysis (STA) environment can be built for the RTL module corresponding to the PR (Place and Route) netlist, the interface clock signal and interface data signal of the PR netlist can be distinguished, and the delay constraints of the interface data signals of the PR netlist can be defined (for example, the set_input_delay and set_output_delay commands can be used to set zero delay), and the static timing analysis of the PR netlist can be completed in combination with the relevant timing constraint files.

[0054] Step 102: According to the static timing analysis results, obtain the average clock network delay corresponding to the interface register in the PR netlist, the target setup time and target hold time of each input interface signal, and the target output delay of each output interface signal.

[0055] Optionally, after obtaining the static timing analysis results of the PR netlist corresponding to the RTL module, the clock network delays of all interface registers corresponding to the PR netlist can be calculated based on the list of all interface registers in the PR netlist. According to the clock network delays of all interface registers, the average clock network delay corresponding to the interface registers in the PR netlist can be calculated. Subsequently, the clock source delay of the virtual clock in the external delay of the interface signal delay model can be set accordingly, so that the interface signal delay model and the RTL module achieve timing matching.

[0056] In addition, based on the static timing analysis results of the PR netlist, the target setup time and target hold time of each input interface signal and the target output delay of each output interface signal in the PR netlist can be obtained, so that the input interfaces of the interface signal delay model can be set according to the target setup time and target hold time of each input interface signal; and the output interfaces of the interface signal delay model can be set according to the target output delay of each output interface signal.

[0057] The target setup time may include: a maximum target setup time and a minimum target setup time; the target hold time may include: a maximum target hold time and a minimum target hold time; and the target output delay may include a maximum target output delay and a minimum target output delay.

[0058] The maximum target output delay or minimum target output delay of each output interface signal is the maximum time or minimum time required for the data signal to be transmitted from the input end of the fan-in register corresponding to the output interface to the output interface; the fan-in register corresponding to the output interface signal is the nearest register found by tracing the output interface signal forward through the logical connection.

[0059] Step 103: Construct an interface signal delay model corresponding to the RTL module according to the average clock network delay, the target setup time and target hold time of each input interface signal, and the target output delay of each output interface signal.

[0060] The interface signal delay model corresponding to the RTL module may include: an input interface, an output interface, and an external delay interface. Of course, it should be noted that this application does not limit the number of input interfaces and output interfaces in the interface signal delay module, and the number may vary depending on the actual RTL module.

[0061] Optionally, when constructing the interface signal delay model corresponding to the RTL module, the clock source delay of the virtual clock in the external delay of the interface signal delay model can be set based on the SDF file format according to the average clock network delay calculated above, so that timing matching can be achieved with the RTL module, that is, solving the problem of timing mismatch between the existing gate-level netlist with delay and RTL; according to the target setup time and target hold time of each input interface signal, the input interface description in the interface signal delay model is set; according to the target output delay of each output interface signal, the output interface description in the interface signal delay model is set, and finally these parameters are output to the specified file, and the specified file can be called the description file of the interface signal delay model.

[0062] Step 104: Perform post-simulation processing based on the interface signal delay model and the RTL module.

[0063] Based on the above description, after obtaining the description file of the interface signal delay model, the description file and RTL module of the interface signal delay model can be delivered to the front end for post-simulation. Through post-simulation, it can be verified whether the circuit timing and function after physical implementation PR meet the design requirements.

[0064] By applying the embodiments of the present application, it is possible to construct an interface signal delay model that matches the RTL module timing based on the average clock network delay, the target setup time and target hold time of each input interface signal, and the target output delay of each output interface signal. Subsequently, when post-simulation processing is performed based on this, the timing mismatch problem between the gate-level netlist with delay and the RTL that exists in the prior art can be solved; in addition, the constructed interface signal delay model can be reused as a whole in the post-simulation process, which can reduce the verification scale of the entire chip, improve verification efficiency, and simplify the verification process.

[0065] In summary, an embodiment of the present application provides a post-simulation method for an integrated circuit, the method comprising: obtaining a static timing analysis result of a physical implementation PR netlist corresponding to a register transfer level RTL module in a target integrated circuit based on a static timing analysis STA environment; obtaining, based on the static timing analysis result, an average clock network delay, a target setup time and a target hold time of each input interface signal, and a target output delay of each output interface signal corresponding to the interface register in the PR netlist; constructing an interface signal delay model corresponding to the RTL module based on the average clock network delay, the target setup time and the target hold time of each input interface signal, and the target output delay of each output interface signal; performing post-simulation processing based on the interface signal delay model and the RTL module to construct an interface signal delay model that matches the timing of the RTL module, and then, when post-simulation processing is subsequently performed based on this, the problem of timing mismatch between the gate-level netlist with delay and the RTL in the prior art can be solved; in addition, the constructed interface signal delay model can be reused as a whole in the post-simulation process, which can reduce the verification scale of the entire chip, improve verification efficiency, and simplify the verification process.

[0066] Figure 2 A flow chart of another integrated circuit post-simulation method provided in an embodiment of the present application. In an optional embodiment, as Figure 2 As shown above, based on the static timing analysis results, the target setup time and target hold time of each input interface signal in the PR netlist are obtained, including:

[0067] Step 201: For each input interface signal, obtain a first timing parameter set under the timing path where the input interface signal is located according to a static timing analysis result.

[0068] The first timing parameter set includes: a maximum setup timing margin, a minimum setup timing margin, a maximum hold timing margin, and a minimum hold timing margin.

[0069] Among them, based on the static timing analysis results, the interface data signals of the PR netlist can be timing analyzed. Optionally, for the input interface signals, the maximum setup timing margin MAX_slack_in under the timing path of all input interface signals can be printed based on the static timing analysis results. setup , minimum setup timing margin MIN_slack_in setup , Maximum hold timing margin MAX_slack_in hold , minimum hold timing margin MIN_slack_in hold .

[0070] Step 202: Calculate the setup time and hold time of the nearest fan-out register corresponding to the input interface signal based on the first timing parameter set and the clock cycle corresponding to the input interface signal, and use them as the target setup time and target hold time respectively.

[0071] Optionally, the target setup time of each input interface signal can be calculated based on the maximum setup timing margin MAX_slack_in under the timing path where it is located. setup , minimum setup timing margin MIN_slack_in setup And the clock cycle corresponding to the input interface signal, calculate the maximum target setup time MAX_delta-Din of the nearest level fan-out register corresponding to the input interface signal. setup and the minimum target settling time MIN_delta-Din setup , thereby obtaining the target establishment time corresponding to the input interface signal.

[0072] Optionally, the target hold time of each input interface signal can be calculated based on the maximum hold timing margin MAX_slack_in under the timing path where it is located. hold , minimum hold timing margin MIN_slack_in hold And the clock cycle corresponding to the input interface signal, respectively calculate the maximum target hold time MAX_delta-Din of the nearest level fan-out register corresponding to the input interface signal hold and minimum target hold time MIN_delta-Din hold , thereby obtaining the target holding time corresponding to the input interface signal.

[0073] The fan-out register at the nearest level corresponding to the input interface signal is the register at the nearest level found by tracing back the logical connection based on the input interface signal.

[0074] Figure 3 A flow chart of another integrated circuit post-simulation method provided in an embodiment of the present application. In an optional embodiment, as Figure 3 As shown above, the interface signal delay model corresponding to the RTL module is constructed based on the average clock network delay, the target setup time and target hold time of each input interface signal, and the target output delay of each output interface signal, including:

[0075] Step 301: According to the average clock network delay, the clock source delay of the virtual clock in the external delay of the interface signal delay model is set.

[0076] Step 302: Set each input interface of the interface signal delay model according to the target setup time and target hold time of each input interface.

[0077] Step 303: Set each output interface of the interface signal delay model according to the target output delay of each output interface signal.

[0078] Optionally, the interface signal delay model may include an input interface module, an output interface module, and an external delay module. The input interface module may include a description of each input interface signal, and the description of each input interface signal may be determined based on the target setup time and target hold time of each input interface calculated above; the output interface module may include a description of each output interface signal, and the description of each output interface signal may be determined based on the target output delay of each output interface signal calculated above; and the external delay module may include a description of the clock source delay of the virtual clock in the external delay, and the description of the clock source delay of the virtual clock in the external delay may be determined based on the average clock network delay calculated above.

[0079] In some embodiments, during specific construction, a TIMINGCHECK constraint value can be defined for each input interface based on the target setup time and target hold time of each input interface, based on the SDF syntax format. An IOPATH delay can be defined for each output interface based on the target output delay of each output interface signal. The clock source delay of the virtual clock in the external delay can be set based on the average clock network delay. Of course, it should be noted that the specific implementation is not limited to this and can vary depending on the actual application scenario.

[0080] It should be noted that, in some embodiments, for the interface signal delay model, the delay constraints of its interface data signal can also be set. For example, the set_input_delay command can be used to set the input delay of the interface data signal to zero delay, and the set_output_delay command can be used to set the output delay of the interface data signal to zero delay. This is not limited here.

[0081] By applying the embodiments of the present application, it is possible to construct an interface signal delay model that matches the RTL module timing, which not only solves the problem of timing mismatch between the gate-level netlist with delay and the RTL, but also can be combined with the RTL to reduce the verification scale of the entire chip, shorten the time for adjusting the internal delay data of the SDF and the verification iteration, improve the verification efficiency, and simplify the verification process.

[0082] Optionally, since for the input interface signal, the corresponding nearest level fan-out register needs to consider the phase relationship between the input data and the input clock jump edge, the target setup time of the input interface signal includes: the maximum target setup time and the minimum target setup time, and the target hold time of the input interface signal includes: the maximum target hold time and the minimum target hold time.

[0083] In an optional embodiment, the maximum target setup time is calculated based on the minimum setup timing margin corresponding to the clock period and the input interface signal, and the minimum target setup time is calculated based on the maximum setup timing margin corresponding to the clock period and the input interface signal.

[0084] Among them, the maximum setup timing margin corresponding to the input interface signal, that is, the maximum setup timing margin under the timing path where the input interface signal is located, can represent the time margin for the input interface signal to arrive at the register input end in advance under the best process conditions (minimum data path delay and maximum clock path delay).

[0085] The minimum setup timing margin corresponding to the input interface signal, that is, the minimum setup timing margin under the timing path where the input interface signal is located, can represent the time margin for the input interface signal to approach or fail to meet the setup time requirements under the worst process conditions (maximum data path delay and minimum clock path delay).

[0086] Optionally, the maximum target setup time corresponding to each input interface signal can be calculated by referring to the following formula:

[0087] MAX_delta-Din setup =cycle_in-MIN_slack_in setup , where MAX_delta-Din setup

[0088] Indicates the maximum target setup time corresponding to the input interface signal, cycle_in indicates the clock cycle corresponding to the input interface signal, MAX_slack_in setup Indicates the minimum setup timing margin corresponding to the input interface signal.

[0089] Optionally, the minimum target setup time corresponding to each input interface signal can be calculated by referring to the following formula:

[0090] MIN_delta-Din setup =cycle_in-MAX_slack_in setup , where MIN_delta-Din setup

[0091] Indicates the minimum target setup time corresponding to the input interface signal, cycle_in indicates the clock cycle corresponding to the input interface signal, MAX_slack_in setup Indicates the maximum target setup timing margin corresponding to the input interface signal.

[0092] The maximum target hold time is determined according to the maximum hold timing margin corresponding to the input interface signal, and the minimum target hold time is determined according to the minimum hold timing margin corresponding to the input interface signal.

[0093] Among them, the maximum hold timing margin corresponding to the input interface signal, that is, the maximum hold timing margin under the timing path where the input interface signal is located, can represent the time margin for the input interface signal to remain stable after the clock edge under the worst process conditions (maximum data path delay and minimum clock path delay).

[0094] The minimum hold timing margin corresponding to the input interface signal, that is, the minimum hold timing margin under the timing path where the input interface signal is located, can represent the time margin for the input interface signal to remain stable after the clock edge under the best process conditions (minimum data path delay and maximum clock path delay).

[0095] Optionally, the maximum target hold time corresponding to each input interface signal can be calculated by referring to the following formula:

[0096] MAX_delta-Din hold =MAX_slack_in hold , where MAX_delta-Din hold Indicates the maximum target hold time corresponding to the input interface signal, MAX_slack_in hold Indicates the maximum hold timing margin corresponding to the input interface signal.

[0097] Optionally, the minimum target hold time corresponding to each input interface signal can be calculated by referring to the following formula:

[0098] MIN_delta-Din hold =MIN_slack_in hold , where MIN_delta-Din hold Indicates the minimum target hold time corresponding to the input interface signal, MIN_slack_in hold Indicates the minimum hold timing margin corresponding to the input interface signal.

[0099] In an optional embodiment, setting the virtual clock source delay in the interface signal delay model based on the average clock network delay includes:

[0100] Set the clock source delay of the virtual clock in the interface signal delay model to a positive value equal to the average clock network delay.

[0101] It is understandable that since there is no clock network delay in the RTL module in the post-simulation, when building the interface signal delay model, the clock source delay of the virtual clock can be set for it, and the clock source delay of the virtual clock can be used to equalize the impact of the no-clock delay in the RTL module on timing analysis.

[0102] Specifically, the clock source delay of the virtual clock in the interface signal delay model can be set to a positive number of the average clock network delay. For example, if the average clock network delay is X, the clock source delay of the virtual clock in the interface signal delay model can be set to X. Subsequently, when the interface signal delay model is combined with the RTL module for post-simulation processing, the timing mismatch between the gate-level netlist with delay and the RTL in the prior art can be resolved.

[0103] Figure 4 A flow chart of another integrated circuit post-simulation method provided in an embodiment of the present application. In an optional embodiment, as Figure 4 As shown above, based on the static timing analysis results, the average clock network delay corresponding to the interface register in the PR netlist is obtained, including:

[0104] Step 401: Obtain the clock network delay of each interface register in the PR netlist.

[0105] Step 402: Calculate the average clock network delay corresponding to each interface register based on the clock network delay of each interface register.

[0106] Optionally, when obtaining the delay, the interface register list corresponding to the PR netlist can be extracted according to the static timing analysis results. Based on the interface register list, the clock network delay of each interface register can be traversed and obtained. According to the number of interface registers corresponding to the PR netlist, the clock network delay of each interface register is weighted and averaged to calculate the average clock network delay Latency corresponding to the interface register. avg .

[0107] It should be noted that the interface register mentioned here refers to the boundary register connected to the input interface and the output interface.

[0108] Figure 5 A flow chart of another integrated circuit post-simulation method provided in an embodiment of the present application. In an optional embodiment, as Figure 5 As shown above, based on the static timing analysis results, the target output delay of the output interface in the PR netlist is obtained, including:

[0109] Step 501: Obtain a second timing parameter set under a timing path where an output interface signal is located according to a static timing analysis result.

[0110] The second timing parameter set includes: a minimum setup timing margin and a minimum hold timing margin.

[0111] Optionally, for output interface signals, the delay data related to each output interface signal can be obtained based on the static timing analysis results. Optionally, the minimum setup timing margin slack_out under the timing path of all output interface signals can be printed out. setup and minimum hold timing margin slack_out hold .

[0112] Step 502: Calculate the output delay of the nearest fan-in register corresponding to the output interface signal according to the second timing parameter set and the clock cycle corresponding to the output interface signal, and use it as the target output delay.

[0113] Optionally, for the target output delay of each output interface signal, a timing margin slack_out can be established based on the minimum timing path in which it is located. setup , minimum hold timing margin slack_out hold And the clock cycle corresponding to the output interface signal, respectively calculate the maximum target output delay MAX_delta-Dout and the minimum target output delay MIN_delta-Dout of the nearest level fan-in register corresponding to the output interface signal, so as to obtain the target output delay corresponding to the output interface signal.

[0114] The fan-in register at the nearest level corresponding to the output interface signal is the register at the nearest level found by tracing back the logical connection based on the output interface signal.

[0115] In an optional embodiment, the target output delay includes: a maximum target output delay and a minimum target output delay, the maximum target output delay being a maximum signal delay corresponding to the output interface signal, the maximum signal delay being calculated based on a clock period and a minimum setup timing margin corresponding to the output interface signal;

[0116] The minimum target output delay is the minimum signal delay corresponding to the output interface signal. The minimum signal delay is calculated based on the minimum hold timing margin corresponding to the output interface signal.

[0117] Optionally, the maximum target output delay corresponding to each output interface signal can be calculated by referring to the following formula:

[0118] MAX_delta-Dout=cycle_out-slack_out setup , where MAX_delta-Dout represents

[0119] The maximum target output delay corresponding to the output interface signal, cycle_out represents the clock cycle corresponding to the output interface signal, slack_out setup Indicates the minimum setup timing margin corresponding to the output interface signal.

[0120] Optionally, the minimum target output delay corresponding to each output interface signal can be calculated by referring to the following formula:

[0121] MIN_delta - Dout = slack_out hold , where MIN_delta-Dout represents the minimum target output delay corresponding to the output interface signal, slack_out hold Indicates the minimum hold timing margin corresponding to the output interface signal.

[0122] In an optional embodiment, the above-mentioned static timing analysis STA environment is based on obtaining the static timing analysis result of the physical implementation PR netlist corresponding to the register transfer level RTL module in the target integrated circuit, including:

[0123] Based on the static timing analysis STA environment, static timing analysis is performed on the PR netlist according to the standard parasitic parameter exchange format file and standard timing constraint file of the RTL module corresponding to the PR netlist to obtain the static timing analysis results.

[0124] Among them, the standard parasitic parameter exchange format file can be used to describe parameters such as the resistance (Resistance) and capacitance (Capacitance) of the interconnect lines in the PR netlist; the standard timing constraint file can be used to define parameters such as clock, input / output delay, timing exceptions, etc., which are not limited here.

[0125] Optionally, when performing static timing analysis, the PR netlist, standard parasitic format (SPF) and standard timing constraint file (Synopsys Design Constraints, SDC) corresponding to the RTL module can be input into a static timing analysis (STA) tool for static timing analysis to obtain static timing analysis results. The obtained static timing analysis results may include: timing reports of various paths (for example, input to register path, register to register path, register to output path, clock gating path, cross-clock domain path, etc.).

[0126] Of course, it should be noted that when performing static timing analysis, the files input to the STA tool are not limited to this. Depending on the actual application scenario, other files such as the Standard Delay Format (SDF) file may also be included. The SDF file may include precise unit delay and interconnect delay parameters.

[0127] Figure 6 This is a functional module diagram of a post-simulation device for integrated circuits provided in an embodiment of the present application. The basic principle and technical effects of the device are the same as those of the corresponding method embodiment described above. For the sake of simplicity, the parts not mentioned in this embodiment can be referred to the corresponding contents in the method embodiment. Figure 6 As shown, the post-imitation device 100 includes:

[0128] The first acquisition module 110 is configured to acquire a static timing analysis result of a physical implementation PR netlist corresponding to a register transfer level (RTL) module in a target integrated circuit based on a static timing analysis (STA) environment.

[0129] The second acquisition module 120 is used to obtain the average clock network delay corresponding to the interface register in the PR netlist, the target setup time and target hold time of each input interface signal, and the target output delay of each output interface signal according to the static timing analysis result;

[0130] A construction module 130 is configured to construct an interface signal delay model corresponding to the RTL module based on the average clock network delay, the target setup time and target hold time of each input interface signal, and the target output delay of each output interface signal;

[0131] The post-simulation module 140 is used to perform post-simulation processing according to the interface signal delay model and the RTL module.

[0132] In an optional embodiment, the second acquisition module 120 is specifically configured to acquire, for each input interface signal, a first timing parameter set under a timing path where the input interface signal is located according to a static timing analysis result, where the first timing parameter set includes: a maximum setup timing margin, a minimum setup timing margin, a maximum hold timing margin, and a minimum hold timing margin;

[0133] According to the first timing parameter set and the clock cycle corresponding to the input interface signal, the setup time and hold time of the nearest level fan-out register corresponding to the input interface signal are calculated and used as the target setup time and the target hold time respectively.

[0134] In an optional embodiment, the construction module 130 is specifically configured to set the clock source delay of the virtual clock in the external delay of the interface signal delay model according to the average clock network delay;

[0135] Set each input interface of the interface signal delay model according to the target setup time and target hold time of each input interface;

[0136] According to the target output delay of each output interface signal, each output interface of the interface signal delay model is set.

[0137] In an optional embodiment, the target setup time includes: a maximum target setup time and a minimum target setup time; the maximum target setup time is calculated based on the clock cycle and the minimum setup timing margin corresponding to the input interface signal; the minimum target setup time is calculated based on the clock cycle and the maximum setup timing margin corresponding to the input interface signal;

[0138] The target hold time includes: a maximum target hold time and a minimum target hold time; the maximum target hold time is determined according to the maximum hold timing margin corresponding to the input interface signal, and the minimum target hold time is determined according to the minimum hold timing margin corresponding to the input interface signal.

[0139] In an optional implementation manner, the construction module 130 is specifically configured to set the clock source delay of the virtual clock in the interface signal delay model to a positive number of the average clock network delay.

[0140] In an optional embodiment, the second acquisition module 120 is specifically configured to acquire the clock network delay of each interface register in the PR netlist;

[0141] According to the clock network delay of each interface register, calculate the average clock network delay corresponding to the interface register.

[0142] In an optional embodiment, the second acquisition module 120 is specifically configured to acquire a second timing parameter set under the timing path where the output interface signal is located based on the static timing analysis result, where the second timing parameter set includes: a minimum setup timing margin and a minimum hold timing margin;

[0143] According to the second timing parameter set and the clock cycle corresponding to the output interface signal, the output delay of the nearest level fan-in register corresponding to the output interface signal is calculated and used as the target output delay.

[0144] In an optional embodiment, the target output delay includes: a maximum target output delay and a minimum target output delay, the maximum target output delay being a maximum signal delay corresponding to the output interface signal, the maximum signal delay being calculated based on a clock period and a minimum setup timing margin corresponding to the output interface signal;

[0145] The minimum target output delay is the minimum signal delay corresponding to the output interface signal. The minimum signal delay is calculated based on the minimum hold timing margin corresponding to the output interface signal.

[0146] In an optional embodiment, the first acquisition module 110 is specifically used to perform static timing analysis on the PR netlist based on the static timing analysis STA environment and the standard parasitic parameter exchange format file and standard timing constraint file of the PR netlist corresponding to the RTL module to obtain the static timing analysis results.

[0147] The above-mentioned device is used to execute the method provided in the above-mentioned embodiment. Its implementation principle and technical effect are similar and will not be repeated here.

[0148] The above modules can be one or more integrated circuits configured to implement the above methods, such as one or more application-specific integrated circuits (ASICs), one or more microprocessors, or one or more field programmable gate arrays (FPGAs). For another example, when a module is implemented by scheduling program code through a processing element, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules can be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0149] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device can be integrated into the above-mentioned post-simulation device. Figure 7 As shown, the electronic device may include: a processor 210, a storage medium 220, and a bus 230. The storage medium 220 stores machine-readable instructions executable by the processor 210. When the electronic device is running, the processor 210 and the storage medium 220 communicate via the bus 230, and the processor 210 executes the machine-readable instructions to perform the steps of the above-mentioned method embodiment. The specific implementation methods and technical effects are similar and will not be repeated here.

[0150] Optionally, the present application further provides a storage medium storing a computer program, which, when executed by a processor, executes the steps of the above method embodiment. The specific implementation and technical effects are similar and will not be described in detail here.

[0151] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0152] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0153] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0154] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) or a processor (English: processor) to perform some steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (English: Read-Only Memory, abbreviated: ROM), a random access memory (English: Random Access Memory, abbreviated: RAM), a disk or an optical disk, and other media that can store program code.

[0155] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0156] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application. It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A post-simulation method for an integrated circuit, characterized in that: The method comprises: Based on the static timing analysis STA environment, obtain the static timing analysis results of the physical implementation PR netlist corresponding to the register transfer level RTL module in the target integrated circuit; According to the static timing analysis results, obtain the average clock network delay corresponding to the interface register in the PR netlist, the target setup time and target hold time of each input interface signal, and the target output delay of each output interface signal; Constructing an interface signal delay model corresponding to the RTL module according to the average clock network delay, the target setup time and target hold time of each input interface signal, and the target output delay of each output interface signal; Post-simulation processing is performed according to the interface signal delay model and the RTL module.

2. The method according to claim 1, characterized in that Obtaining target setup time and target hold time of each input interface signal in the PR netlist according to the static timing analysis result includes: For each input interface signal, obtaining, based on the static timing analysis result, a first timing parameter set under the timing path where the input interface signal is located, the first timing parameter set including: a maximum setup timing margin, a minimum setup timing margin, a maximum hold timing margin, and a minimum hold timing margin; According to the first timing parameter set and the clock cycle corresponding to the input interface signal, the setup time and hold time of the nearest level fan-out register corresponding to the input interface signal are calculated, and the target setup time and the target hold time are used as the target setup time and the target hold time respectively.

3. The method according to claim 2, characterized in that The constructing of the interface signal delay model corresponding to the RTL module according to the average clock network delay, the target setup time and the target hold time of each input interface signal, and the target output delay of each output interface signal comprises: According to the average clock network delay, setting the clock source delay of the virtual clock in the external delay of the interface signal delay model; Setting each input interface of the interface signal delay model according to the target setup time and the target hold time of each input interface; Each output interface of the interface signal delay model is set according to the target output delay of each output interface signal.

4. The method according to claim 3, characterized in that The target setup time includes: a maximum target setup time and a minimum target setup time; the maximum target setup time is calculated based on the clock cycle and the minimum setup timing margin corresponding to the input interface signal; the minimum target setup time is calculated based on the clock cycle and the maximum setup timing margin corresponding to the input interface signal; The target hold time includes: a maximum target hold time and a minimum target hold time; the maximum target hold time is determined according to a maximum hold timing margin corresponding to the input interface signal, and the minimum target hold time is determined according to a minimum hold timing margin corresponding to the input interface signal.

5. The method according to claim 3, characterized in that The step of setting the virtual clock source delay in the interface signal delay model according to the average clock network delay includes: The clock source delay of the virtual clock in the interface signal delay model is set to a positive number of the average clock network delay.

6. The method according to claim 1, characterized in that Obtaining, according to the static timing analysis result, an average clock network delay corresponding to the interface register in the PR netlist, includes: Obtaining the clock network delay of each interface register in the PR netlist; According to the clock network delay of each interface register, an average clock network delay corresponding to the interface register is calculated.

7. The method according to claim 1, characterized in that Obtaining a target output delay of an output interface in the PR netlist according to the static timing analysis result includes: According to the static timing analysis result, obtaining a second timing parameter set under the timing path where the output interface signal is located, the second timing parameter set including: a minimum setup timing margin and a minimum hold timing margin; According to the second timing parameter set and the clock cycle corresponding to the output interface signal, the output delay of the nearest level fan-in register corresponding to the output interface signal is calculated and used as the target output delay.

8. The method according to claim 7, characterized in that The target output delay includes: a maximum target output delay and a minimum target output delay, wherein the maximum target output delay is a maximum signal delay corresponding to the output interface signal, and the maximum signal delay is calculated based on the clock period and a minimum setup timing margin corresponding to the output interface signal; The minimum target output delay is a minimum signal delay corresponding to the output interface signal, and the minimum signal delay is calculated based on a minimum hold timing margin corresponding to the output interface signal.

9. The method according to any one of claims 1 to 8, characterized in that The method of obtaining the static timing analysis result of the physical implementation PR netlist corresponding to the register transfer level (RTL) module in the target integrated circuit based on the static timing analysis (STA) environment includes: Based on the static timing analysis STA environment, according to the standard parasitic parameter exchange format file and standard timing constraint file of the PR netlist corresponding to the RTL module, static timing analysis is performed on the PR netlist to obtain static timing analysis results.

10. An electronic device, characterized in that: include: A processor, a storage medium, and a bus, wherein the storage medium stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the storage medium communicate via the bus, and the processor executes the machine-readable instructions to perform the steps of the post-simulation method of the integrated circuit as described in any one of claims 1 to 9.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the post-simulation method of an integrated circuit according to any one of claims 1 to 9 are executed.

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