Data error correction method and device, electronic equipment and computer readable storage medium

Abstract

The embodiment of the invention provides a data error correction method and device, electronic equipment and a computer readable storage medium, and relates to the technical field of storage, the bias reading voltage value of a storage unit of a memory is obtained, hard decoding is carried out according to the bias reading voltage value and a reference reading voltage value, and the data error correction efficiency is improved. The method comprises the following steps: acquiring a read voltage characteristic diagram of a memory, acquiring a reference log-likelihood ratio according to the read voltage characteristic diagram, a bias read voltage value and a reference read voltage value of the memory, if hard decoding fails, offsetting the reference read voltage value by the bias read voltage value in the read voltage characteristic diagram, and determining the CELL change quantity between the offset reference read voltage value and the reference read voltage value according to the read voltage characteristic diagram, and adjusting the reference log-likelihood ratio according to the CELL change number, and performing soft decoding according to the adjusted reference log-likelihood ratio. The log-likelihood ratio is adjusted according to the actual CELL change number, the more accurate log-likelihood ratio is obtained, the error correction performance of the LDPC is improved, the reliability of a memory is improved, and the service life of the memory is prolonged.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a data error correction method, device, electronic device and computer-readable storage medium. Background Art

[0002] With advancements in NAND Flash manufacturing processes and the demand for higher storage capacities, TLC (Triple-Level Cell) and QLC (Quad-Level Cell) technologies are becoming increasingly widely used. As the number of bits stored in each cell increases, the stored charge is more susceptible to changes after data is written, leading to data errors. To address this challenge, a growing number of algorithms are being applied to NAND Flash data error correction.

[0003] The Log-Likelihood Ratio (LLR) refers to the logarithm of the ratio of likelihood information, and its value can be understood as the degree of confidence in each bit in the data. TLC and QLC particles have high error rates, and traditional error correction methods cannot handle such a high number of flipped bits. To address these problems, the more commonly used error correction method is the LDPC algorithm. During the LDPC decoding process, the correct determination of the soft information log-likelihood ratio is crucial to fully utilize the error correction capability. The traditional method is to fix the log-likelihood ratio. Regardless of the number of erases and reads, or in high or low temperature environments or data retention scenarios, the log-likelihood ratio is fixed in a table. However, the log-likelihood ratio values ​​stored in this table are limited, and it is difficult to accurately match the log-likelihood ratio values ​​required in actual error scenarios. This makes it difficult to fully utilize the decoding performance of LDPC, which in turn affects the reliability and life of the memory. Summary of the Invention

[0004] The object of the present invention is to provide a data error correction method, device, electronic device and computer-readable storage medium to solve the problem that it is difficult to fully utilize the maximum decoding performance of LDPC, thereby affecting the reliability and life of the memory.

[0005] In a first aspect, the present invention provides a data error correction method, the method comprising:

[0006] Obtaining a bias read voltage value of a memory cell of the memory;

[0007] Performing hard decoding according to the biased read voltage value and the reference read voltage value, and obtaining a reference log-likelihood ratio according to a read voltage characteristic diagram of the memory, the biased read voltage value, and the reference read voltage value;

[0008] If hard decoding fails, offsetting the reference read voltage value in the read voltage characteristic diagram by the biased read voltage value;

[0009] determining a cell change amount between the offset reference read voltage value and the reference read voltage value according to the read voltage characteristic diagram, and adjusting the reference log-likelihood ratio according to the cell change amount;

[0010] Soft decoding is performed based on the adjusted reference log-likelihood ratio.

[0011] In an optional embodiment, determining the cell change amount between the offset reference read voltage value and the reference read voltage value according to the read voltage characteristic diagram includes:

[0012] Obtaining, according to the read voltage characteristic diagram, the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value;

[0013] The cell change number is obtained according to the cell number corresponding to the reference read voltage value and the cell number corresponding to the offset reference read voltage value.

[0014] In an optional implementation manner, after performing soft decoding according to the adjusted reference log-likelihood ratio, the method further includes:

[0015] If soft decoding fails, get the number of offsets;

[0016] If the number of offsets is less than the preset number of offsets, continue adjusting the adjusted reference log-likelihood ratio until soft decoding is successful;

[0017] If the number of shifts is equal to the preset number of shifts, then the adjustment of the adjusted reference log-likelihood ratio is stopped.

[0018] In an optional implementation, the performing hard decoding according to the biased read voltage value and the reference read voltage value includes:

[0019] determining a voltage state of the memory cell according to the bias read voltage value and a reference read voltage value;

[0020] The voltage state is read and verified. If the voltage state verification fails, it is determined that the hard decoding fails. If the voltage state verification succeeds, it is determined that the hard decoding succeeds.

[0021] In an optional embodiment, obtaining a reference log-likelihood ratio according to a read voltage characteristic diagram of the memory, the biased read voltage value, and the reference read voltage value includes:

[0022] dividing the read voltage characteristic diagram into a plurality of intervals according to the bias read voltage value and the reference read voltage value;

[0023] Obtaining the number of storage units with bit values ​​of 0 and the number of storage units with bit values ​​of 1 in the memory within each of the intervals;

[0024] According to the number of storage units with bit values ​​of 0 and the number of storage units with bit values ​​of 1 in the memory within each of the intervals, a reference log-likelihood ratio corresponding to each of the intervals is obtained.

[0025] In an optional embodiment, obtaining the reference log-likelihood ratio corresponding to each interval according to the number of storage units with bit values ​​of 0 and the number of storage units with bit values ​​of 1 in the memory within each interval includes:

[0026] Calculating the probability that the bit value of the storage unit in the memory in each of the intervals is 0 and the probability that the bit value is 1 according to the number of storage units with bit values ​​0 and the number of storage units with bit values ​​1 in the memory in each of the intervals;

[0027] The ratio of the probability that the bit value of the storage unit in the memory is 0 to the probability that the bit value is 1 in each of the intervals is calculated, and the logarithm of the ratio is calculated to obtain a reference log-likelihood ratio corresponding to each of the intervals.

[0028] In an optional embodiment, adjusting the reference log-likelihood ratio according to the number of cell changes includes:

[0029] The reference log-likelihood ratio is adjusted according to the CELL change quantity and a preset relationship model to obtain an adjusted reference log-likelihood ratio.

[0030] In a second aspect, the present invention provides a data error correction device, comprising:

[0031] A bias read voltage value obtaining module, used for obtaining a bias read voltage value of a storage unit of the memory;

[0032] a hard decoding module, configured to perform hard decoding according to the biased read voltage value and the reference read voltage value, and obtain a reference log-likelihood ratio according to a read voltage characteristic diagram of the memory, the biased read voltage value, and the reference read voltage value;

[0033] an offset module, configured to offset the reference read voltage value in the read voltage characteristic diagram by the biased read voltage value if hard decoding fails;

[0034] a log-likelihood ratio adjustment module, configured to determine a cell change amount between the offset reference read voltage value and the reference read voltage value according to the read voltage characteristic diagram, and adjust the reference log-likelihood ratio according to the cell change amount;

[0035] The soft decoding module is used to perform soft decoding according to the adjusted reference log-likelihood ratio.

[0036] In an optional embodiment, the log-likelihood ratio adjustment module is further used to obtain the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value based on the read voltage characteristic diagram; and obtain the number of cells changed based on the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value.

[0037] In a third aspect, the present invention provides an electronic device comprising a processor and a memory, wherein the memory stores a computer program executable by the processor, and the computer program executable by the processor is used to implement the data error correction method described in any of the aforementioned embodiments.

[0038] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the data error correction method as described in any one of the aforementioned embodiments.

[0039] Embodiments of the present invention provide a data error correction method, apparatus, electronic device, and computer-readable storage medium. The method includes obtaining a biased read voltage value of a memory cell, performing hard decoding based on the biased read voltage value and a reference read voltage value, and obtaining a reference log-likelihood ratio based on a read voltage characteristic diagram of the memory, the biased read voltage value, and the reference read voltage value. If the hard decoding fails, the reference read voltage value is offset by the biased read voltage value in the read voltage characteristic diagram, the number of cell changes between the offset reference read voltage value and the reference read voltage value is determined based on the read voltage characteristic diagram, the reference log-likelihood ratio is adjusted based on the number of cell changes, and soft decoding is performed based on the adjusted reference log-likelihood ratio. By adjusting the log-likelihood ratio based on the actual number of cell changes, a more accurate log-likelihood ratio is obtained, thereby improving the error correction performance of LDPC (Low-Level Parity Check), and thereby improving the reliability and lifespan of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0041] Figure 1 A schematic diagram of a flow chart of a data error correction method provided by an embodiment of the present invention is shown;

[0042] Figure 2 A schematic diagram showing a read voltage characteristic diagram of a memory provided by an embodiment of the present invention;

[0043] Figure 3 Another schematic diagram showing a read voltage characteristic diagram of a memory provided by an embodiment of the present invention;

[0044] Figure 4 Another schematic diagram showing a read voltage characteristic diagram of a memory provided by an embodiment of the present invention;

[0045] Figure 5 A module block diagram of a data error correction device provided by an embodiment of the present invention is shown;

[0046] Figure 6 A block diagram of an electronic device provided by an embodiment of the present invention is shown.

[0047] Icons: 100 - electronic device; 110 - memory; 120 - processor; 130 - communication module; 200 - data error correction device; 210 - biased reading voltage value acquisition module; 220 - hard decoding module; 230 - offset module; 240 - log-likelihood ratio adjustment module; 250 - soft decoding module. DETAILED DESCRIPTION

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0049] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0050] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0051] See also Figure 1 , Figure 1 A flow chart of a data error correction method provided by an embodiment of the present invention is shown. The data error correction method can be applied to electronic devices. The following takes electronic devices as an example to illustrate the specific process of this embodiment. Figure 1 The process shown is described in detail. The data error correction method may specifically include the following steps:

[0052] Step 110: Obtain a bias read voltage value of a memory cell of the memory.

[0053] The memory may be a NAND Flash non-volatile memory, and the storage unit may be an SLC (Single Level Cell), an MLC (Multi Level Cell), a TLC, or a QLC.

[0054] In some embodiments, the electronic device reads a bias read voltage value of a memory cell requiring error correction from a memory, where the bias read voltage value reflects a data storage state of the memory cell.

[0055] Step 120 : performing hard decoding according to the biased read voltage value and the reference read voltage value, and obtaining a reference log-likelihood ratio according to the read voltage characteristic diagram of the memory, the biased read voltage value, and the reference read voltage value.

[0056] It should be noted that hard decoding is a commonly used decoding method in digital communication and storage systems. Hard decoding extracts the most likely original data bits from the biased read voltage. The memory read voltage characteristic diagram is used to describe the distribution of the memory cells (CELL) under different read voltages. Figure 2 As shown, the horizontal axis of the read voltage characteristic graph is the read voltage, and the vertical axis of the read voltage characteristic graph is the number of cells.

[0057] In some embodiments, the reference read voltage value may be determined according to a Gray code.

[0058] For example, each memory cell can store two bits, resulting in four states (00, 01, 11, and 10). These four states are represented using Gray code as shown in Table 1. Three reference read voltage values ​​(R1, R2, and R3) are set to distinguish these four states. Assuming the voltage ranges corresponding to these four states are: state 00: 0.0V-1.0V; state 01: 1.0V-2.0V; state 10: 2.0V-3.0V; and state 11: 3.0V-4.0V, R1 is set between the voltage ranges of states 00 and 01, R2 is set between the voltage ranges of states 01 and 10, and R3 is set between the voltage ranges of states 10 and 11. Thus, the reference read voltage values ​​are R1 = 0.5V, R2 = 1.5V, and R3 = 2.5V, respectively.

[0059] state Gray code 00 00 01 01 10 11 11 10

[0060] Table 1

[0061] It's important to note that only one bit differs between two consecutive states. Even a slight shift in the read voltage will only result in a single bit error, not multiple bits simultaneously. For example, if the read voltage fluctuates around 1.0V, the Gray code encoding of states 01 and 10 will only result in a single bit change, rather than being misread as completely different states. This reduces the probability of misreading.

[0062] In some embodiments, the number of reference read voltage values ​​may be one or more, depending on the actual situation. The reference read voltage value may be set between two peaks in the read voltage characteristic graph, for example, Figure 2 As shown, if the number of reference read voltage values ​​is one, R1 can be used as the reference read voltage value; if the number of reference read voltage values ​​is two, R1 and R5 can be used as the reference read voltage values.

[0063] Step 130 : If the hard decoding fails, the reference read voltage value is offset by the biased read voltage value in the read voltage characteristic diagram.

[0064] The offset direction of the reference read voltage value in the read voltage characteristic diagram depends on the distribution of the read voltage characteristic diagram. For example, if the read window between two peaks is narrow, the reference read voltage value between the two peaks can be offset to the left to expand the read window. It should be noted that if the reference read voltage value is offset to the left, more memory cells will be judged as having a lower data state. When the memory is prone to misjudgment at a higher read voltage state, offsetting the reference read voltage value to the left can reduce the bit error rate at the higher read voltage state. If the reference read voltage value is offset to the right, more memory cells will be judged as having a higher data state. When the memory is prone to misjudgment at a lower read voltage value, offsetting the reference read voltage value to the right can reduce the bit error rate at the lower read voltage value.

[0065] For example, Figure 3 As shown, the offset read voltage value is 80mv. If the reference read voltage values ​​are R1 and R5, then R1 and R5 are both offset to the left by 80mv, and the reference read voltage values ​​after the offset are R1a and R5a respectively.

[0066] Step 140 : Determine the cell change number between the offset reference read voltage value and the reference read voltage value according to the read voltage characteristic diagram, and adjust the reference log-likelihood ratio according to the cell change number.

[0067] Step 150: Perform soft decoding according to the adjusted reference log-likelihood ratio.

[0068] It should be noted that the soft decoding can use the adjusted reference log-likelihood ratio to gradually correct data errors through an iterative algorithm.

[0069] The data error correction method provided by an embodiment of the present invention obtains a biased read voltage value of a memory cell, performs hard decoding based on the biased read voltage value and a reference read voltage value, and obtains a reference log-likelihood ratio based on a read voltage characteristic diagram of the memory, the biased read voltage value, and the reference read voltage value. If the hard decoding fails, the reference read voltage value is offset by the biased read voltage value in the read voltage characteristic diagram, the number of cell changes between the offset reference read voltage value and the reference read voltage value is determined based on the read voltage characteristic diagram, the reference log-likelihood ratio is adjusted based on the number of cell changes, and soft decoding is performed based on the adjusted reference log-likelihood ratio. By adjusting the log-likelihood ratio based on the actual number of cell changes, a more accurate log-likelihood ratio is obtained, thereby improving the error correction performance of LDPC (Low-Level Parity Check), and thereby improving the reliability and lifespan of the memory.

[0070] In some embodiments, since the log-likelihood ratio indicates the reliability of a bit and the number of cell changes has an explicit relationship with the log-likelihood ratio, a relationship model can be established and stored in the electronic device, where the relationship model characterizes the relationship between the number of cell changes, the reference log-likelihood ratio, and the adjusted reference log-likelihood ratio.

[0071] In this embodiment, the reference log-likelihood ratio may be adjusted according to the number of cell changes and a preset relationship model to obtain an adjusted reference log-likelihood ratio.

[0072] In an example, assuming the number of offset reads is 5, the relationship model can be established as follows:

[0073] (LLR4,LLR5,LLR6)=f(B1,B2,B3,B4,LLR1,LLR2,LLR3)

[0074] Among them, B1, B2, B3, B4 are the number of CELL changes, LLR4, LLR5, LLR6 are the adjusted reference log-likelihood ratios, LLR1, LLR2, LLR3 are the reference log-likelihood ratios, and f is the relationship model.

[0075] In some implementations, the relationship model may be set based on professional experience and historical data, such as a function relationship model, a rule relationship model, or other possible relationship models.

[0076] As an implementation, when the relationship model is a rule-based relationship model, it can be represented by a table. For example, as shown in Table 2, LLR1 is the reference log-likelihood ratio, LLR2 is the adjusted reference log-likelihood ratio, d and e are adjustment parameters determined based on experience, B2 is the number of cell changes after the current shift, and B1 is the number of cell changes after the previous shift.

[0077] LLR1 LLR2 if B2>B1 -b -llr1+d if B2<B1 -b -llr1-e ifB2==B1 -b -llr1

[0078] Table 2

[0079] As another embodiment, when the relationship model is a functional relationship, the reference log-likelihood ratio can be adjusted based on the functional relationship and the number of cell changes. For example, the functional relationship can be LLR2 = w1*LLR1 + w2*B1, where LLR1 is the reference log-likelihood ratio, LLR2 is the adjusted reference log-likelihood ratio, B1 is the number of cell changes after the current offset, and w1 and w2 are adjustment parameters, which can be set based on experience.

[0080] In order to reduce the error correction time, the following steps are specifically included after step 150: if the soft decoding fails, obtain the number of offsets; if the number of offsets is less than the preset number of offsets, continue to adjust the adjusted reference log-likelihood ratio until the soft decoding is successful; if the number of offsets is equal to the preset number of offsets, stop adjusting the adjusted reference log-likelihood ratio.

[0081] It is understandable that during the data error correction process, the reference read voltage value will be gradually increased or decreased. By gradually increasing the reference read voltage value, the reference log-likelihood ratio can be gradually adjusted, so that the LDPC algorithm gradually adapts to the reference read voltage value, which can reduce decoding failures caused by excessive increase or decrease at one time, thereby reducing the number of offsets and improving the decoding capability of LDPC.

[0082] In some embodiments, step 120 specifically further includes the following steps: determining the voltage state of the storage unit based on the bias read voltage value and the reference read voltage value; reading the voltage state and verifying the voltage state, and if the voltage state verification fails, determining that the hard decoding fails, and if the voltage state verification succeeds, determining that the hard decoding succeeds.

[0083] In some embodiments, the electronic device may compare the biased read voltage value with the reference read voltage value, and determine the voltage state of the memory cell according to the comparison result.

[0084] It can be understood that the voltage state refers to whether the logic value stored in the corresponding storage location of the memory cell is logic 1 or logic 0.

[0085] For example, if the reference read voltage value is R1, and the biased read voltage value is greater than or equal to the reference read voltage value, it is determined that the storage location corresponding to the memory cell stores a logic "1"; if the biased read voltage value is less than the reference read voltage value, it is determined that the storage location corresponding to the memory cell stores a logic "0." If the reference read voltage values ​​are R1 and R5, and the biased read voltage value is less than R1 or greater than or equal to R5, it is determined that the storage location corresponding to the memory cell stores a logic "1"; if the biased read voltage value is greater than or equal to R1 and less than R5, it is determined that the storage location corresponding to the memory cell stores a logic "0."

[0086] It should be noted that if the bias read voltage value is inaccurate, the data bit in the memory cell cannot be correctly identified, resulting in an incorrect determination of the memory cell's voltage state. In this case, the voltage state check fails, and thus the hard decoding fails. For example, if the bias read voltage value is too high or too low, a data bit that should be a logic "0" may be incorrectly decoded as a logic "1."

[0087] In order to obtain the reference log-likelihood ratio corresponding to each interval, step 120 specifically also includes the following steps: dividing the read voltage characteristic diagram into multiple intervals according to the biased read voltage value and the reference read voltage value; obtaining the number of storage cells with bit values ​​of 0 and the number of storage cells with bit values ​​of 1 in the memory in each interval; and obtaining the reference log-likelihood ratio corresponding to each interval according to the number of storage cells with bit values ​​of 0 and the number of storage cells with bit values ​​of 1 in the memory in each interval.

[0088] In some embodiments, the probability of the bit value of the storage unit in the memory in each interval being 0 and the probability of the bit value being 1 are calculated based on the number of storage units with bit value 0 and the number of storage units with bit value 1 in the memory in each interval, the ratio of the probability of the bit value of the storage unit in the memory in each interval being 0 to the probability of the bit value being 1 is calculated, and the comparison value is logarithmically calculated to obtain a reference log-likelihood ratio corresponding to each interval.

[0089] For example, Figure 4 As shown, the biased read voltage value is V2, the reference read voltage value is V1, and the read voltage characteristic diagram is divided into three intervals: interval A, interval B, and interval C according to the biased read voltage value V2 and the reference read voltage value V1. Taking the reference log-likelihood ratio corresponding to interval A as an example, the number of storage cells with bit values ​​of 0 in the memory in interval A is 1000, and the number of storage cells with bit values ​​of 1 is 500. The probability that the bit value of the storage cell in the memory in interval A is 0 is 2 / 3 (1000 / 1500=2 / 3), and the probability that the bit value of the storage cell in the memory in interval A is 1 is 1 / 3 (500 / 1500=1 / 3). The reference log-likelihood ratio corresponding to interval A is 0.3

[0090] In some embodiments, step 140 specifically further includes the following steps: obtaining the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value according to the read voltage characteristic diagram; obtaining the number of cell changes according to the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value.

[0091] In some embodiments, the electronic device is provided with a preset operation rule, and the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value are calculated according to the preset operation rule to obtain the number of cell changes. The preset operation rule may be addition, subtraction, multiplication, division, exclusive OR, or exclusive OR.

[0092] For example, the default operation rule is XOR, such as Figure 4As shown, the number of cells corresponding to the reference read voltage value is 3 (CELL2), and the number of cells corresponding to the offset reference read voltage value is 5 (CELL1). The number of cells 3 corresponding to the reference read voltage value is converted to binary 011, and the number of cells 5 corresponding to the offset reference read voltage value is converted to binary 101. An XOR operation is performed on 101 and 011 to obtain a cell change number of 110 (6 in decimal).

[0093] In order to execute the corresponding steps in the above embodiments and various possible methods, a method for implementing a data error correction device is given below. Figure 5 , FIG is a functional module diagram of a data error correction device provided by an embodiment of the present invention. It should be noted that the basic principle and technical effects of the data error correction device provided by this embodiment are the same as those of the above embodiment. For the sake of simplicity, for parts not mentioned in this embodiment, reference can be made to the corresponding contents of the above embodiment. The data error correction device 200 includes: a biased reading voltage value acquisition module 210, a hard decoding module 220, an offset module 230, a log-likelihood ratio adjustment module 240, and a soft decoding module 250, wherein:

[0094] A bias read voltage value obtaining module 210 is used to obtain a bias read voltage value of a storage unit of the memory;

[0095] The hard decoding module 220 is configured to perform hard decoding according to the biased read voltage value and the reference read voltage value, and obtain a reference log-likelihood ratio according to the read voltage characteristic diagram of the memory, the biased read voltage value and the reference read voltage value.

[0096] The offset module 230 is configured to offset the reference read voltage value by an offset read voltage value in the read voltage characteristic diagram if the hard decoding fails.

[0097] The log-likelihood ratio adjustment module 240 is configured to determine the cell variation number between the reference read voltage value after the shift and the reference read voltage value according to the read voltage characteristic diagram, and adjust the reference log-likelihood ratio according to the cell variation number.

[0098] The soft decoding module 250 is configured to perform soft decoding according to the adjusted reference log-likelihood ratio.

[0099] Furthermore, the log-likelihood ratio adjustment module 240 is further configured to obtain the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value according to the read voltage characteristic diagram; and obtain the number of cell changes according to the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value.

[0100] Furthermore, the offset module 230 is also used to obtain the number of offsets if soft decoding fails; if the number of offsets is less than the preset number of offsets, continue to adjust the adjusted reference log-likelihood ratio until the soft decoding is successful; if the number of offsets is equal to the preset number of offsets, stop adjusting the adjusted reference log-likelihood ratio.

[0101] Furthermore, the hard decoding module 220 is also used to determine the voltage state of the storage unit based on the biased read voltage value and the reference read voltage value; read the voltage state and verify the voltage state. If the voltage state verification fails, it is determined that the hard decoding has failed; if the voltage state verification succeeds, it is determined that the hard decoding has succeeded.

[0102] Furthermore, the hard decoding module 220 is also used to divide the read voltage characteristic diagram into multiple intervals according to the biased read voltage value and the reference read voltage value; obtain the number of storage cells with bit values ​​of 0 and the number of storage cells with bit values ​​of 1 in the memory in each interval; and obtain the reference log-likelihood ratio corresponding to each interval according to the number of storage cells with bit values ​​of 0 and the number of storage cells with bit values ​​of 1 in the memory in each interval.

[0103] Furthermore, the hard decoding module 220 is also used to calculate the probability that the bit value of the storage unit in the memory in each interval is 0 and the probability that the bit value is 1 based on the number of storage units with bit value 0 and the number of storage units with bit value 1 in the memory in each interval; calculate the ratio of the probability that the bit value of the storage unit in the memory in each interval is 0 to the probability that the bit value is 1, and perform logarithmic calculation on the comparison value to obtain a reference log-likelihood ratio corresponding to each interval.

[0104] Furthermore, the log-likelihood ratio adjustment module 240 is further configured to adjust the reference log-likelihood ratio according to the number of cell changes and a preset relationship model to obtain an adjusted reference log-likelihood ratio.

[0105] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0106] In several embodiments provided by the present invention, the coupling between modules can be electrical, mechanical or other forms of coupling.

[0107] In addition, the functional modules in various embodiments of the present invention may be integrated into a single processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules.

[0108] Please refer to Figure 6 is a block diagram of an electronic device 100 provided in an embodiment of the present invention. Electronic device 100 includes a memory 110, a processor 120, and a communication module 130. The memory 110, processor 120, and communication module 130 are electrically connected to each other, directly or indirectly, to enable data transmission or exchange. For example, these components may be electrically connected to each other via one or more communication buses or signal lines.

[0109] Memory 110 is used to store programs or data. Memory 110 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0110] The processor 120 is used to read / write data or programs stored in the memory and execute corresponding functions. For example, when the computer program stored in the memory 110 is executed by the processor 120, the data error correction method disclosed in the above embodiments can be implemented.

[0111] The communication module 130 is used to establish a communication connection between the electronic device 100 and other devices through a network, and to send and receive data through the network.

[0112] It should be understood that Figure 6 The structure shown is only a schematic diagram of the structure of the electronic device. The electronic device may also include Figure 6 More or fewer components may be shown. Figure 6 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0113] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the data error correction method described in the above method embodiment is implemented.

[0114] The computer-readable storage medium may be an electronic memory such as a flash memory, an EEPROM (Electrically Erasable Programmable Read-Only Memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer-readable storage medium includes a non-transitory computer-readable storage medium. The computer-readable storage medium has storage space for program codes for executing any of the method steps described above. These program codes can be read from or written to one or more computer program products. The program codes can be compressed, for example, in an appropriate form.

[0115] In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the devices, methods, and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or part of the code, which contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, as well as the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified functions or actions, or can be implemented using a combination of dedicated hardware and computer instructions.

[0116] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0117] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A data error correction method, characterized in that: The method comprises: Obtaining a bias read voltage value of a memory cell of the memory; Performing hard decoding according to the biased read voltage value and the reference read voltage value, and obtaining a reference log-likelihood ratio according to a read voltage characteristic diagram of the memory, the biased read voltage value, and the reference read voltage value; If hard decoding fails, offsetting the reference read voltage value in the read voltage characteristic diagram by the biased read voltage value; determining a cell change amount between the offset reference read voltage value and the reference read voltage value according to the read voltage characteristic diagram, and adjusting the reference log-likelihood ratio according to the cell change amount; Soft decoding is performed based on the adjusted reference log-likelihood ratio.

2. The method according to claim 1, characterized in that The determining, according to the read voltage characteristic diagram, the number of cell changes between the offset reference read voltage value and the reference read voltage value includes: Obtaining, according to the read voltage characteristic diagram, the number of cells corresponding to the reference read voltage value and the number of cells corresponding to the offset reference read voltage value; The cell change number is obtained according to the cell number corresponding to the reference read voltage value and the cell number corresponding to the offset reference read voltage value.

3. The method according to claim 1, characterized in that After performing soft decoding according to the adjusted reference log-likelihood ratio, the method further includes: If soft decoding fails, get the number of offsets; If the number of offsets is less than the preset number of offsets, continue adjusting the adjusted reference log-likelihood ratio until soft decoding is successful; If the number of shifts is equal to the preset number of shifts, then the adjustment of the adjusted reference log-likelihood ratio is stopped.

4. The method according to claim 1, wherein The hard decoding according to the biased read voltage value and the reference read voltage value includes: determining a voltage state of the memory cell according to the bias read voltage value and a reference read voltage value; The voltage state is read and verified. If the voltage state verification fails, it is determined that the hard decoding fails. If the voltage state verification succeeds, it is determined that the hard decoding succeeds.

5. The method according to claim 1, wherein Obtaining a reference log-likelihood ratio according to the read voltage characteristic diagram of the memory, the biased read voltage value, and the reference read voltage value includes: dividing the read voltage characteristic diagram into a plurality of intervals according to the bias read voltage value and the reference read voltage value; Obtaining the number of storage units with bit values ​​of 0 and the number of storage units with bit values ​​of 1 in the memory within each of the intervals; According to the number of storage units with bit values ​​of 0 and the number of storage units with bit values ​​of 1 in the memory within each of the intervals, a reference log-likelihood ratio corresponding to each of the intervals is obtained.

6. The method according to claim 5, characterized in that Obtaining the reference log-likelihood ratio corresponding to each interval according to the number of storage units with bit values ​​of 0 and the number of storage units with bit values ​​of 1 in the memory in each interval includes: calculating the probability that the bit value of the storage unit in the memory in each interval is 0 and the probability that the bit value is 1 according to the number of storage units with bit values ​​of 0 and the number of storage units with bit values ​​of 1 in the memory in each interval; The ratio of the probability that the bit value of the storage unit in the memory is 0 to the probability that the bit value is 1 in each of the intervals is calculated, and the logarithm of the ratio is calculated to obtain a reference log-likelihood ratio corresponding to each of the intervals.

7. The method according to claim 1, characterized in that The adjusting the reference log-likelihood ratio according to the number of cell changes includes: The reference log-likelihood ratio is adjusted according to the CELL change quantity and a preset relationship model to obtain an adjusted reference log-likelihood ratio.

8. A data error correction device, characterized in that: The device comprises: A bias read voltage value obtaining module, used for obtaining a bias read voltage value of a storage unit of the memory; a hard decoding module, configured to perform hard decoding according to the biased read voltage value and the reference read voltage value, and obtain a reference log-likelihood ratio according to a read voltage characteristic diagram of the memory, the biased read voltage value, and the reference read voltage value; an offset module, configured to offset the reference read voltage value in the read voltage characteristic diagram by the biased read voltage value if hard decoding fails; a log-likelihood ratio adjustment module, configured to determine a cell change amount between the offset reference read voltage value and the reference read voltage value according to the read voltage characteristic diagram, and adjust the reference log-likelihood ratio according to the cell change amount; The soft decoding module is used to perform soft decoding according to the adjusted reference log-likelihood ratio.

9. An electronic device, characterized in that: The device comprises a processor and a memory, wherein the memory stores a computer program executable by the processor, and the computer program executable by the processor is used to implement the data error correction method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data error correction method according to any one of claims 1 to 7 is implemented.

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