Component carrier and method of manufacturing a component carrier

Abstract

A component carrier and a method of manufacturing a component carrier are described wherein the component carrier comprises: i) an inorganic carrier structure; ii) an electrically insulating layer structure comprising a resin and a reinforcement structure on the inorganic carrier structure; iii) an ultrathin insulating film on the electrically insulating layer structure; and iv) an electrically conductive structure having a fine line pattern directly on the ultra-thin insulating film.

Description

Technical Field

[0001] The present invention relates to a component carrier having an inorganic carrier structure, an electrically insulating layer structure, an ultrathin insulating film, and an electrically conductive structure having a fine line pattern directly on the ultrathin insulating film. Furthermore, the present invention relates to a method for producing the component carrier.

[0002] Thus, the present invention may relate to the technical field of component carriers such as printed circuit boards or IC substrates and their manufacture. Background Art

[0003] Against the backdrop of the increasing number of product functions in component carriers equipped with one or more electronic components, the increasing miniaturization of such electronic components, and the increasing number of electronic components mounted on component carriers such as printed circuit boards, increasingly powerful array-like components or packages with multiple electronic components are being used. These array-like components or packages have multiple contacts or connections with increasingly smaller spacing between these contacts. Removing the heat generated by such electronic components and the component carriers themselves during operation is becoming an increasingly serious problem. In addition, effectively preventing electromagnetic interference (EMI) is also becoming an increasingly serious problem. At the same time, component carriers should have mechanical robustness as well as electrical and magnetic reliability in order to operate even under harsh conditions.

[0004] In particular, providing a component carrier with fine line pattern metal traces on the one hand and high stiffness (stability) on the other hand may be considered a challenge.

[0005] Figure 3 A cross-section of a conventional circuit board 200 is shown. The circuit board 200 includes a glass core 210 with an insulating layer 220 (Ajinomoto laminate film, ABF) on top. A solder resist layer 250 is further provided on top of the insulating layer. An IC chip 260 is arranged on top of the circuit board 200. To electrically connect the IC chip 260 to the circuit board 200 stack, solder balls 265 are formed, which electrically connect the IC chip pad 261 to the component carrier pad 242. The component carrier pad 242 is part of the patterned copper layer 240 located on top of the insulating layer 220 and is embedded in the solder resist material 250. The component carrier pad 242 is also connected to another component carrier pad 286 located on the glass core 210 by a blind laser via and is embedded in the insulating layer 220. The embedded component carrier pad of the patterned copper layer 240 can be manufactured on top of the ABF layer 220 using a semi-additive manufacturing process (SAP).

[0006] Figure 4 Shown Figure 3A variant of the present invention is provided in which an additional insulating layer 280 (ABF) is provided between the insulating layer 220 and the glass core 210. Thus, an additional component carrier pad 286 is embedded in the insulating layer material (ABF).

[0007] However, this architecture may have some disadvantages, especially in terms of metal trace stability and fine-line patterning.

[0008] First, a seed layer is formed on the glass core 210 in order to form the additional component carrier pad 186. This is usually done by sputtering Ti / Cu or high-build electroless copper processes, resulting in high costs.

[0009] Secondly, the formation of the fine line structure may be limited by the formation process of the insulating layer 220 (ABF), for example, the insulating layer 220 is conventionally formed by SAP.

[0010] Furthermore, stiffness may be limited, and this problem may further lead to susceptibility to cracking in case of multiple layers or thermal shock. Summary of the Invention

[0011] The present invention may require providing a component carrier with fine line patterning and high stability in an efficient and reliable manner.

[0012] A component carrier and a method for producing the same are described.

[0013] According to a first aspect of the invention, a component carrier (e.g. printed circuit board, IC substrate, interposer) is described, wherein the component carrier comprises (a stack-up having):

[0014] i) Inorganic support structure (e.g. glass core);

[0015] ii) an (organic) electrically insulating layer structure comprising a resin (e.g. epoxy resin) and a reinforcement structure (e.g. glass fibre) on an inorganic carrier structure (e.g. provided as a prepreg);

[0016] iii) an ultra-thin insulating film on an electrically insulating layer structure; and

[0017] iv) An electrically conductive (layer) structure (eg a patterned electrically conductive layer structure, in particular a metal trace) with a fine line pattern (eg a line pitch of 10 / 10 μm or less) directly on an ultra-thin insulating film.

[0018] According to a second aspect of the invention, a method for producing a component carrier is described, wherein the method comprises:

[0019] i) providing an inorganic support structure;

[0020] ii) applying (e.g. laminating) an electrically insulating layer structure (e.g. a prepreg) on ​​the inorganic carrier structure, the electrically insulating layer structure comprising a resin and a reinforcement structure;

[0021] iii) applying an ultra-thin insulating film on the electrically insulating layer structure; and

[0022] iv) directly forming an electrically conductive layer structure with a fine line pattern on an ultra-thin insulating film (eg, by a SAP process).

[0023] In this document, the term "component carrier" can refer to both the final component carrier product and the component carrier preform (i.e., a component carrier in production, in other words, a semi-finished product). In an example, a component carrier preform can be a panel consisting of multiple semi-finished component carriers manufactured together. At the final stage, the panel can be separated into multiple final component carrier products.

[0024] In an embodiment, a component carrier "stack" comprises at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier can be a laminate of the mentioned electrically insulating layer structure and the electrically conductive layer structure, in particular, the component carrier is formed by applying mechanical pressure and / or heat energy. The mentioned stack can provide a plate-like component carrier that can provide a large mounting surface for additional components. In an example, the stack can still be very thin and compact. In another example, for high-density products, the stack can be very thick. The stacking direction (height / thickness) can be arranged in the vertical direction z. In addition, the stacking direction can be perpendicular to the two main extension directions of the (plate-like) component carrier (along x and y). In an example, all layers of the component carrier can form a stack. In another example, only a portion of the layers of the component carrier form a stack.

[0025] In this context, the term "layer structure" may particularly refer to a continuous or discontinuous layer (or separated islands in the same plane) of electrically conductive or insulating material. A plurality of such layers are stacked parallel to each other on top of each other and may form a stack in the vertical direction.

[0026] As used herein, the term "electrically conductive layer structure" may refer to an electrically conductive structure (e.g., metal, particularly copper, more particularly copper foil, or carbon, particularly graphene, for example, as a layer) that has been patterned, for example, by a subtractive or additive process, such as by (wet or plasma) etching. After patterning, the electrically conductive structure may, for example, include a plurality of electrically conductive (metal, e.g., copper) traces and / or pads and / or interconnects and / or conductive paths / areas. In this manner, electrical connections within the component carrier may be provided.

[0027] In this document, the term "inorganic carrier structure" may refer to a (layer) structure (e.g., an electrically insulating layer structure and / or a solder mask structure) that is suitable for use as a support (base layer) for an accumulated layer. The inorganic carrier structure preferably comprises or consists of an inorganic material, such as glass, ceramic, quartz or a semiconductor material. Thus, the inorganic carrier structure may be (substantially) free of organic materials such as resins. In an example, at least one via connection (e.g., a through hole / blind via) may be formed through the inorganic carrier structure for electrical connection within the component carrier stack.

[0028] In this document, the term "ultra-thin insulating film" may refer to a layer structure (particularly a foil-like structure) comprising or consisting of an electrically insulating (dielectric) material. In an embodiment, the term "ultra-thin" may particularly refer to a thickness in the range of 1 μm to 20 μm, particularly 2 μm to 15 μm. Preferably, the ultra-thin insulating film is configured to achieve high adhesion to the electrically conductive layer structure directly on top. This can be achieved, for example, by high surface roughness. The ultra-thin insulating film may be a mixture of different materials, such as a composite material. For example, the ultra-thin insulating film may include a polymer mixture, such as a rigid thermosetting resin and / or a reactive low-polarity polymer. In addition, the ultra-thin insulating film may contain fillers (particles), such as inorganic fillers. In one example, the ultra-thin insulating film includes a low CTE (coefficient of thermal expansion) material (e.g., about 18 ppm / °C). In an example, the ultra-thin insulating film may be provided with a thin metal (copper) foil (e.g., with a thickness in the range of 1 to 3 μm) for protection and / or for producing a high surface roughness (as a mirror image of the high surface roughness of the thin metal foil). The metal layer may be used as a seed layer or may be removed (by etching) to enable formation of another seed layer.The ultra-thin insulating film may be used as a primer in a SAP or mSAP process (or a primer SAP process).

[0029] According to an exemplary embodiment, the present invention may be based on the concept that when an electrically conductive layer structure having a fine line pattern is formed directly on an ultra-thin insulating film, which in turn is based on a reinforced resin layer and an inorganic carrier structure, a component carrier having a fine line pattern (of metal traces) and high stiffness / stability may be provided in an effective and reliable manner.

[0030] Although traditionally, fine-line space traces are formed directly on ABF materials (see Figure 3 and Figure 4 ), but the inventors have found that a particularly stable and (cost) efficient architecture can be achieved by forming a fine line pattern on a (glass fiber) reinforced resin layer (supported by an inorganic carrier) with an ultra-thin insulating film located directly between the reinforced resin layer and the fine line pattern.

[0031] The ultra-thin insulating film can provide exceptionally high adhesion for fine-line pattern structures at a low cost. The inorganic carrier structure and the reinforced resin layer structure can form a stable, highly rigid, and low-cost support structure, especially with electrical connection pads / traces on top. The reinforced resin layer structure can be provided as a thin layer with high stiffness and heat resistance.

[0032] The described architecture further enables high design flexibility, since properties such as CTE can be modified in a straightforward manner. In addition, the corresponding manufacturing method can be directly implemented into existing component carrier production lines.

[0033] Exemplary embodiments

[0034] In one embodiment, the inorganic carrier structure comprises at least one of the following: glass, ceramic, semiconductor material. This may provide the advantage that a stable and flexibly adaptable layer structure is provided, in particular the layer structure serves as a robust support.

[0035] In the context of this application, the term "glass structure" may particularly refer to a body that is configured for insertion and comprises glass as a primary component. For example, the glass structure may be a block or a plate. The primary material component of the glass structure (in particular, the material component that provides the highest weight percentage of the glass structure) is glass, such as silica-based glass, in particular soda-lime glass, and / or borosilicate glass and / or aluminosilicate glass and / or lithium silicate glass and / or alkali-free glass. For example, at least 90% by weight of the glass structure may be glass. For example, the glass structure may consist solely of glass, with the exception of a patterned metal layer on the glass structure. However, the glass structure may also contain one or more additional materials. For example, additional electrically conductive structures (e.g., comprising metals and / or metal alloys, such as copper and / or tin and / or bronze and / or conductive pastes) (e.g., wiring traces and / or vertical through-connections) may be integrated into the main glass body of the glass structure and / or may be formed on the surface of the main glass body.

[0036] In addition, the glass structure may also be provided with a specific structure inside to provide heat dissipation and power supply functions. However, the glass structure may also include ceramic materials, such as aluminum nitride and / or aluminum oxide and / or silicon nitride and / or boron nitride and / or tungsten-containing ceramic materials. Additionally and / or alternatively, the glass structure may include semiconductor materials, such as silicon and / or germanium and / or silicon oxide and / or germanium oxide and / or silicon carbide and / or gallium nitride. However, it is further possible that the glass structure may include inorganic materials not listed in the above examples, such as: MoS2, CuGaO2, AgAlO2, LiGaTe2, AgInSe2, CuFeS2, BeO.

[0037] In an embodiment, the resin of the electrically insulating layer structure comprises an epoxy resin. This can provide the advantage of being able to directly apply a mature and economically important material. The epoxy resin (with the reinforcement structure) can be present / provided in an uncured state (prepreg) or in a (fully) cured state.

[0038] In an embodiment, the reinforcement structure of the electrically insulating layer structure comprises reinforcement fibers, in particular glass fibers, more in particular glass fabric.Thereby, high stability and stiffness can be achieved in a cost-effective and reliable manner.

[0039] In one embodiment, the thickness of the ultra-thin insulating film is in the range of 2 μm to 15 μm, particularly 2 μm to 10 μm, and more particularly about 4 μm. This can provide the following advantages: an extremely thin (ultra-thin) layer (film / foil) can be provided, which can effectively serve as a primer (seed layer) for a fine-line patterned electrically conductive layer structure.

[0040] In an embodiment, the ultra-thin insulating film has a first surface roughness that is higher than (or equal to or lower than) the second surface roughness of the electrically insulating layer structure and / or higher than (or equal to or lower than) the third surface roughness of the electrically conductive fine line pattern, and / or higher than (or equal to or lower than) the fourth surface roughness of the further electrically insulating layer structure. A larger surface roughness can improve the adhesion of the electrically conductive material, thereby ultimately achieving a smaller fine line pattern.

[0041] In a specific example, the first surface roughness may be in the range of 0.2 to 0.5 μm (Ra) and 1.0 to 2.5 μm (Rz). The second surface roughness / fourth surface roughness may be, for example, in the range of 0.2 to 0.3 μm (Ra) and 2 to 3 μm (Rz). The difference may be the Rsar ratio (relative surface area increase ratio). In the present case, a larger Rsar may be advantageous. In an example, the ultra-thin insulating film Rsar may be 100% to 300%, while the (additional) electrically insulating layer structure Rsar may be less than 50%.

[0042] In one embodiment, the ultra-thin insulating film is formed in contact with, and in particular, directly on, the electrically insulating layer structure. This can provide the following advantages: the ultra-thin layer film acts as an intermediate layer between the electrically insulating layer structure (prepreg) and the electrically conductive layer structure (metal traces), thereby providing improved adhesion of the electrically conductive material; however, the ultra-thin layer film is thin enough not to cause additional effects.

[0043] In one embodiment, the fine line pattern of the electrically conductive layer structure comprises at least one (metal / copper) trace (in particular a plurality of traces), the width of at least one trace being in the range of 3 μm to 15 μm, in particular 3 μm to 10 μm. This can provide the following advantages: providing very small fine line patterns. In an example, the trace width and the spacing between the traces can both be in the range of 3 μm to 15 μm. Thus, very fine line spacings, such as 10 / 10 μm L / S or 8 / 8 μm L / S (or lower), can be provided. For line spacings below 8 / 8, additional Ti / Cu sputtering techniques can be used.

[0044] In one embodiment, the thickness of the fine line pattern of the electrically conductive layer structure is in the range of 3 μm to 15 μm. This may also provide the advantage of providing a very small fine line pattern.

[0045] In an embodiment, the (further) electrically insulating layer structure is formed directly on the inorganic carrier structure. Thus, a compact and stable build-up structure can be provided, for example by lamination.

[0046] In one embodiment, the component carrier further comprises: a (surface mounted) electronic component (e.g., a semiconductor element, such as an IC), which is electrically connected to the fine line pattern of the electrically insulating layer structure via an electrically conductive connection structure, in particular a solder structure. Thus, the electronic component can be electrically connected to the component carrier stack in an efficient and reliable manner. The electrically conductive connection structure can connect the pads / traces / terminals of the electronic component to the pads / traces / terminals of the component carrier stack, in particular to a portion of the electrically conductive layer structure (at or adjacent to the fine line pattern). In an example, the electrically conductive connection structure can be (at least partially) embedded in a dielectric material (e.g., a solder mask structure).

[0047] In an embodiment, the component carrier further comprises a dielectric layer, in particular a solder mask structure, which is arranged on (and embedded / encapsulated in) the fine-line pattern structure of the electrically conductive layer structure. In one embodiment, the solder mask structure has a thickness in the range of 5 μm to 20 μm. This can provide the following advantages: the solder mask structure can effectively protect the fine-line pattern structure while still achieving a stable electrical connection.

[0048] In one embodiment, the component carrier further comprises: an additional electrically insulating layer structure, the additional electrically insulating layer structure comprising an additional resin and an additional reinforcement structure on the inorganic carrier structure. In an embodiment, the component carrier further comprises: an additional ultrathin insulating film located on the additional electrically insulating layer structure. In an embodiment, the component carrier further comprises: an additional electrically conductive layer structure located (directly) on the additional ultrathin insulating film. In an embodiment, the additional electrically insulating layer structure and the additional ultrathin insulating film are arranged between the inorganic carrier structure and the electrically insulating layer structure. The above-mentioned advantages of the ultrathin insulating layer (on the electrically insulating layer structure) can be applied in the same way within the component carrier stack. Thus, an additional electrically conductive layer structure (in particular with a fine line pattern) can be provided on the ultrathin insulating film in an effective and reliable manner (and with good adhesion), which additional electrically conductive layer structure is embedded in the component carrier stack.

[0049] The additional electrically conductive layer structure can be closer to the glass core, so that the additional electrically conductive layer structure can share the benefits brought by the glass core, namely glass stiffness and low thermal expansion coefficient ratio. This can provide advantages of the glass core (and the additional insulating layer structure) over the organic base substrate.

[0050] In one embodiment, the component carrier further comprises an electrically conductive vertical through-connector extending through at least one of the inorganic carrier structure, the electrically insulating layer structure, and the ultra-thin insulating film. This allows for efficient and reliable electrical (inter)connection. This also provides direct electrical connection between the stacked components on both sides of the inorganic component structure. This shortens the signal transmission path between the two stacked components and increases the density of the conductive structure, thereby achieving higher performance for the component carrier.

[0051] In one example, the electrically conductive vertical through-connection can be configured as a through-via extending through two or more layers. In another example, the electrically conductive vertical through-connection can be implemented by at least one pad and at least one via. For example, the corresponding blind via can extend through the inorganic carrier structure and / or the electrically insulating layer structure. At the junction of the layers, a pad / trace can be formed (e.g., through the corresponding electrically conductive layer structure) to interconnect the vias.

[0052] In one embodiment, the component carrier further includes a mixed zone located at the junction between the electrically insulating layer structure and the ultra-thin insulating film. The mixed zone comprises a mixture of the material of the electrically insulating layer structure and the material of the ultra-thin insulating film. The two materials may interpenetrate, resulting in a merging surface between the two layers, with portions of one material or filler material protruding into the other. This structural feature may reflect the manufacturing step of forming the ultra-thin insulating film on the electrically insulating layer structure, for example, through a lamination process. Furthermore, the mixed zone can improve adhesion between the electrically insulating layer structure and the ultra-thin insulating film.

[0053] In one embodiment, the component carrier further comprises a base structure located below the inorganic carrier structure. Thus, a stable and robust component carrier can be provided. The base structure can be, for example, a carrier structure (eg a core structure) or another stacked component.

[0054] In one embodiment, the ultrathin insulating film includes at least one of the following materials: a polymer (e.g., a (rigid) thermosetting resin, a reactive (low-polarity) polymer) and a filler (e.g., an organic or inorganic filler). Depending on the desired application, the composition of the ultrathin insulating film can be adjusted. This adjustment can improve electrical and / or mechanical properties.

[0055] In one example, the ultrathin insulating film includes a rigid thermosetting resin having at least one of the following properties: low Df, high Tg, low CTE, high elastic modulus, high heat resistance, and high flame retardancy. In another example, the ultrathin insulating film includes a reactive polymer having at least one of the following properties: high adhesion, low Dk, low Df, high Tg, low water absorption, high toughness, and low polarity. In another example, the ultrathin insulating film includes a filler having at least one of the following properties: low CTE, low Df, high heat resistance, and low water absorption.

[0056] In one embodiment, the method further comprises: applying an electrically conductive material on the ultra-thin insulating film by at least one of chemical deposition, plating, sputtering, and laminating a metal foil to form an electrically conductive layer structure having a fine line pattern structure. The fine line pattern structure of the electrically conductive layer structure can be formed in a cost-effective manner using established and reliable techniques of component carrier manufacturing processes (see, for example, Figures 5A to 5H ).

[0057] In an embodiment, the method further comprises applying the ultrathin insulating film in an at least partially uncured state. This allows for a uniform distribution of the film and potentially facilitates manufacturing. The film may be cured at a subsequent stage, either before or after providing the electrically conductive material on the ultrathin insulating film to form the electrically conductive layer structure having the fine line pattern structure. In some examples, the ultrathin insulating film may be provided with a high surface roughness in the uncured state, for example, by providing the ultrathin insulating film with a corresponding metal layer having a high surface roughness.

[0058] In one embodiment, the CTE of the ultra-thin insulating film may be approximately 18 ppm / °C. For the entire structure, for example, using glass fabric prepreg as the electrical insulating layer structure, the CTE(Z) may be in the range of 8 to 45 ppm / °C, and the CTE(X / Y) may be in the range of 3 to 17 ppm / °C.

[0059] In one embodiment, the component carrier is formed as a plate. This facilitates a compact design, while still providing a large base for mounting components. Furthermore, bare chips, particularly as an example of embedded electronic components, can be routinely embedded on thin boards such as printed circuit boards due to their small thickness.

[0060] In an embodiment, the component carrier is configured as one of: a printed circuit board, a substrate (particularly an IC substrate), and an interposer.

[0061] In the context of the present application, the term "printed circuit board" (PCB) may particularly denote a plate-like component carrier formed by laminating a plurality of electrically conductive layer structures with a plurality of electrically insulating layer structures, for example by applying pressure and / or by supplying heat. As a preferred material for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may comprise resin and / or glass fiber, so-called prepreg or FR4 materials. The various electrically conductive layer structures can be connected to one another in a desired manner by forming through-holes through the laminate, for example by laser drilling or mechanical drilling, and by partially or completely filling these through-holes with conductive material, in particular copper, to form vias or any other through-hole connections. A filled hole connecting the entire stack (a through-hole connection extending through multiple layers or the entire stack) or a filled hole connecting at least two electrically conductive layers is referred to as a via. Similarly, optical interconnections can be formed through the various layers of the stack to accommodate an electro-optical circuit board (EOCB). In addition to one or more components that can be embedded in the printed circuit board, the printed circuit board is generally configured to accommodate one or more components on one or both opposing surfaces of the plate-shaped printed circuit board. The components can be connected to the corresponding main surfaces by soldering. The dielectric portion of the PCB can be composed of a resin with reinforcing fibers (such as glass fiber).

[0062] In the context of the present application, the term "substrate" can particularly refer to a small component carrier. A substrate can be a relatively small component carrier relative to a PCB, one or more components can be mounted on the component carrier, and the substrate can serve as a connection medium between one or more chips and another PCB. For example, the substrate can have a size substantially the same as the components (particularly electronic components) to be mounted on the substrate (for example, in the case of a chip scale package (CSP)). More specifically, a substrate can be understood as a carrier for electrical connection or an electrical network and a component carrier comparable to a printed circuit board (PCB), but the connectors arranged laterally and / or vertically have a relatively high density. Lateral connectors are, for example, conductive paths, and vertical connectors can be, for example, drill holes. These lateral and / or vertical connectors are arranged in the substrate and can be used to provide electrical, thermal and / or mechanical connections between accommodated components or unaccommodated components (such as bare chips), particularly IC chips and printed circuit boards or intermediate printed circuit boards. Therefore, the term "substrate" also includes "IC substrates". The dielectric portion of the substrate may consist of a resin with reinforcing particles, such as reinforcing spheres, particularly glass spheres.

[0063] In the context of this application, the term "inorganic layer structure" may particularly refer to a layer structure comprising an inorganic material, such as an inorganic compound. In particular, the dielectric material of the inorganic layer structure or even the entire inorganic layer structure may be made exclusively or at least substantially exclusively of an inorganic material. In another embodiment, the inorganic layer structure may comprise an inorganic dielectric material and another additional dielectric material. The inorganic compound may be a compound lacking carbon-hydrogen bonds or a compound that is not an organic compound. In one example, the inorganic layer structure may comprise glass, such as silicon-based glass, particularly soda-lime glass, and / or borosilicate glass and / or aluminosilicate glass and / or lithium silicate glass and / or alkali-free glass. In another example, the inorganic layer structure may comprise a ceramic material, such as aluminum nitride and / or aluminum oxide and / or silicon nitride and / or boron nitride and / or a tungsten-containing ceramic material. However, in another example, the inorganic layer structure may comprise a semiconductor material, such as silicon and / or germanium and / or silicon oxide and / or germanium oxide and / or silicon carbide and / or gallium nitride. In another embodiment, the inorganic layer structure may comprise (elemental) metals and / or metal alloys, such as copper and / or tin and / or bronze. In yet another embodiment, the inorganic layer structure may comprise inorganic materials not listed in the above examples, such as MoS2, CuGaO2, AgAlO2, LiGaTe2, AgInSe2, CuFeS2, BeO.

[0064] The substrate or interposer may include or consist of at least one layer of glass, silicon (Si), or a photoimageable or dry-etchable organic material such as an epoxy-based laminate material (such as an epoxy-based laminate film) or a polymer compound (which may or may not include photosensitive and / or heat-sensitive molecules) such as polyimide or polybenzoxazole.

[0065] In an embodiment, at least one electrically insulating layer structure (and / or a curable dielectric element) comprises at least one of the following: a resin or polymer (such as an epoxy resin, a cyanate resin, a benzocyclobutene resin, a bismaleimide triazine resin), a polyphenylene derivative (e.g. based on polyphenylene ether, PPE), a polyimide (PI), a polyamide (PA), a liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), polyvinylidene fluoride (PVDF) and / or a combination thereof. Reinforcement structures such as meshes, fibers, spheres or other types of filler particles made of glass (multilayer glass) may also be used to form a composite material. Semi-cured resins combined with reinforcing agents, such as fibers impregnated with the above resins, are called prepregs. These prepregs are usually named after properties that describe their flame retardant properties, such as FR4 or FR5. Although prepregs, especially FR4, are generally preferred for rigid PCBs, other materials may also be used, in particular epoxy-based laminates (such as laminate films) or photoimageable dielectric materials. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate resins may be preferred. In addition to these polymers, low-temperature co-fired ceramics (LTCC) or other low-DK materials, very-low-DK materials, or ultra-low-DK materials may be used as the electrically insulating layer structure in the component carrier.

[0066] In an embodiment, the at least one electrically conductive layer structure comprises at least one of the following: copper, aluminum, nickel, silver, gold, palladium, tungsten, carbon, platinum, (doped) silicon, and magnesium. Although copper is generally preferred, other materials or coated versions thereof are also possible, in particular coated with a superconducting material or a conductive polymer, such as graphene or poly (3,4-ethylenedioxythiophene) (PEDOT), respectively.

[0067] At least one component can be embedded in the component carrier and / or can be surface-mounted on the component carrier. Such a component can be selected from the following: a non-conductive inlay, a conductive inlay (such as a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (such as a heat pipe), an optical element (such as an optical waveguide or optical conductor connector), an electronic component, or a combination thereof. The inlay can be, for example, a metal block with or without a coating of insulating material (IMS inlay), which can be embedded or surface-mounted to promote heat dissipation. Suitable materials are defined by their thermal conductivity, which should be at least 2 W / mK. Such materials are typically based on, but not limited to, metals, metal oxides, and / or ceramics, such as copper, aluminum oxide (Al2O3), or aluminum nitride (AlN). Other geometries with increased surface area are also often used to increase the heat exchange capacity. Furthermore, the component may be an active electronic component (having at least one pn junction implemented), a passive electronic component (such as a resistor, an inductor, or a capacitor), an electronic chip, a memory device (e.g., a DRAM or other data memory), a filter, an integrated circuit (such as a field programmable gate array (FPGA), a programmable array logic (PAL), a general array logic (GAL), and a complex programmable logic device (CPLD)), a signal processing component, a power management component (such as a field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), a junction field effect transistor (JFET), or a combination thereof). or insulated-gate field effect transistors (IGFETs), all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs) and / or any other suitable inorganic compound), optoelectronic interface elements, light-emitting diodes, optocouplers, voltage converters (e.g., DC / DC converters or AC / DC converters), cryptographic components, transmitters and / or receivers, electromechanical transducers, sensors, actuators, microelectromechanical systems (MEMS), microprocessors, capacitors, resistors, inductors, batteries, switches, cameras, antennas, logic chips, and energy harvesting units. However, other components may be embedded on the component carrier. For example, a magnetic element may be used as a component. Such a magnetic element may be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferromagnetic element, or a ferrimagnetic element, such as a ferrite core) or may be a paramagnetic element. However, the component may also be an IC substrate, an interposer, or another component carrier, such as a component carrier in a board-in-board configuration. The component can be surface-mounted on the component carrier and / or can be embedded in the interior of the component carrier.In addition, other components, in particular those that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment, can also be used as components.

[0068] In an embodiment, the component carrier structure is a laminated component carrier. In such an embodiment, the component carrier is a composite of multilayer structures stacked and connected together by applying a compressive force and / or heat.

[0069] After processing the internal layer structure of the component carrier, one or both opposing main surfaces of the processed layer structure can be covered symmetrically or asymmetrically (in particular by lamination) with one or more further electrically insulating and / or electrically conductive layer structures. In other words, the stacking can be continued until the desired number of layers is obtained.

[0070] After the formation of the stack with an electrically insulating layer structure and an electrically conductive layer structure is completed, the obtained layer structure or component carrier can be subjected to surface treatment. In particular, with regard to surface treatment, an electrically insulating solder resist can be applied to one or two opposite main surfaces of the layer stack or component carrier. For example, such a solder resist can be formed on the entire main surface, and the solder resist layer can be subsequently patterned to expose one or more conductive surface portions that will be used to electrically couple the component carrier to the electronic peripheral. The surface portions of the component carrier that are still covered with the solder resist can be effectively protected from oxidation or corrosion, and in particular the surface portions that contain copper are effectively protected from oxidation or corrosion.

[0071] In terms of surface treatment, the exposed electrically conductive surface portions of the component carrier can also be selectively treated. Such surface treatment can be an electrically conductive covering material on exposed electrically conductive layer structures (such as pads, conductive traces, etc., particularly comprising or consisting of copper) on the surface of the component carrier. If such exposed electrically conductive layer structures are not protected, the exposed electrically conductive component carrier material (particularly copper) may oxidize, making the component carrier less reliable.

[0072] A surface finish can then be formed, for example, as a joint between a surface-mounted component and a component carrier. The surface finish has the function of protecting the exposed electrically conductive layer structure (particularly the copper circuitry) and enabling the joining process (e.g., by soldering) to one or more components. Examples of suitable materials for the surface finish include organic solderability preservatives (OSP), electroless nickel immersion gold (ENIG), electroless nickel palladium immersion gold (ENIPIG), gold (particularly hard gold), chemical tin, nickel-gold, nickel-palladium, and the like. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] The aspects defined above and further aspects of the invention are apparent from the examples of embodiment described hereinafter and are explained with reference to these examples of embodiment.

[0074] Figure 1A cross section through a component carrier according to an exemplary embodiment of the invention is shown.

[0075] Figure 2 A cross section through a component carrier with a further electrically insulating layer structure according to an exemplary embodiment of the invention is shown.

[0076] Figure 3 and Figure 4 A cross section of a conventional circuit board is shown.

[0077] Figures 5A to 5H A method for producing a component carrier according to an exemplary embodiment of the present invention is respectively shown. DETAILED DESCRIPTION

[0078] Figure 1 A cross-section of a component carrier 100 according to an exemplary embodiment of the present invention is shown. The component carrier 100 comprises a laminate having an inorganic carrier structure 110 at its base (in this example, any base structure below the inorganic carrier structure 110 is not shown). The inorganic carrier structure, in this example, is constructed as a glass core layer. Directly on top of the inorganic carrier structure 110, an electrically insulating layer structure 120 is arranged. The electrically insulating layer structure comprises a resin matrix 121 with an embedded reinforcement structure 122, preferably glass fiber. Directly on top of the reinforced electrically insulating layer structure 120, an ultrathin insulating film 130 is also formed. The ultrathin insulating film is, for example, a mixture of a thermosetting resin, a reactive (low-polarity) polymer, and an inorganic filler. Furthermore, an electrically conductive layer structure 140 having a fine line pattern is formed directly on the ultrathin insulating film 130.

[0079] The thickness of the ultra-thin insulating film 130 is in the range of 2 μm to 15 μm (here, 4 μm), and the first surface roughness of the ultra-thin insulating film is higher than the second surface roughness of the electrical insulating layer structure 120 .

[0080] The fine line pattern of the electrically conductive layer structure 140 includes traces having a width in the range of 3 μm to 15 μm. Furthermore, the fine line pattern of the electrically conductive layer structure 140 has a thickness in the range of 3 μm to 15 μm.

[0081] The component carrier 100 (stack) further comprises a solder resist structure 150 which is arranged (directly) on the fine line pattern of the electrically conductive layer structure 140, such that the fine line pattern is embedded (encapsulated) in the material of the solder resist structure 150. The thickness of the solder resist structure 150 is in the range of 5 μm to 20 μm.

[0082] Furthermore, an electronic component 160 (e.g., a semiconductor element such as an IC chip) is surface mounted to the component carrier 100 and electrically coupled to the fine line pattern and / or electrically conductive layer structure connections 142 (e.g., pads) of the electrically conductive layer structure 140 via an electrically conductive connection structure, which is here a solder ball structure 165.

[0083] The component carrier 100 further comprises electrically conductive vertical through-connections 111 extending through the inorganic carrier structure 110 , the electrically insulating layer structure 120 and the ultra-thin insulating film 130 to electrically connect to the traces of the fine line pattern of the electrically conductive layer structure 140 .

[0084] In the example shown, the electrically conductive vertical through-connections 111 are realized by: i) through-vias 111 extending through the inorganic carrier structure 110 , ii) electrically conductive pads 170 directly on top of the inorganic carrier structure 110 , which are embedded in the material of the electrically insulating layer structure 120 , and iii) blind vias 171 extending through the electrically insulating layer structure 120 and the ultra-thin insulating film 130 and directly connected to the fine line pattern of the electrically conductive layer structure 140 .

[0085] A mixed region (not shown) may be formed at a junction between the electrical insulating layer structure 120 and the ultra-thin insulating film 130 , wherein the mixed region includes a mixture of a material of the electrical insulating layer structure and a material of the ultra-thin insulating film.

[0086] Figure 2 A cross-section of a component carrier 100 according to an exemplary embodiment of the present invention is shown, comprising an additional electrically insulating layer structure 180 (including an additional resin and an additional reinforcement structure) and an additional ultrathin insulating film 185 located on the additional electrically insulating layer structure 180. The additional electrically insulating layer structure 180 and the additional ultrathin insulating film 185 are arranged between the inorganic carrier structure 110 and the electrically insulating layer structure 120. In this manner, the electrically conductive pad 170 described above is not arranged directly on the inorganic carrier structure, but is formed as an additional electrically conductive layer structure 186 directly on the additional ultrathin insulating film 185. At the junction between the electrically insulating layer structure 120 and the ultrathin insulating film 130 and / or the additional ultrathin insulating film 185, a mixed region can be present, comprising the material of the electrically insulating layer structure 120 and the material of the ultrathin insulating film 130 and / or the additional ultrathin insulating film 185. The two materials may interpenetrate, so there may be a merging surface between the two layers, and one material may protrude into the other.

[0087] The through-vias 111 passing through the inorganic carrier structure 110 further protrude from the surface of the inorganic carrier structure 110 and then pass through the further electrically insulating layer structure 180 and the further ultra-thin insulating film 185. This structure can improve adhesion, especially when the further electrically insulating layer structure 180 is directly located on the inorganic carrier structure 110, and can also realize a fine line pattern of the further electrically conductive layer structure 186 on the further ultra-thin insulating film 185.

[0088] Figures 5A to 5H A method for manufacturing a component carrier 100 using a pSAP process according to an exemplary embodiment of the present invention is respectively shown.

[0089] Figure 5A An electrically insulating core layer 125 having a patterned metal structure 126 is provided. The core layer 125 may be an inorganic support structure 110 or may be formed on such an inorganic support structure 110.

[0090] Figure 5B An electrically insulating layer structure 120 (a reinforced electrically insulating layer structure) is formed by lamination on a core layer 125 (e.g., as a prepreg). An ultra-thin insulating film 130 (with a thin metal layer on top) is then formed / laminated on the electrically insulating layer structure 120. Holes 127 are drilled through the electrically insulating layer structure 120 and the ultra-thin insulating film 130, down to the patterned metal structure 126.

[0091] Figure 5C : The thin metal (copper) layer on top of the ultra-thin insulating film 130 is removed by etching.

[0092] Figure 5D : The ultra-thin insulating film 130 serves as a primer for forming the electroless plating layer 145 (copper). Thus, the sidewalls of the hole 127 are also plated.

[0093] Figure 5E : A dielectric pattern film (negative mask) 146 is disposed on the plating layer 145 .

[0094] Figure 5F : The space between the dielectric pattern film 146 and the hole 127 is completely filled with metal (copper) by plating, thereby forming the electrically conductive layer structure 140 having a fine line pattern structure.

[0095] Figure 5G : The dielectric pattern film 146 is removed (peeled off).

[0096] Figure 5H Using a rapid etch, the copper residues between the traces of the electrically conductive layer structure 140 are removed to expose the underlying ultra-thin insulating film 130. In a further step (not shown), a solder resist layer structure 150 may be provided.

[0097] Reference numerals

[0098] 100-component carrier

[0099] 110 Inorganic carrier structure

[0100] 111 Electrically conductive vertical through-connection portion

[0101] 120 electrical insulation layer structure

[0102] 121 resin

[0103] 122 reinforced fiber

[0104] 125 core layer

[0105] 126 Patterned Metal Structure

[0106] 130 ultra-thin insulating film

[0107] 140 Electrically conductive layer structure with fine line pattern

[0108] 142 Electrically conductive layer structural connector

[0109] 145 coating

[0110] 146 Patterned dielectric film

[0111] 150 solder mask structure

[0112] 160 Electronic components, ICs

[0113] 161 Electronic components and electrical connectors

[0114] 165 solder structure / ball-shaped parts

[0115] 170 Additional electrical conductive layer structure

[0116] 171 Another electrically conductive vertical through-connection portion

[0117] 180 Additional electrical insulation layer structure

[0118] 185 Additional ultra-thin insulating film

[0119] 186 Additional electronically conductive layer structures.

Claims

1. A component carrier (100), wherein: The component carrier (100) comprises: Inorganic carrier structure (110); An electrical insulating layer structure (120), the electrical insulating layer structure (120) comprising a resin (121) and a reinforcing structure (122) located on the inorganic carrier structure (110); an ultra-thin insulating film (130) located on the electrical insulating layer structure (120); and An electrically conductive layer structure (140) having a fine line pattern is directly located on the ultra-thin insulating film (130).

2. The component carrier (100) according to claim 1, in, The inorganic support structure (110) includes at least one of the following: Glass, ceramics, Semiconductor materials.

3. The component carrier (100) according to claim 1 or 2, in, The resin (121) of the electrical insulation layer structure (120) comprises epoxy resin.

4. The component carrier (100) according to one of the preceding claims, in, The reinforcement structure (122) of the electrically insulating layer structure (120) comprises reinforcement fibers, in particular, the reinforcement structure of the electrically insulating layer structure comprises glass fibers, more in particular, the reinforcement structure of the electrically insulating layer structure comprises glass fabric.

5. The component carrier (100) according to one of the preceding claims, in, The ultrathin insulating film (130) has a thickness in the range of 2 μm to 15 μm.

6. Component carrier (100) according to one of the preceding claims, in, The ultra-thin insulating film (130) has a first surface roughness, which is higher than a second surface roughness of the electrical insulating layer structure (120), and / or higher than a third surface roughness of the fine line pattern of the electrical conductive layer structure (140).

7. Component carrier (100) according to one of the preceding claims, in, The ultra-thin insulating film (130) is formed to be in contact with the electrical insulating layer structure (120); in particular, the ultra-thin insulating film (130) is directly formed on the electrical insulating layer structure (120).

8. Component carrier (100) according to one of the preceding claims, in, The fine line pattern of the electrically conductive layer structure (140) comprises at least one trace having a width in the range of 3 μm to 15 μm.

9. Component carrier according to one of the preceding claims, in, The fine line pattern of the electrically conductive layer structure (140) has a thickness in the range of 3 μm to 15 μm.

10. Component carrier (100) according to one of the preceding claims, in, The electrically insulating layer structure (120) is formed directly on the inorganic carrier structure (110).

11. The component carrier (100) according to one of the preceding claims, further comprising: A surface mounted electronic component (160) is electrically connected to the fine line pattern of the electrically conductive layer structure (140) via an electrically conductive connection structure, in particular, the surface mounted electronic component (160) is electrically connected to the fine line pattern of the electrically conductive layer structure (140) via a solder structure (165).

12. The component carrier (100) according to one of the preceding claims, further comprising: a solder resist layer structure (150), the solder resist layer structure (150) being arranged on the fine line pattern of the electrically conductive layer structure (140), In particular, the solder resist structure (150) has a thickness in the range of 5 μm to 20 μm.

13. The component carrier (100) according to one of the preceding claims, further comprising: a further electrically insulating layer structure (180), the further electrically insulating layer structure (180) comprising a further resin and a further reinforcement structure; A further ultrathin insulating film (185) is located on the further electrically insulating layer structure (180), in particular, wherein the further electrically insulating layer structure (180) and the further ultrathin insulating film (185) are arranged between the inorganic carrier structure (110) and the electrically insulating layer structure (120).

14. The component carrier (100) according to one of the preceding claims, further comprising: An electrically conductive vertical through-connection portion (111), the electrically conductive vertical through-connection portion (111) extending through at least one of the inorganic carrier structure (110), the electrical insulating layer structure (120), and the ultra-thin insulating film (130).

15. The component carrier (100) according to one of the preceding claims, further comprising: A mixed region is located at the junction between the electrical insulating layer structure (120) and the ultra-thin insulating film (130), wherein the mixed region comprises a mixture of the material of the electrical insulating layer structure (120) and the material of the ultra-thin insulating film (130).

16. The component carrier (100) according to one of the preceding claims, further comprising: A base structure is located below the inorganic carrier structure (110).

17. Component carrier (100) according to one of the preceding claims, wherein The ultra-thin insulating film (130) comprises at least one of the following materials: a polymer, a filler, and in particular, the polymer is a resin.

18. A method of manufacturing a component carrier (100), wherein: The method comprises: Providing an inorganic carrier structure (110); applying an electrically insulating layer structure (120) on the inorganic carrier structure (110), the electrically insulating layer structure (120) comprising a resin (121) and a reinforcement structure (122); applying an ultra-thin insulating film (130) on the electrical insulating layer structure (120); and An electrical conductive layer structure (140) having a fine line pattern is formed directly on the ultra-thin insulating film (130).

19. The method according to claim 18, further comprising: An electrically conductive material is applied on the ultra-thin insulating film (130) by at least one of chemical deposition, plating, sputtering, and lamination of metal foil to form the electrically conductive layer structure (140) having the fine line pattern.

20. The method according to claim 18 or 19, further comprising: The ultra-thin insulating film (130) is applied in an at least partially uncured state.

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