Circuit test point generation method and system

Abstract

The invention provides a circuit test point generation method and system. The method comprises the following steps: obtaining layout information and setting rules of a circuit; a circuit diagram is generated according to the layout information. Obtaining a plurality of center lines of a plurality of traces of the circuit diagram; a plurality of test points are provided on each of the center lines. Judging whether the test points of each center line conform to a setting rule or not, and removing one part of the test points which do not conform to the setting rule and reserving the other part of the test points which conform to the setting rule; arranging and combining the other part of the test points of each of the center lines according to a setting rule to generate a plurality of candidate circuit test point diagrams, and calculating the test point coverage rate of each of the candidate circuit test point diagrams; and determining the candidate circuit measuring point diagrams with the highest measuring point coverage rate as a target circuit measuring point diagram. Therefore, the setting coverage rate of the test points is improved.

Description

Technical Field

[0001] The present invention relates to a test point generation method and a system thereof, and in particular to a circuit test point generation method and a system thereof. Background Art

[0002] When testing a printed circuit board (PCB), test points are set up on the board and probes are placed on the test points to confirm the continuity of components on the board. Ideally, test points should be set up on all component pins on the board to ensure that all components are tested. However, the test point setting must comply with the spacing specifications between traces and components to ensure that the probe can accurately test when the test points are actually placed on the board.

[0003] Existing test point configuration tools only provide a test point generation function, which sets test points at component pins on a circuit board. To ensure that test point configuration complies with trace and component spacing specifications, these tools cannot set test points at all component pins. Consequently, their test point coverage is low, meaning that only a limited number of components can have test points assigned to them at any one time.

[0004] In view of this, developing a circuit test point generation method and system that can generate a variety of test point setting combinations and set the test points on the circuit traces has become a worthy research and development goal for related industries. Summary of the Invention

[0005] Therefore, the object of the present invention is to provide a circuit test point generation method and system thereof, which uses a processor to set multiple test points on the center line of the routing, generate multiple test point setting methods, and find a target circuit test point diagram with the optimal test point setting method based on the test point coverage of the multiple test point setting methods.

[0006] According to one embodiment of the method of the present invention, a circuit test point generation method is provided, comprising: obtaining, by a processor, layout information and a configuration rule for a circuit from a database, wherein the layout information includes routing information. Generating, by the processor, a circuit diagram of the circuit based on the layout information. Obtaining, by the processor, multiple center lines of multiple routings in the circuit diagram based on the routing information. Setting, by the processor, multiple test points on each of these center lines. Determining, by the processor, whether these test points on each of these center lines comply with the configuration rule, and removing a portion of these test points that do not comply with the configuration rule while retaining another portion of these test points that comply with the configuration rule. The configuration rule includes a test point spacing limit. Arranging, by the processor, another portion of these test points on each of these center lines according to the configuration rule to generate multiple candidate circuit test point diagrams, and calculating a test point coverage rate for each of these candidate circuit test point diagrams. Determining, by the processor, the one with the highest test point coverage rate among the candidate circuit test point diagrams as a target circuit test point diagram.

[0007] Therefore, the circuit test point generation method of the present invention can generate a target circuit test point diagram with extremely high test point coverage.

[0008] According to one embodiment of the present invention, a circuit test point generation system is provided, comprising a database and a processor. The database is used to store layout information and a configuration rule for a circuit. The layout information includes routing information. The processor is signal-connected to the database and retrieves the circuit layout information from the database. The processor is configured to perform operations including the following steps: generating a circuit diagram of the circuit based on the layout information; obtaining multiple centerlines of multiple routing lines in the circuit diagram based on the routing information; setting multiple test points on each of these centerlines; determining whether the test points on each of these centerlines comply with the configuration rule, removing a portion of these test points that do not comply with the configuration rule, and retaining another portion of these test points that comply with the configuration rule. The configuration rule includes a test point spacing constraint. Arranging and combining the other portion of these test points on each of these centerlines based on the configuration rule to generate multiple candidate circuit test point diagrams, and calculating a test point coverage for each of these candidate circuit test point diagrams. Determining the candidate circuit test point diagram with the highest test point coverage as a target circuit test point diagram.

[0009] Therefore, the circuit test point generation system of the present invention is highly flexible and can be applied to circuit boards of different specifications. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a flow chart illustrating a method for generating circuit test points according to a first embodiment of the present invention;

[0011] Figure 2 It is drawn according to Figure 1 A schematic diagram of a partial area of ​​a circuit diagram of a method for generating circuit test points;

[0012] Figure 3 It is drawn according to Figure 1 A schematic diagram of a center line of a trace of a circuit test point generation method;

[0013] Figure 4 It is drawn according to Figure 1 Another schematic diagram of the center line of the routing of the circuit test point generation method;

[0014] Figure 5 It is drawn according to Figure 1 A schematic diagram of a partial area of ​​a target circuit test point diagram of a circuit test point generation method;

[0015] Figure 6 is a flow chart illustrating a circuit test point generating method according to a second embodiment of the present invention; and

[0016] Figure 7 FIG. 4 is a schematic diagram illustrating a circuit test point generating system according to a third embodiment of the present invention.

[0017] The description of the accompanying drawings is as follows:

[0018] 100,100a: Circuit test point generation method

[0019] 110,120,130,140,150,160,170,180: Steps

[0020] 200: Circuit test point generation system

[0021] 210: Database

[0022] 220: Processor

[0023] C1, C2, C3, C4, C5, C6, C7: Center lines

[0024] D1: Layout information

[0025] E1: Component

[0026] F1: Circuit diagram

[0027] F2: Target circuit measurement point diagram

[0028] H: Hole position

[0029] L4: Routing

[0030] P, P0, P1, P2, P3: test points

[0031] R1: Set rules DETAILED DESCRIPTION

[0032] See also Figures 1 to 5 , Figure 1 is a flow chart illustrating a circuit test point generating method 100 according to a first embodiment of the present invention; Figure 2 It is drawn according to Figure 1 A schematic diagram of a partial area of ​​a circuit diagram F1 of a circuit test point generating method 100; Figure 3 It is drawn according to Figure 1 Schematic diagram of a center line C4 of a trace L4 of a circuit test point generating method 100; Figure 4 It is drawn according to Figure 1 Another schematic diagram of the center lines C1, C2, C3, C4, C5, C6, and C7 of the routing of the circuit test point generation method 100; and

[0033] Figure 5 It is drawn according to Figure 1 Schematic diagram of a partial area of ​​a target circuit test point diagram F2 of a circuit test point generation method 100. The circuit test point generation method 100 includes steps 110, 120, 130, 140, 150, 160, and 170. Step 110 is performed by a processor 220 (see Figure 7 ) from a database 210 (see Figure 7 ) obtains a layout information D1 and a setting rule R1 of a circuit (see Figure 7 ). The layout information D1 includes circuit board information, component location information, and routing information. Step 120 generates a circuit diagram F1 of the circuit according to the layout information D1 by the processor 220. Step 130 obtains multiple center lines C1, C2, C3, C4, C5, C6, and C7 of multiple routing lines (not shown) of the circuit diagram F1 according to the routing information by the processor 220. Step 140 sets multiple test points P, P0, P1, P2, and P3 on each of these center lines C1 to C7 by the processor 220. Step 150 determines whether the test points P, P0, P1, P2, and P3 of each of these center lines C1 to C7 meet the setting rule R1 by the processor 220, and removes the test points P and P0 that do not meet the setting rule R1 and retains the test points P1, P2, and P3 that meet the setting rule R1. The setting rule R1 includes a test point spacing limit. In step 160, processor 220 arranges and combines test points P1, P2, and P3 on each of center lines C1-C7 according to configuration rule R1 to generate a plurality of candidate circuit test point diagrams, and calculates a test point coverage for each of these candidate circuit test point diagrams. In step 170, processor 220 determines the one with the highest test point coverage among the candidate circuit test point diagrams as a target circuit test point diagram F2.

[0034] In other words, the layout information D1 may be a layout file of the circuit, the circuit board information may include the geometric shape of the circuit board of the circuit, the component position information may include the type and layout position of the component E1 in the circuit, and the routing information may include the wire diameter, setting position, and connected component E1 of the routing in the circuit, but the present invention is not limited to this.

[0035] exist Figure 2 In step 120 , the layout information D1 is converted into a visual graphic object and displayed in the form of a circuit diagram F1 .

[0036] Step 130 is to find the center line C1-C7 of each line. Step 140 is to set a plurality of test points P, P0, P1, P2, P3 on the center line C1-C7 of each line. For example, the center line C4 of line L4 and the test points P, P0, P1, P2, P3 set thereon can be as follows: Figure 3 shown.

[0037] The measurement point spacing restriction includes a measurement point-to-measurement point spacing restriction, a measurement point-to-adjacent trace spacing restriction, a measurement point-to-adjacent component spacing restriction, and a measurement point-to-circuit board hole spacing restriction, but the present invention is not limited thereto. The measurement point-to-measure point spacing restriction indicates that the distance between two adjacent test points on different center lines C1-C7 is greater than a first preset distance. The measurement point-to-adjacent trace spacing restriction indicates that the distance between one of the test points P, P0, P1, P2, or P3 and one of the adjacent traces is greater than a second preset distance. The measurement point-to-adjacent component spacing restriction indicates that the distance between one of these test points P, P0, P1, P2, or P3 and a component E1 of the circuit is greater than a third preset distance. The measurement point-to-circuit board hole spacing restriction indicates that the distance between one of the test points P, P0, P1, P2, or P3 and a hole H of the circuit is greater than a fourth preset distance. In step 150, the test points P and P0 on the center line C4 of trace L4 are removed according to the setting rule R1. In the first embodiment, the first preset distance, the second preset distance, the third preset distance, and the fourth preset distance can be adjusted according to circuit board rules, but the present invention is not limited thereto.

[0038] Taking test points P, P0, P1, P2, and P3 on centerline C4 of trace L4 as an example, if the distance between test points P and P0 on centerline C4 and at least one of the adjacent traces (corresponding to the traces on centerlines C3 and C5) is too close, this indicates that the current test points P and P0 do not meet the spacing restrictions between the test points and the adjacent traces. If component E1 is located near test point P and the distance between component E1 and test point P is too close, this indicates that the current test point P does not meet the spacing restrictions between the test points and the adjacent components. If a hole H is located near test point P0 and the distance between hole H and test point P0 is too close, this indicates that the current test point P0 does not meet the spacing restrictions between the test points and the circuit board holes.

[0039] After the test points P and P0 that do not comply with the setting rule R1 on the center line C4 of the trace L4 are removed, the test points P1, P2, and P3 that comply with the setting rule R1 on the center line C4 can be Figure 4 Specifically, a plurality of test points (not shown) that comply with the setting rule R1 are also set on the center lines C1-C3 and C5-C7.

[0040] In step 160, the test points P1, P2, and P3 are considered as candidate test points for the center line C4 of the trace L4. When performing permutations and combinations, all candidate test points on the center line C4 are selected, and one of the test points P1 to P3 that does not meet the setting rule R1 is removed. The test point coverage of all candidate circuit test point diagrams is calculated to generate a candidate circuit test point diagram. For example, Table 1 lists 6 candidate circuit test point diagrams (test points) generated by permuting and combining the test points P1 and P2 on the center lines C1 to C3 of the traces and the test points P1, P2, and P3 on the center line C4 of the trace L4. Figures 1 to 6 ), where "1" represents the selected test points P1, P2, and P3; "0" represents the unselected test points P1, P2, and P3; and "1-" represents the test points P1, P2, and P3 that were selected but removed because they did not meet the setting rule R1. In the first candidate circuit test point diagram, the test points in the arrangement and combination include the test point P1 on the center line C1, the test point P1 on the center line C2, the test point P1 on the center line C3, and the test point P1 on the center line C4. Table 2 lists the test point coverage of the six candidate circuit test point diagrams in Table 1. The test point coverage can be calculated as the number of traces with test points P1, P2, and P3 divided by the total number of traces.

[0041] Table 1

[0042]

[0043]

[0044] Table 2

[0045] Candidate circuit test point diagram Total number of traces Number of traces with test points Measurement point coverage Measuring point Figure 1 4 3 75％ Measuring point Figure 2 4 3 75％ Measuring point Figure 3 4 3 75％ Measuring point Figure 4 4 3 75％ Measuring point Figure 5 4 3 75％ Measuring point Figure 6 4 4 100％

[0046] Step 170 is to select the candidate circuit test point diagram with the highest test point coverage as the target circuit test point diagram F2. As can be seen from Table 1 and Table 2, the sixth candidate circuit test point diagram in Table 1 (i.e., test point Figure 6 ) has the highest test point coverage, so the sixth candidate circuit test point diagram is selected as the target circuit test point diagram F2, which can be Figure 5 shown.

[0047] Thus, the circuit test point generation method 100 of the present invention can automatically generate a target circuit test point map F2 with extremely high test point coverage, thereby reducing the lead time for planning the placement of test points P1, P2, and P3 in the test process and the modification time required to manually add test points P1, P2, and P3 due to low test point coverage.

[0048] Please refer to Figures 1 to 6 , Figure 6 1 is a flow chart illustrating a circuit test point generation method 100a according to a second embodiment of the present invention. The circuit test point generation method 100a includes steps 110, 120, 130, 140, 150, 160, 170, and 180. In the second embodiment, steps 110, 120, 130, 140, 150, 160, and 170 are identical to steps 110, 120, 130, 140, 150, 160, and 170 of the circuit test point generation method 100 according to the first embodiment, and are not further described. Specifically, the circuit test point generation method 100a may further include step 180. Step 180 involves the processor 220 setting at least one prohibited test point placement region on the circuit diagram F1 of the circuit. The prohibited test point placement region does not include any of the test points P, P0, P1, P2, and P3; that is, the test points P, P0, P1, P2, and P3 are located outside the prohibited test point placement region.

[0049] In other words, step 180 can be performed at Figure 2 A prohibited test point placement area is set in the circuit diagram F1. After the prohibited test point placement area is set, test points P, P0, P1, P2, and P3 set along each center line C1-C7 in step 140 cannot be placed within the prohibited test point placement area and can only be placed within the circuit board, outside the prohibited test point placement area. Step 180 can be performed after step 130 and before step 140, but the present invention is not limited to this. Thus, the circuit test point generation method 100a of the present invention is highly flexible and applicable to circuit boards of different specifications.

[0050] Please refer to Figures 1 to 7 , Figure 72 is a schematic diagram illustrating a circuit test point generation system 200 according to a third embodiment of the present invention. The circuit test point generation system 200 includes a database 210 and a processor 220. The database 210 is used to store layout information D1 and a setting rule R1 of a circuit. The layout information D1 includes circuit board information, component location information, and routing information. The processor 220 is signal-connected to the database 210 and obtains the circuit layout information D1 from the database 210. The processor 220 is configured to implement the circuit test point generation methods 100 and 100a of the first and second embodiments, generate a circuit diagram F1 based on the layout information D1, and remove test points P and P0 that do not comply with the setting rule R1, thereby generating a target circuit test point diagram F2 with high test point coverage, but the present invention is not limited to this. In this way, the circuit test point generation system 200 of the present invention can set test points P, P1, P2, and P3 on the routing to improve the test point coverage.

[0051] Specifically, the database 210 may be a memory, a register, or other data storage elements, and the processor 220 may be a microprocessor or a central processing unit, but the present invention is not limited thereto.

[0052] Although the present invention has been disclosed in the form of embodiments as described above, it is not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A method for generating circuit test points, characterized in that: Include: Obtaining layout information and a setting rule of a circuit from a database through a processor, wherein the layout information includes routing information; generating, by the processor, a circuit diagram of the circuit according to the layout information; Obtaining, by the processor, a plurality of center lines of a plurality of routings of the circuit diagram according to the routing information; setting, by the processor, a plurality of test points on each of the plurality of center lines; determining, by the processor, whether the plurality of test points of each of the plurality of center lines conform to the setting rule, and removing a portion of the plurality of test points that do not conform to the setting rule and retaining another portion of the plurality of test points that conform to the setting rule, wherein the setting rule includes a test point spacing restriction; Arrange and combine, by the processor, the other portion of the plurality of test points of each of the plurality of center lines according to the setting rule to generate a plurality of candidate circuit test point diagrams, and calculate a test point coverage rate of each of the plurality of candidate circuit test point diagrams; as well as The processor determines a target circuit test point diagram having the highest test point coverage rate among the candidate circuit test point diagrams.

2. The circuit test point generation method according to claim 1, wherein: Also includes: Setting, by the processor, at least one measurement point prohibited placement area in the circuit diagram of the circuit; The plurality of test points are arranged outside the at least one test point prohibited placement area.

3. The circuit test point generation method according to claim 1, wherein: One of the other portion of the plurality of test points is regarded as a candidate test point for each of the plurality of center lines. When performing permutation and combination, the plurality of candidate test points of the plurality of center lines are selected, and one of the plurality of candidate test points that does not meet the setting rule is removed to generate one of the plurality of candidate circuit test point diagrams.

4. The circuit test point generation method according to claim 1, wherein: The measuring point spacing restriction includes a measuring point-to-measuring point spacing restriction, and the measuring point-to-measuring point spacing restriction indicates that a distance between two adjacent measuring points of each of the plurality of center lines is greater than a first preset distance.

5. The circuit test point generation method according to claim 4, wherein: The measurement point spacing limit also includes: an adjacent trace spacing limit, indicating that a spacing between one of the plurality of test points and one of the adjacent traces is greater than a second preset spacing; a spacing limit between a test point and an adjacent component, indicating that a spacing between one of the test points and a component of the circuit is greater than a third predetermined spacing; and A spacing limit between a test point and a hole in a circuit board indicates that a spacing between one of the test points and a hole in the circuit board is greater than a fourth preset spacing.

6. A circuit test point generation system, characterized in that: Include: A database for storing layout information and a configuration rule of a circuit, wherein the layout information includes routing information; and A processor is connected to the database and obtains the layout information of the circuit from the database. The processor is configured to perform operations including the following steps: generating a circuit diagram of the circuit according to the layout information; Obtaining a plurality of center lines of a plurality of routings of the circuit diagram according to the routing information; Setting a plurality of test points on each of the plurality of center lines; determining whether the plurality of test points of each of the plurality of center lines conform to the setting rule, removing a portion of the plurality of test points that do not conform to the setting rule and retaining another portion of the plurality of test points that conform to the setting rule, wherein the setting rule includes a test point spacing restriction; Arrange and combine the other portion of the plurality of test points of each of the plurality of center lines according to the setting rule to generate a plurality of candidate circuit test point diagrams, and calculate a test point coverage rate of each of the plurality of candidate circuit test point diagrams; and A target circuit test point diagram is determined as a target circuit test point diagram having the highest test point coverage among the candidate circuit test point diagrams.

7. The circuit test point generation system according to claim 6, wherein: The processor sets at least one test point prohibited placement area on the circuit diagram of the circuit, and the plurality of test points are set outside the at least one test point prohibited placement area.

8. The circuit test point generation system according to claim 6, wherein: One of the other portion of the plurality of test points is regarded as a candidate test point for each of the plurality of center lines. When performing permutation and combination, the plurality of candidate test points of the plurality of center lines are selected, and one of the plurality of candidate test points that does not meet the setting rule is removed to generate one of the plurality of candidate circuit test point diagrams.

9. The circuit test point generation system according to claim 6, wherein: The measuring point spacing restriction includes a measuring point-to-measuring point spacing restriction, and the measuring point-to-measuring point spacing restriction indicates that a distance between two adjacent measuring points of each of the plurality of center lines is greater than a first preset distance.

10. The circuit test point generation system according to claim 9, wherein: The measurement point spacing limit also includes: an adjacent trace spacing limit, indicating that a spacing between one of the plurality of test points and one of the adjacent traces is greater than a second preset spacing; a spacing limit between a test point and an adjacent component, indicating that a spacing between one of the test points and a component of the circuit is greater than a third predetermined spacing; and A spacing limit between a test point and a hole in a circuit board indicates that a spacing between one of the test points and a hole in the circuit board is greater than a fourth preset spacing.

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