FPGA + CPU-based hardware-in-loop test simulation method for permanent magnet synchronous motor

Abstract

According to the FPGA + CPU-based permanent magnet synchronous motor hardware-in-the-loop test simulation method provided by the invention, rapid verification and optimization of a motor control system can be realized through automatic tool chain development and a high-real-time simulation technology. The method comprises the following steps: firstly, building a mathematical model of a high-precision permanent magnet synchronous motor system on the basis of an HDL Coder modeling specification, and developing a whole set of complete solution covering model design, code generation, deployment and debugging on the basis of an HDL Coder Workflow Advisor; the method has the advantages of being high in universality, high in usability and low in cost, is suitable for various power electronic models with high-frequency requirements, optimizes and adapts to an FPGA + CPU multi-core heterogeneous computing architecture through a code generation technology, and achieves efficient hardware-in-loop simulation testing.

Description

Technical Field

[0001] The present invention relates to the technical field of hardware-in-the-loop simulation testing, and in particular to a permanent magnet synchronous motor hardware-in-the-loop testing simulation method based on FPGA+CPU. Background Art

[0002] Currently, there are several main implementation solutions for hardware-in-the-loop test simulation technology for permanent magnet synchronous motors: 1. Topological modeling solution based on Simscape This method uses the Simscape toolbox for physical modeling. Although the toolboxes are specially designed for power electronic system modeling, the model libraries are black boxes and cannot be modified as needed.

[0003] 2. Hardware-in-the-loop simulation solution based on LabVIEW This method provides graphical programming tools that support real-time testing and verification of motor control systems. However, its computational efficiency is low, especially when dealing with complex motor control algorithms. It struggles to meet the demands of high-precision motor control system simulation. Hardware compatibility is also a significant issue; different brands or models of hardware may not connect seamlessly, limiting its application.

[0004] 3. dSPACE-based hardware-in-the-loop simulation solution This method supports real-time simulation, control algorithm verification, and can accurately simulate the interaction between the motor and the control system. However, the dSPACE system is relatively expensive and is suitable for large-scale, high-precision simulation, but it may be unaffordable for small and medium-sized enterprises.

[0005] 4. Hardware-in-the-loop simulation solution based on RT-LAB This method is suitable for hardware-in-the-loop (HIL) and software-in-the-loop (SIL) simulation, providing real-time simulation capabilities, but has high hardware requirements. Especially under high real-time requirements, expensive hardware resources may be needed.

[0006] The above existing technologies generally have the following disadvantages: 1. Limited real-time simulation capabilities and complex hardware interfaces; 2. Low computing efficiency and hardware compatibility issues; 3. High cost and complex system configuration; 4. Steep learning curve and high hardware requirements. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a permanent magnet synchronous motor hardware-in-the-loop test simulation method based on FPGA+CPU, which can effectively solve the problems raised in the above background technology.

[0008] In order to solve the above problems, the technical solution adopted by the present invention is as follows: The present invention provides a permanent magnet synchronous motor hardware-in-the-loop test simulation method based on FPGA+CPU, which can realize rapid verification and optimization of the motor control system through automated tool chain development and high real-time simulation technology. First, a high-precision permanent magnet synchronous motor system mathematical model is built based on the HDL Coder modeling specification, and a complete solution covering model design, code generation, deployment and debugging is developed based on the HDL Coder Workflow Advisor. This method has the advantages of strong versatility, high ease of use and low cost. It is suitable for power electronic models with various high-frequency requirements, and optimizes and adapts the FPGA+CPU multi-core heterogeneous computing architecture through code generation technology to achieve efficient hardware-in-the-loop simulation testing.

[0009] The following steps are involved: Step 1: Create a mathematical model of the permanent magnet synchronous motor in the MATLAB / Simulink environment, including the motor body, inverter, encoder, resolver, and load model running on the FPGA, and the motor control algorithm based on Park transform and space vector pulse width modulation running on the CPU, and define the input and output interfaces. Step 2: Encapsulate the motor control algorithm and motor dynamic model as independent subsystems and configure interface parameters; Step 3: Convert the motor subsystem model into synthesizable hardware description code using the hardware description language code generation toolbox and select code optimization options; Step 4: Encapsulate the generated hardware description code into an FPGA IP core and complete functional simulation and timing verification; Step 5: Analyze the hardware resources of the FPGA board and define the signal interfaces supported by the tool chain; Step 6: Develop ADC / DAC driver code based on the datasheet timing to achieve precise control of signal acquisition and output; Step 7: Build a high-speed data transmission module between FPGA and CPU based on PCIe communication protocol; Step 8: Integrate the hardware driver module, communication module, and user IP core in the FPGA development environment, and complete clock distribution, pin constraints, and timing optimization; Step 9: Configure the tool chain through automated scripts to achieve one-click deployment from simulation model to FPGA bitstream; Step 10: Build a collaborative computing architecture between the FPGA and the CPU. The FPGA runs the motor system model, the CPU processes the control algorithm, and implements cross-domain data exchange through PCIe DMA. Step 11: Connect the digital input and output channels of the FPGA to the signal interface of the motor controller to simulate sensor signals and collect feedback signals; Step 12: Implement nanosecond-level time synchronization between FPGA and CPU based on the PTP precision clock protocol; Step 13: Execute the automated test process through the host computer, simulate various working conditions and generate a test report.

[0010] As a further preferred embodiment of the present invention, the toolbox in step 3 is an HDL Coder toolbox. The motor subsystem model is automatically converted into synthesizable VHDL / Verilog code using the HDLCoder toolbox. Code optimization includes pipeline design and resource reuse.

[0011] As a further preferred solution of the present invention, in step 4, the generated HDL code is encapsulated as an FPGA IP core through the HDL Workflow Advisor, and functional simulation and timing verification are performed to ensure logical correctness and timing closure.

[0012] As a further preferred embodiment of the present invention, the driving code of the ADC / DAC module in step 6 is controlled by a state machine, and the signal acquisition error is less than 0.1%.

[0013] As a further preferred solution of the present invention, the PCIe communication module in step 7 is constructed based on the Xilinx XDMAIP core and uses the AXI-Lite bus protocol to extend the registers.

[0014] As a further preferred embodiment of the present invention, in step 10, the update rate of the motor system model run by the FPGA is 100 MHz, the cycle of the CPU processing the control algorithm is 1 ms, and the cross-domain communication delay is <1 μs.

[0015] As a further preferred embodiment of the present invention, step 11 specifically includes connecting the DIO channel of the FPGA to the PWM input of the motor controller, the AO channel simulates the current sensor signal, and the DI channel collects the encoder position feedback.

[0016] As a further preferred solution of the present invention, the step 12 uses the IEEE 1588 PTP protocol to achieve time synchronization, with a timing jitter of <±50ns.

[0017] Compared with the existing technology, the present invention provides a permanent magnet synchronous motor hardware-in-the-loop test simulation method based on FPGA+CPU, which has the following beneficial effects: 1. Improved efficiency: Development cycle shortened from 6 months to 2 months Through model-based design (MBD) methodologies and automated tool chains, we achieve full automation from algorithm design to hardware deployment. FPGA code generation eliminates traditional manual coding, while one-click deployment of simulation models reduces debugging time by 80%. A multi-domain collaborative test platform enables parallel verification, significantly improving overall development efficiency.

[0018] 2. Cost reduction: hardware costs reduced by 60% (domestic alternative) By replacing imported components with domestically produced chips and integrating independently developed driver modules and interface solutions, the tool chain supports optimized hardware resource allocation, reduces redundant design, and achieves high test system integration, lowering equipment procurement and maintenance costs. Overall hardware investment is only 40% of that of similar international solutions.

[0019] 3. Accuracy guarantee: current simulation error <0.5%, speed control accuracy ±1rpm Based on a 16-bit high-precision ADC / DAC and a 10MHz update rate FPGA model, the system accurately reproduces PWM harmonic characteristics. Adaptive filtering algorithms eliminate signal noise, combined with dead-zone compensation technology, ensure the authenticity of current simulation. A time synchronization mechanism (PTP) ensures the timing accuracy of control commands.

[0020] 4. Flexible expansion: supports multiple motor types and even other power systems The modular architecture allows for rapid switching of motor models through parameter configuration, and the tool chain supports automatic adaptation of multiple control algorithms (such as FOC and DTC). Standardized hardware interfaces and communication protocols enable scalability and compatibility with motor systems of varying power levels and topologies, and even power electronics systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Develop a flow chart for the FPGA tool chain; Figure 2 This is the effect diagram of recording the AD channel excitation signal in step six of the present invention; Figure 3 This is the Sine wave output effect diagram of the rotary transformer in step thirteen of the present invention. DETAILED DESCRIPTION

[0022] It should be noted that if "and / or" or "and / or" appears in the full text, its meaning includes three parallel options. Taking "A and / or B" as an example, it includes option A, or option B, or options in which A and B are met at the same time.

[0023] In addition, the embodiments are based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0024] Explanation of terms: 1. Hardware-in-the-Loop Simulation (HIL) is a real-time simulation technology that combines actual hardware (such as a controller) with a simulation model to verify the hardware's performance in a virtual environment. It is commonly used for testing and verifying complex systems and can verify control system performance without using the actual controlled object.

[0025] 2.FPGA (Field-Programmable Gate Array) A programmable logic device whose internal logic circuits can be configured by users according to their needs. It is suitable for scenarios such as parallel computing and signal processing.

[0026] 3. HDL (Hardware Description Language) Programming languages ​​(such as VHDL / Verilog) used to describe the behavior of digital circuits.

[0027] 4. PCIE (Peripheral Component Interconnect Express) high-speed serial bus standard that supports multi-channel data transmission.

[0028] 5. Xilinx Vivado IDE An integrated development environment developed by Xilinx for design, simulation, and debugging of FPGAs and SoCs, supporting the complete development process from RTL design to bitstream generation. 6.AXI4 bus The high-performance bus protocol defined by ARM is part of the AMBA (Advanced Microcontroller Bus Architecture) specification and is used for communication between IP cores.

[0029] 7. SVPWM (Space Vector Pulse Width Modulation) Motor control algorithm that optimizes inverter switching states.

[0030] 8.PTP (Precision Time Protocol) A network protocol that enables nanosecond-level clock synchronization in distributed systems.

[0031] 9.Simulink HDL Coder A MATLAB tool for converting Simulink models into hardware description languages ​​(such as Verilog or VHDL) suitable for FPGA and ASIC design, enabling rapid implementation of hardware-accelerated algorithms.

[0032] Reference Figure 1-3The present invention provides a permanent magnet synchronous motor hardware-in-the-loop test simulation method based on FPGA+CPU, comprising the following steps: Step 1: Simulink mathematical modeling Build a mathematical model of a permanent magnet synchronous motor (PMSM) in the MATLAB / Simulink environment, including the motor body, inverter, encoder, resolver, and load model running on the FPGA, and the control algorithm logic based on Park transform and space vector pulse width modulation (SVPWM) running on the CPU. Define the input and output interfaces (PWM signal, three-phase current, speed / position feedback).

[0033] Step 2: Model subsystem packaging Encapsulate the motor control algorithm and motor dynamic model as independent subsystems, configure interface parameters (such as signal bit number and sampling rate) to ensure model modularity and portability.

[0034] Step 3: Automatically generate HDL code The HDL Coder toolbox automatically converts motor subsystem models into synthesizable VHDL / Verilog code, improving hardware implementation efficiency through code optimization options such as pipelining and resource reuse.

[0035] Step 4: IP core generation and verification The generated HDL code is packaged into an FPGA IP core using the HDL Workflow Advisor, and functional simulation (ModelSim) and timing verification (Vivado) are performed to ensure logical correctness and timing closure (meeting the 10ns clock cycle constraint).

[0036] Step 5: Board resource analysis and requirement definition For the Xilinx Kintex7-325T FPGA board, analyze its hardware resources (325K logic units, 8-channel ADC / DAC, 16-channel DI / DO, PCIe interface) and define the signal interfaces supported by the toolchain (16-channel AIO, 32-channel DIO, PCIe registers).

[0037] Step 6: Driver code development Based on the AD7606 (ADC) and DA8568 (DAC) datasheet timing, a state machine-driven HDL code was written to achieve precise control of analog signal acquisition (0-10V) and output (4-20mA), with an error of <0.1%. The AD channel signal acquisition effect diagram is as follows Figure 2 shown.

[0038] Step 7: PCIe interface design The Xilinx XDMA IP core is used to build a PCIe communication module, which extends 256 64-bit registers through the AXI-Lite bus protocol to support high-speed data transmission (bandwidth 4GB / s) under the Linux system.

[0039] Step 8: Hardware Engineering Integration Create a Block Design in the Vivado IDE, connect the ADC / DAC driver module, PCIe interface module, and user IP core, and complete clock distribution (200 MHz main frequency), pin constraints (LVCMOS33 level), and timing optimization (Slack > 0.5 ns).

[0040] Step 9: Toolchain automatic configuration Write board registration files (describing port names, quantities, and bit counts) and TCL scripts (automated engineering construction) to achieve one-click deployment from Simulink models to FPGA bitstreams, supporting batch generation and version management. The FPGA tool chain development process is as follows: Figure 1 shown.

[0041] Step 10: Building a Heterogeneous Hardware Architecture Build an FPGA+CPU collaborative platform: The FPGA runs the motor system model (100MHz update rate, simulating PWM harmonics and dead-zone effects), the CPU (x86) processes the motor control algorithm model (1ms cycle), and cross-domain data exchange is achieved through PCIe DMA (latency <1μs).

[0042] Step 11: Signal Level Interface Connection The FPGA's DIO channel is connected to the motor controller (MCU)'s PWM input (frequency 20kHz), the AO channel simulates the current sensor signal (±10V), and the DI channel collects the encoder position feedback (1024-line resolution).

[0043] Step 12: Real-time synchronization mechanism design Nanosecond-level time synchronization between the FPGA and CPU is achieved based on the PTP precision clock protocol (IEEE 1588). Control instructions and simulation data are aligned through timestamps to ensure timing consistency (jitter <±50ns).

[0044] Step 13: Automated testing process Send test instructions through the host computer (LabVIEW) to simulate acceleration, braking, short circuit and other working conditions, and record the motor response data (speed, torque, current, resolver waveform) in real time. The resolver effect diagram is as follows Figure 3 As shown, a test report (PDF / Excel format) is generated, which supports integration with MES system.

[0045] Automatically generate HDL code from Simulink models and package them into IP cores, eliminating manual coding. Define board interface resources (AIO / DIO / PCIe) to automatically connect driver modules to user IP cores. Enable nanosecond-level synchronization between the FPGA and CPU using the PTP protocol, with timing jitter <±50ns. Accurately simulate PWM harmonics with a 100MHz model update rate and dead-time error <0.1μs.

[0046] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made by using the contents of the present invention description and drawings under the inventive concept of the present invention, or direct / indirect application in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A hardware-in-the-loop test simulation method for a permanent magnet synchronous motor based on FPGA+CPU, characterized in that: The following steps are involved: Step 1: Create a mathematical model of the permanent magnet synchronous motor in the MATLAB / Simulink environment, including the motor body, inverter, encoder, resolver, and load model running on the FPGA, and the motor control algorithm based on Park transform and space vector pulse width modulation running on the CPU, and define the input and output interfaces. Step 2: Encapsulate the motor control algorithm and motor dynamic model as independent subsystems and configure interface parameters; Step 3: Convert the motor subsystem model into synthesizable hardware description code using the hardware description language code generation toolbox and select code optimization options; Step 4: Encapsulate the generated hardware description code into an FPGA IP core and complete functional simulation and timing verification; Step 5: Analyze the hardware resources of the FPGA board and define the signal interfaces supported by the tool chain; Step 6: Develop ADC / DAC driver code based on the datasheet timing to achieve precise control of signal acquisition and output; Step 7: Build a high-speed data transmission module between FPGA and CPU based on PCIe communication protocol; Step 8: Integrate the hardware driver module, communication module, and user IP core in the FPGA development environment, and complete clock distribution, pin constraints, and timing optimization; Step 9: Configure the tool chain through automated scripts to achieve one-click deployment from simulation model to FPGA bitstream; Step 10: Build a collaborative computing architecture between the FPGA and the CPU. The FPGA runs the motor system model, the CPU processes the control algorithm, and implements cross-domain data exchange through PCIe DMA. Step 11: Connect the digital input and output channels of the FPGA to the signal interface of the motor controller to simulate sensor signals and collect feedback signals; Step 12: Implement nanosecond-level time synchronization between FPGA and CPU based on the PTP precision clock protocol; Step 13: Execute the automated test process through the host computer, simulate various working conditions and generate a test report.

2. The FPGA+CPU-based permanent magnet synchronous motor hardware-in-the-loop test simulation method according to claim 1, characterized in that: The toolbox in step 3 is the HDL Coder toolbox. The HDL Coder toolbox is used to automatically convert the motor subsystem model into synthesizable VHDL / Verilog code. Code optimization includes pipeline design and resource reuse.

3. The FPGA+CPU-based permanent magnet synchronous motor hardware-in-the-loop test simulation method according to claim 2, characterized in that: In step 4, the generated HDL code is packaged into an FPGA IP core through the HDL Workflow Advisor, and functional simulation and timing verification are performed to ensure logical correctness and timing closure.

4. The FPGA+CPU-based permanent magnet synchronous motor hardware-in-the-loop test simulation method according to claim 3, characterized in that: The driving code of the ADC / DAC module in step 6 is controlled by a state machine, and the signal acquisition error is less than 0.1%.

5. The FPGA+CPU-based permanent magnet synchronous motor hardware-in-the-loop test simulation method according to claim 4 is characterized in that: The PCIe communication module in step 7 is built based on the Xilinx XDMA IP core and uses the AXI-Lite bus protocol to extend the register.

6. The FPGA+CPU-based permanent magnet synchronous motor hardware-in-the-loop test simulation method according to claim 5, characterized in that: In step 10, the update rate of the motor system model run by the FPGA is 100 MHz, the cycle of the CPU processing the control algorithm is 1 ms, and the cross-domain communication delay is <1 μs.

7. The FPGA+CPU-based permanent magnet synchronous motor hardware-in-the-loop test simulation method according to claim 6, characterized in that: The step 11 specifically includes connecting the DIO channel of the FPGA to the PWM input of the motor controller, the AO channel simulates the current sensor signal, and the DI channel collects the encoder position feedback.

8. The FPGA+CPU-based permanent magnet synchronous motor hardware-in-the-loop test simulation method according to claim 7, characterized in that: The step 12 uses the IEEE 1588 PTP protocol to achieve time synchronization, with a timing jitter of <±50ns.

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