Cascade signal processing circuit based on separate components

Abstract

The invention discloses a cascading signal processing circuit based on separation components, and belongs to the technical field of signal processing circuits. The cascading signal processing circuit comprises a first circuit, a second circuit, a cascading convergence point J1, a third circuit and a cascading convergence point J2. The circuit is composed of three circuit parts which are all designed by using separation elements, based on the cost and flexible layout advantages of the separation elements, parameter matching under the requirements of signal anti-shake and signal latching flexibility is achieved, and the circuit can respond to high-speed abrupt change signals and can also adapt to anti-interference application of conventional level or pulse signals. On the premise that the circuit topology is not changed, grouping cascading of multiple intra-group signals and multi-path cascading of multiple paths of signals are supported, and meanwhile infinite cascading of interrupt signals corresponding to the multiple paths of signals and time division multiplexing summarizing access of the interrupt signals are achieved; and the effects of reducing the circuit cost, the PCB layout flexibility, the function and performance adaptation flexibility and the cascade expansibility are obvious.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing circuits, and in particular to a cascaded signal processing circuit based on discrete components. Background Art

[0002] In control systems with multiple signal inputs, MCUs are mostly used to detect changes in signal status and then perform logical judgment, calculation, output control, display, etc.

[0003] As a single-threaded processing chip, most MCUs find it difficult to scan the changes in various signals in real time and respond quickly, so the signals need to be connected to the chip's interrupt port. When the number of input signals is large, such as the corresponding circuit where dozens of people participate in a quick-answer game, due to limited interrupt hardware resources, on the one hand, multiple signals are aggregated and input into the interrupt port, and on the other hand, the status of each signal is input into the chip's GPIO or bus interface. Once the signal changes, the interrupt can be triggered in time, and the status of multiple signals can be scanned at the first time.

[0004] In existing circuits that aggregate the changes in multiple signals into an interrupt input, integrated circuits, such as monostable multivibrator chips, are typically used to convert the rising or falling edges of these signals into a single output pulse signal. However, this conventional circuit has the following drawbacks.

[0005] In terms of cost, in this application field, the price of a single integrated chip based on the circuit application of integrated chips is generally the sum of dozens of conventional capacitors, resistors, transistors and other discrete components, which is relatively costly.

[0006] In terms of flexibility, the PCB layout of large-size chips is relatively "clumsy", especially when the circuit board space is small. When the chip is replaced, the peripheral circuit may be adjusted as a whole. There are defects such as difficulty in fine-tuning a single parameter, large changes in the circuit adjustment body after changes in the power supply voltage amplitude, insufficient chip supply and few replaceable categories.

[0007] In terms of scalability, a single chip has a limited number of pins. Once the chip pins are saturated, the number of new input signals is limited. Using multiple chips to access signals may result in excessive redundancy or multiple interrupt outputs from multiple chips, and simultaneous interrupt output from existing chips. When the MCU interrupt hardware resources are full, scalability is limited. If expansion continues, it may be necessary to add a new next-level signal aggregation circuit. At this time, the circuit topology may change, which will cause potential problems such as increased time costs for developing new circuits and reduced design reliability.

[0008] In summary, conventional solutions have certain shortcomings in cost, flexibility, and scalability, and are in urgent need of improvement. Summary of the Invention

[0009] In order to solve the above problems, the present invention provides a cascaded signal processing circuit based on discrete components.

[0010] The present invention is achieved through the following technical solutions: A cascaded signal processing circuit based on discrete components, comprising circuit one, circuit two, a cascade junction J1, circuit three, and a cascade junction J2. Circuit one is connected to the cascade junction J1, the cascade junction J1 is connected to circuit two, the circuit two is connected to circuit three, and the circuit three is connected to the cascade junction J2.

[0011] Preferably, the circuit 1 is a signal amplification circuit, in which the power supply VCC1 is connected to the first end of the resistor R1, the second end of the resistor R1 is connected to the anode of the diode of the optocoupler U1, the cathode of the diode of the optocoupler U1 is connected to the first end of the switch S1, the second end of the switch S1 is grounded, the emitter of the transistor of the optocoupler U1 is grounded, the collector of the transistor of the optocoupler U1 is connected to the power supply VCC via the resistor R2, the collector of the transistor of the optocoupler U1 is connected to the base of the transistor Q1, the emitter of the transistor Q1 is grounded, and the collector of the transistor Q1 is connected to the first end of the resistor R3 The second end of the resistor R3 is connected to the power supply VCC, the first end of the resistor R3 is connected to the first end of the resistor R4, the second end of the resistor R4 is connected to the base of the transistor Q2, the emitter of the transistor Q2 is connected to the power supply VCC, the collector of the transistor Q2 is connected to the first end of the resistor R5, the second end of the resistor R5 is grounded, the collector of the transistor Q2 is connected to the anode of the diode D1, the cathode of the diode D1 serves as the OUT point of circuit one, and the OUT point of circuit one is connected to the cascade junction J1; the cascade junction J1 is the access point of the OUT points of several circuits one.

[0012] Preferably, the second circuit implements latching and filtering of sudden change signals. In the second circuit, a first end of a resistor R21 is connected to the cascade junction J1, a second end of the resistor R21 is connected to a first end of a resistor R22, a second end of the resistor R22 is grounded, a first end of the resistor R21 is connected to a first end of a capacitor C21, a second end of the capacitor C21 is grounded, a first end of the capacitor C21 is connected to a first end of a resistor R23, a second end of the resistor R23 is connected to a base of a transistor Q21, an emitter of the transistor Q21 is grounded, a collector of the transistor Q21 is connected to a power supply VCC via a resistor R24, a collector of the transistor Q21 is connected to a base of a transistor Q22 via a resistor R25, an emitter of the transistor Q22 is grounded, and a collector of the transistor Q22 is connected to a power supply VCC via a resistor R26. The second circuit includes two output signals: an interrupt signal IRQ 1 and a GPIO 1.

[0013] Preferably, the circuit three realizes the conversion from rising edge signal input to negative pulse signal output, IRQ 1 in the circuit three and IRQ 1 in the circuit two are the same node, the IRQ 1 point is connected to the first end of the resistor R31, the second end of the resistor R31 is connected to the base of the transistor Q31, the emitter of the transistor Q31 is connected to the first end of the capacitor C31, the second end of the capacitor C31 is grounded, the collector of the transistor Q31 is connected to the power supply VCC via the resistor R33, the first end of the resistor R31 is connected to the first end of the resistor R32, and the second end of the resistor R32 is connected to the first end of the capacitor C31; the OUT point of the circuit three outputs a pulse signal.

[0014] Preferably, the OUT point in the circuit three is connected to the cascade junction J2, the cascade junction J2 is connected to the interrupt port of the MCU, and the negative pulse signal of the circuit three outputs a negative pulse after passing through the cascade junction J2. The OUT points in multiple circuits three are connected to the cascade junction J2 to realize time-sharing multiplexing of multiple interrupt signals and aggregate access to a single interrupt port of the MCU.

[0015] Preferably, multiple OUT points in the circuit three are connected to the cascade junction J2, and the negative pulse signal of the circuit three outputs a positive pulse at the IRQ all point after passing through the cascade junction J2 and the NOT gate D31, thereby realizing time-sharing multiplexing of multiple interrupt signals and accessing a single interrupt port of the MCU.

[0016] Preferably, the GPIO 1 in the second circuit is connected to the IO pin of the MCU, or is connected to the MCU after being serially connected via the chip.

[0017] Preferably, a series discharge circuit of a diode and a resistor is connected in parallel at both ends of R32.

[0018] Compared with the prior art, the present invention has the following beneficial effects: The present invention consists of three circuit parts, all of which are designed using separate components. Based on the cost and flexible layout advantages of separate components, the parameters of signal anti-shake and signal latching can be matched under flexible requirements. It can respond to high-speed sudden change signals and can also adapt to anti-interference applications of conventional level or pulse signals.

[0019] Without changing the circuit topology, the present invention supports group cascading of multiple intra-group signals and multi-channel cascading of multiple-channel signals, while realizing unlimited cascading of interrupt signals corresponding to the multiple-channel signals and their time-division multiplexing and aggregated access; it has obvious effects in reducing circuit costs, PCB layout flexibility, function and performance adaptation flexibility, and cascade expandability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1Schematic diagram of the circuit structure of the present invention. DETAILED DESCRIPTION

[0021] The present invention will be further described below with reference to the accompanying drawings: As shown in the attached figure of the instruction manual Figure 1 The application circuit shown includes circuit 1, circuit 2, cascade junction J1, circuit 3, cascade junction J2 and NOT gate D31. Circuit 1 is connected to cascade junction J1, cascade junction J1 is connected to circuit 2, circuit 2 is connected to circuit 3, and circuit 3 is connected to cascade junction J2 and NOT gate D31 to output a positive pulse.

[0022] As attached Figure 1 As shown, in circuit 1, the power supply VCC1 is connected to the first end of the resistor R1, the second end of the resistor R1 is connected to the anode of the diode of the optocoupler U1, the cathode of the diode of the optocoupler U1 is connected to the first end of the switch S1, the second end of the switch S1 is grounded, the emitter of the transistor of the optocoupler U1 is grounded, the collector of the transistor of the optocoupler U1 is connected to the power supply VCC via the resistor R2, the collector of the transistor of the optocoupler U1 is connected to the base of the transistor Q1, the emitter of the transistor Q1 is grounded, the collector of the transistor Q1 is connected to the first end of the resistor R3, and the base of the transistor R3 is grounded. The second end is connected to the power supply VCC, the first end of the resistor R3 is connected to the first end of the resistor R4, the second end of the resistor R4 is connected to the base of the transistor Q2, the emitter of the transistor Q2 is connected to the power supply VCC, the collector of the transistor Q2 is connected to the first end of the resistor R5, the second end of the resistor R5 is grounded, the collector of the transistor Q2 is connected to the anode of the diode D1, the cathode of the diode D1 serves as the OUT point of the circuit one, and the OUT point of the circuit one is connected to the cascade junction J1; the cascade junction J1 is the access point of the OUT points of several circuits one.

[0023] Circuit 2 implements latching and filtering of sudden change signals. In Circuit 2, a first end of resistor R21 is connected to cascade junction J1, a second end of resistor R21 is connected to a first end of resistor R22, a second end of resistor R22 is grounded, a first end of resistor R21 is connected to a first end of capacitor C21, a second end of capacitor C21 is grounded, a first end of capacitor C21 is connected to a first end of resistor R23, a second end of resistor R23 is connected to the base of transistor Q21, an emitter of transistor Q21 is grounded, a collector of transistor Q21 is connected to power supply VCC via resistor R24, a collector of transistor Q21 is connected to the base of transistor Q22 via resistor R25, an emitter of transistor Q22 is grounded, and a collector of transistor Q22 is connected to power supply VCC via resistor R26. Circuit 2 includes two output signals: interrupt signal IRQ 1 and GPIO 1.

[0024] Circuit three implements the conversion from rising edge signal input to negative pulse signal output. IRQ 1 in circuit three and IRQ 1 in circuit two are the same node. IRQ 1 is connected to the first end of resistor R31, the second end of resistor R31 is connected to the base of transistor Q31, the emitter of transistor Q31 is connected to the first end of capacitor C31, the second end of capacitor C31 is grounded, the collector of transistor Q31 is connected to power supply VCC via resistor R33, the first end of resistor R31 is connected to the first end of resistor R32, and the second end of resistor R32 is connected to the first end of capacitor C31. The OUT point of circuit three outputs a pulse signal. The OUT points of multiple circuits three are connected to the cascade junction J2. After the negative pulse signal of circuit three passes through the cascade junction J2 and the NOT gate D31, a positive pulse is output at the IRQ all point, thereby realizing time-sharing multiplexing of multiple interrupt signals and aggregating them into a single interrupt port of the MCU.

[0025] The NOT gate D31 may not be set in the circuit, and the cascade junction J2 may be directly connected to the interrupt port of the MCU. The negative pulse signals of the OUT points of multiple circuits three output negative pulses after passing through the cascade junction J2. The OUT points of multiple circuits three are connected to the cascade junction J2 to realize time-sharing multiplexing of multiple interrupt signals and aggregate them into a single interrupt port of the MCU.

[0026] Circuit 1 is a signal amplification circuit. The input signal in Circuit 1 uses the normally closed pushbutton switch S1 as an example. When the switch is pressed, the optocoupler U1 outputs a high impedance, transistor Q1 turns on, and transistor Q1's collector C is low. At this point, transistor Q2 turns on, and the OUT point of Circuit 1 outputs a high level.

[0027] Circuit 1 as a whole is used to capture small-amplitude, transient signals and output the corresponding amplified signal at the OUT point. The cascade junction J1 connects the OUT points of multiple Circuit 1s. Diode D1 in Circuit 1 isolates the signals from the lower-level circuits. Furthermore, when multiple Circuit 1s are connected via the cascade junction J1, a logical AND operation is performed by the multiple diodes D1. This means that if the OUT point of any Circuit 1 is high, then point J1 is also high.

[0028] Resistors R21 and R22 in Circuit 2 implement voltage division, and the circuitry associated with transistors Q21 and Q22 forms a two-stage amplification circuit for the input signal. Circuit 2 as a whole separates the amplitude and rising / falling trends of the two output signals, interrupt signal IRQ 1 and GPIO 1, as shown in the figure. The specific operating principle and process are as follows: (1) When the voltage V at point J1 changes from a low level to a high level, that is, during the rising edge, the level of IRQ 1 is V*(R22 / (R21+R22)). The source signal voltage of GPIO 1 in circuit 2 is also V, that is, the voltage at the front end of resistor R23. After two-stage amplification, the amplitude of this voltage is greater than or equal to V (after Q21 is turned on). Due to the presence of capacitor C21, the rising process of voltage V is inclined. Therefore, during the rising process of voltage V, the voltage amplitude and slope of GPIO 1 are greater than the input signal voltage V. Therefore, during the rising edge of voltage V at point J1, the voltage amplitude of GPIO 1 is greater than the voltage amplitude of IRQ 1, and the voltage slope of GPIO 1 is greater than the voltage slope of IRQ 1.

[0029] (2) When the voltage V at point J1 changes from a high level to a low level, that is, during the falling edge, before transistor Q21 is cut off, the voltage amplitude of GPIO 1 is greater than the voltage amplitude of IRQ 1. At the same time, when transistor Q21 is about to be cut off but has not yet been cut off, the amplitude of IRQ 1 is already small. Assuming that R21 and R22 have the same resistance value and the cut-off voltage of transistor Q21 is 0.7V, the voltage of IRQ 1 is about 0.35V at this time, and the voltage amplitude of GPIO 1 is close to VCC. In summary, if point J1 is a pulse voltage, points IRQ 1 and GPIO 1 are also approximately pulse voltages. The pulse amplitude of IRQ 1 is smaller than that of GPIO 1, the pulse width of IRQ 1 is smaller than that of GPIO 1, and relative to the pulse of IRQ 1, the pulse of GPIO 1 first rises and then falls.

[0030] Circuit 2 latches and filters sudden signal fluctuations. When capacitor C21 is low, the voltage pulse width between IRQ 1 and GPIO 1 is narrow, making the interrupt response sensitive and enabling rapid signal fluctuations. When capacitor C21 is high, the voltage pulse width between IRQ 1 and GPIO 1 is wide, resulting in a slow interrupt response. This helps mitigate high-frequency disturbances and implement key debounce. Circuit 2 latches valid pulse input signals, ensuring that the GPIO1 signal remains readable for a period of time after the IRQ 1 interrupt signal is received. Furthermore, increasing the value of resistor R21 reduces the amplitude of the interrupt IRQ 1 signal, effectively providing debounce. Decreasing the value of resistor R21 increases the sensitivity of the IRQ 1 interrupt signal level. Adjusting the resistor and capacitor parameters based on the MCU's response speed and actual application scenario allows for flexible adaptation to application requirements.

[0031] Circuit 3 converts a rising-edge signal into a negative-pulse signal. IRQ 1 in Circuit 3 and Circuit 2 share the same node. When the signal level at IRQ 1 changes from low to high (a rising edge), transistor Q31 turns on. At this point, the voltage at OUT in Circuit 3 changes from VCC to zero, signaling a falling edge. Simultaneously, VCC charges capacitor C31 through resistor R33 and transistor Q31. When the voltage at C31 approaches the voltage at IRQ 1, the transistor turns off, and the voltage at OUT in Circuit 3 changes from zero to VCC, signaling a rising edge.

[0032] Therefore, Circuit 3 achieves the conversion from a rising edge signal input to a negative pulse signal output. Adjusting the capacitance of capacitor C31 adjusts the output pulse width: a larger capacitance results in a wider pulse width, and vice versa. Capacitor C31 can be discharged through resistor R32. If necessary, a series discharge circuit consisting of a diode and resistor can be added in parallel across R32 to adjust the discharge time of capacitor C31.

[0033] The above negative pulse signal passes through the cascade junction J2 and the NOT gate D31, making the rising edge or falling edge steeper. Figure 1 The IRQ all points in the output positive pulse. When there are multiple interrupt signals input in time sharing, the circuit can be copied three times, press Figure 1 In the design method, the OUTs of multiple circuits 3 are connected to the cascade junction J2, realizing time-sharing multiplexing of multiple interrupt signals and accessing a single interrupt port of the MCU.

[0034] In actual circuit design applications, any input signal connected to the MCU needs to be formed by performing a logical AND operation on multiple parallel signals. In this solution, the parallel signal of the signal connected to the MCU is defined as an intra-group signal, the cascade of intra-group signals is defined as group cascade, the output signal after group cascade is defined as a path signal, and the cascade of path signals is defined as path cascade.

[0035] When the circuit is actually used, if a new signal needs to be added directly or indirectly to the MCU input pin, a complete set of Figure 1 The circuit can be reconfigured by removing J2 and the NOT gate. The specific connections are as follows: In the new circuit: connect IRQ 1 of Circuit 2 to IRQ 1 of Circuit 3. Connect the OUT pin of Circuit 3 to the cascade junction J2. Connect GPIO 1 of Circuit 2 to an unused MCU IO pin, or connect it via an IC or other chip. Adding multiple signals is done in the same way as above, allowing for multi-channel cascading of any number of signals.

[0036] If you need to add an intra-group signal to any input signal of the MCU, you only need to add a complete set of Circuit 1 and connect the OUT point in Circuit 1 to the cascade junction J1. The method of adding multiple intra-group signals is similar, thus realizing group cascade with unlimited number of intra-group signals.

[0037] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent changes and modifications to the shape, structure, characteristics and spirit described in the claims of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A cascaded signal processing circuit based on discrete components, characterized in that: The cascaded signal processing circuit includes circuit 1, circuit 2, a cascade junction J1, circuit 3 and a cascade junction J2. Circuit 1 is connected to the cascade junction J1, the cascade junction J1 is connected to circuit 2, the circuit 2 is connected to circuit 3, and the circuit 3 is connected to the cascade junction J2.

2. The cascadeable signal processing circuit based on discrete components according to claim 1, characterized in that: The circuit 1 is a signal amplifying circuit, in which the power supply VCC1 is connected to the first end of the resistor R1, the second end of the resistor R1 is connected to the anode of the diode of the optocoupler U1, the cathode of the diode of the optocoupler U1 is connected to the first end of the switch S1, the second end of the switch S1 is grounded, the emitter of the transistor of the optocoupler U1 is grounded, the collector of the transistor of the optocoupler U1 is connected to the power supply VCC via the resistor R2, the collector of the transistor of the optocoupler U1 is connected to the base of the transistor Q1, the emitter of the transistor Q1 is grounded, and the collector of the transistor Q1 is connected to the first end of the resistor R3. The second end of the resistor R3 is connected to the power supply VCC, the first end of the resistor R3 is connected to the first end of the resistor R4, the second end of the resistor R4 is connected to the base of the transistor Q2, the emitter of the transistor Q2 is connected to the power supply VCC, the collector of the transistor Q2 is connected to the first end of the resistor R5, the second end of the resistor R5 is grounded, the collector of the transistor Q2 is connected to the anode of the diode D1, the cathode of the diode D1 serves as the OUT point of circuit one, and the OUT point of circuit one is connected to the cascade junction J1; the cascade junction J1 is the access point for the OUT points of several circuits one.

3. The cascadeable signal processing circuit based on discrete components according to claim 1, characterized in that: Circuit 2 implements latching and filtering of sudden change signals. A first end of a resistor R21 in circuit 2 is connected to a cascade junction J1, a second end of the resistor R21 is connected to a first end of a resistor R22, a second end of the resistor R22 is grounded, a first end of the resistor R21 is connected to a first end of a capacitor C21, a second end of the capacitor C21 is grounded, a first end of the capacitor C21 is connected to a first end of a resistor R23, a second end of the resistor R23 is connected to a base of a transistor Q21, an emitter of the transistor Q21 is grounded, a collector of the transistor Q21 is connected to a power supply VCC via a resistor R24, a collector of the transistor Q21 is connected to a base of a transistor Q22 via a resistor R25, an emitter of the transistor Q22 is grounded, and a collector of the transistor Q22 is connected to a power supply VCC via a resistor R26. Circuit 2 includes two output signals: an interrupt signal IRQ 1 and a GPIO 1.

4. The cascadeable signal processing circuit based on discrete components according to claim 1, characterized in that: The circuit three realizes the conversion from rising edge signal input to negative pulse signal output. IRQ 1 in the circuit three and IRQ 1 in the circuit two are the same node. The IRQ 1 point is connected to the first end of the resistor R31, the second end of the resistor R31 is connected to the base of the transistor Q31, the emitter of the transistor Q31 is connected to the first end of the capacitor C31, the second end of the capacitor C31 is grounded, the collector of the transistor Q31 is connected to the power supply VCC via the resistor R33, the first end of the resistor R31 is connected to the first end of the resistor R32, and the second end of the resistor R32 is connected to the first end of the capacitor C31; the OUT point of the circuit three outputs a pulse signal.

5. The cascadeable signal processing circuit based on discrete components according to claim 4, characterized in that: The OUT point in the circuit three is connected to the cascade junction J2, and the cascade junction J2 is connected to the interrupt port of the MCU. The negative pulse signal of the circuit three outputs a negative pulse after passing through the cascade junction J2. The OUT points in multiple circuits three are connected to the cascade junction J2 to realize time-sharing multiplexing of multiple interrupt signals and aggregate them into a single interrupt port of the MCU.

6. The cascadeable signal processing circuit based on discrete components according to claim 5, characterized in that: Multiple OUT points in the circuit three are connected to the cascade junction J2. After the negative pulse signal of the circuit three passes through the cascade junction J2 and the NOT gate D31, a positive pulse is output at the IRQ all point, realizing time-sharing multiplexing of multiple interrupt signals and accessing a single interrupt port of the MCU.

7. The cascadeable signal processing circuit based on discrete components according to claim 3, characterized in that: The GPIO 1 in the second circuit is connected to the IO pin of the MCU, or is connected to the MCU after being parallel-input and serial-output through the chip.

8. The cascadeable signal processing circuit based on discrete components according to claim 3, characterized in that: A series discharge circuit of a diode and a resistor is connected in parallel at both ends of R32.

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