Relaxation oscillator with oscillation frequency irrelevant to temperature

Abstract

The invention relates to a relaxation oscillator irrelevant to oscillation frequency and temperature. The relaxation oscillator comprises a reference module, a bias current source module and an oscillator core circuit module, the reference module is used for outputting zero temperature coefficient current; the bias current source module is used for finely adjusting the zero temperature coefficient current and outputting the zero temperature coefficient current after fine adjustment; and the oscillator core circuit module is used for charging and discharging the capacitor C by taking the fine-tuned zero temperature coefficient current as a charging and discharging current. According to the invention, the change rate of the current at-40 DEG C to 125 DEG C along with the temperature can be controlled below + / -0.6%.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a relaxation oscillator whose oscillation frequency is independent of temperature. Background Art

[0002] For power supply chips, using an on-chip oscillator to generate a clock signal can replace an external crystal. The relaxation oscillator has the advantages of small size and good on-chip compatibility, and has a wide range of applications. Figure 1 The following shows a simplified schematic diagram of a traditional relaxation oscillator.

[0003] The specific structure of the traditional relaxation oscillator consists of constant current sources IREF1, IREF2, a high-threshold comparator comp1, a low-threshold comparator comp2, a charging switch MP, a discharging switch MN, a charge-discharge capacitor C, an output buffer buffer, and an RS flip-flop. Its specific working principle is that the voltages generated by alternately charging and discharging the capacitor C through the constant current sources I REF1 、I REF2 are compared with the reference thresholds of the two comparators, the high-threshold reference voltage VH and the low-threshold reference voltage VL (VH>VL>0). Finally, the RS flip-flop outputs an oscillating waveform CLK after being shaped by the buffer buffer.

[0004] Working process: The output signals of the RS flip-flop control MP and MN. At the initial moment, Vc = 0, (Vc < VL and Vc < VH), S = 0 and R = 1 of the RS flip-flop, then MP is turned on and MN is turned off, and the capacitor C is charged. The voltage Vc on the capacitor C rises linearly. When Vc > VL, the output of the comparator comp2 flips, R = 0, and the output of the RS flip-flop remains unchanged, and the capacitor C continues to be charged. When Vc > VH, the output of the comparator comp1 flips, S = 1 and R = 0 of the RS flip-flop, then MP is turned off and MN is turned on, and the capacitor C discharges. When Vc < VL, the capacitor is charged. When Vc > VH, the capacitor discharges. When Vc is between VL and VH, the output of the RS flip-flop remains in the previous state. In this way, the capacitor C oscillates back and forth between VL and VH after being powered on, and the output of the RS flip-flop passes through the buffer buffer to output the CLK clock signal.

[0005] In the traditional relaxation oscillator, the oscillator frequency is directly related to the charging and discharging currents IREF1 and IREF2. The temperature characteristics of the charging and discharging currents directly affect the temperature characteristics of the oscillator. The charging and discharging currents provided by an ordinary bias circuit are greatly affected by temperature; the traditional relaxation oscillator structure requires two comparators, which increases a part of the power consumption and area. Summary of the Invention

[0006] The purpose of the present invention is to provide a relaxation oscillator whose oscillation frequency is independent of temperature, and to provide a charge and discharge current I that is independent of temperature through a bias current source module. REF1 , I REF2 , the two comparators of the traditional structure are merged and shared, the RS trigger is eliminated, and an inverter is used instead.

[0007] To achieve the above object, the present invention provides the following solutions:

[0008] A relaxation oscillator with an oscillation frequency independent of temperature, comprising: a reference module, a bias current source module, and an oscillator core circuit module;

[0009] The reference module is used to output a zero temperature coefficient current;

[0010] The bias current source module is used to fine-tune the zero temperature coefficient current and output the fine-tuned zero temperature coefficient current;

[0011] The oscillator core circuit module is used to charge and discharge the capacitor C using the fine-tuned zero temperature coefficient current as the charging and discharging current.

[0012] Optionally, the reference module includes a reference core unit and a first bias unit;

[0013] The reference core unit is used to provide a reference voltage and a bias current;

[0014] The first bias unit is used for coarsely adjusting the bias current, outputting a zero temperature coefficient current, and outputting a limited current to the oscillator core circuit module.

[0015] Optionally, the reference core unit includes a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a second resistor R2, a third resistor R3, and a fourth resistor R4;

[0016] Among them, the thirteenth PMOS transistor MP13, the fourteenth PMOS transistor MP14, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the second resistor R2, the third resistor R3, and the fourth resistor R4, the base of the first transistor T1 is connected to the collector, and is connected to one end of the second resistor R2 and the base of the second transistor T2, the other end of the second resistor R2 is connected to the emitter of the fourth transistor T4, the emitter of the first transistor T1 is grounded, the emitter of the second transistor T2 is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is grounded, the collector of the second transistor T2 is connected to the base of the third transistor T3, and is connected to one end of the third resistor R3 and the second capacitor C CThe other end of the third resistor R3 is connected to the emitter of the fourth transistor T4, the collector of the fourth transistor T4 is connected to the drain and gate of the thirteenth PMOS transistor MP13, and is connected to bias1, and the base of the fourth transistor T4 is connected to the collector of the third transistor T3 and the second capacitor C C The upper plate is connected to the base of the fifth transistor T5 in the first bias unit. The source of the thirteenth PMOS transistor MP13 is connected to the power supply. The gate and drain are interconnected and connected to the gate of the fourteenth PMOS transistor MP14. The source of the fourteenth PMOS transistor MP14 is connected to the power supply, and the drain is connected to the collector of the third transistor T3.

[0017] Optionally, the first bias unit includes a fifth transistor T5, a fifth resistor R5, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a fifteenth PMOS transistor MP15, a ninth transistor T9, an eighth resistor R8, and a twenty-fourth PMOS transistor MP24;

[0018] The emitter of the fifth transistor T5 is connected to the fifth resistor R5, the other end of the fifth resistor R5 is grounded, the collector of the fifth transistor T5 is connected to the gate and drain of the sixteenth PMOS transistor MP16, the gate of the seventeenth PMOS transistor MP17, and bias2, the sources of the sixteenth PMOS transistor MP16 and the seventeenth PMOS transistor MP17 are both connected to the power supply, the drain of the seventeenth PMOS transistor MP17 is connected to the gate and drain of the seventh NMOS transistor MN7, the drain of the eighth NMOS transistor MN8, and bias3, the source of the seventh NMOS transistor MN7 is grounded, the gate of the eighth NMOS transistor MN8 is connected to the gate and drain of the ninth NMOS transistor MN9, the source of the eighth NMOS transistor MN8 is grounded, the source of the ninth NMOS transistor MN9 is grounded, and the source of the ninth NMOS transistor MN9 is grounded. The gate and drain of N9 are connected to the drain of the fifteenth PMOS transistor. The gate of the fifteenth PMOS transistor MP15 is connected to the gates of the thirteenth PMOS transistor MP13 and the fourteenth PMOS transistor MP14, and is connected to bias1. The source of the fifteenth PMOS transistor MP15 is connected to the power supply. One end of the eighth resistor R8 is connected to the ground, and the other end is connected to the emitter of the ninth transistor T9. The base of the ninth transistor T9 is connected to the base of the fifth transistor T5, and is connected to the drain of the fourteenth PMOS transistor MP14 of the reference core unit and the collector of the third transistor T3. The collector of the ninth transistor T9 is connected to the gate and drain of the twenty-fourth PMOS transistor MP24. The source of the twenty-fourth PMOS transistor MP24 is connected to the power supply. The gate and drain of the twenty-fourth PMOS transistor MP24 are connected to the bias4 line.

[0019] Optionally, the bias current source module includes a second bias unit, which includes a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighteenth PMOS transistor MP18, a nineteenth PMOS transistor MP19, a twentieth PMOS transistor MP20, a twenty-first PMOS transistor MP21, a twenty-second PMOS transistor MP22, a twenty-third PMOS transistor MP23, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a sixth resistor R6, a seventh resistor R7, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, and a sixteenth NMOS transistor MN16;

[0020] The gate of the eighteenth PMOS transistor MP18 is connected to the thirteenth PMOS transistor MP13 and the fourteenth PMOS transistor MP14; the gate of the fifteenth PMOS transistor MP15 is bias1; the nineteenth PMOS transistor MP19 is connected to the gates of the sixteenth PMOS transistor MP16 and the seventeenth PMOS transistor MP17 is bias2; the source of the eighteenth PMOS transistor MP18 and the source of the nineteenth PMOS transistor MP19 are both connected to the power supply; the drain of the eighteenth PMOS transistor MP18 and the drain of the nineteenth PMOS transistor MP19 are both connected to the collector and base of the sixth transistor T6; the emitter of the sixth transistor T6 is connected to one end of the sixth resistor R6; the other end of the sixth resistor R6 is grounded; The base and collector of the sixth transistor T6 are connected and connected to the base of the seventh transistor T7. The emitter of the seventh transistor T7 is connected to one end of the seventh resistor R7. The other end of the seventh resistor R7 is grounded. The collector of the seventh transistor T7 is connected to the drain and gate of the 20th PMOS transistor MP20, the gate of the 21st PMOS transistor MP21, the gate of the 22nd PMOS transistor MP22, and the collector and base of the eighth transistor T8. The source of the 20th PMOS transistor MP20 is connected to the power supply. The source of the 21st PMOS transistor MP21 is connected to the power supply. The drain of the 21st PMOS transistor MP21 is connected to the gate and drain of the 12th NMOS transistor MN12. The emitter of the eighth transistor T8 is connected to the 10th The drain of the NMOS transistor MN10 and the drain of the seventh PMOS transistor MP7, the gate of the tenth NMOS transistor MN10 is connected to the gate and drain of the seventh NMOS transistor MN7, the source of the tenth NMOS transistor MN10 is grounded, the gate of the seventh PMOS transistor MP7 is connected to the gate and drain of the eighth PMOS transistor MP8, the source of the seventh PMOS transistor MP7 and the source of the eighth PMOS transistor MP8 are both connected to a high potential, the gate and drain of the eighth PMOS transistor MP8 are connected and connected to the drain of the eleventh NMOS transistor MN11, the source of the eleventh NMOS transistor MN11 is grounded, the gate of the eleventh NMOS transistor MN11 is connected to the gate and drain of the twelfth NMOS transistor MN12, and the gate of the twelfth NMOS transistor MN12 is connected. The source of the NMOS transistor MN12 is grounded, the source of the twenty-second PMOS transistor MP22 is connected to the power supply, and the drain is connected to the gate and drain of the fifteenth NMOS transistor MN15 and the gate of the sixteenth NMOS transistor MN16. The source of the fifteenth NMOS transistor MN15 is connected to the drain and gate of the thirteenth NMOS transistor and the gate of the fourteenth NMOS transistor MN14. The source of the thirteenth NMOS transistor MN13 is grounded, the source of the fourteenth NMOS transistor MN14 is grounded, the drain of the fourteenth NMOS transistor MN14 is connected to the source of the sixteenth NMOS transistor MN16, the drain of the sixteenth NMOS transistor MN16 is connected to the drain and gate of the twenty-third PMOS transistor MP23, and is also connected to the line BIAS.

[0021] Optionally, the oscillator core circuit module includes: a limiter circuit unit, a capacitor charging and discharging unit, and a comparator unit;

[0022] The amplitude limiting circuit unit is used to generate an amplitude limiting voltage according to the amplitude limiting current to limit the oscillation voltage at point Vc;

[0023] The capacitor charging and discharging unit is used to charge and discharge the capacitor C;

[0024] The comparator unit is used to compare the capacitor voltage with the limiting voltage to control the charging and discharging of the capacitor charging and discharging unit.

[0025] Optionally, the amplitude limiting circuit unit includes a first NMOS transistor MN1, a first resistor R1, and a ninth PMOS transistor MP9;

[0026] The gate and drain of the first NMOS transistor MN1 are connected to one end of the first resistor R1, the source of the first NMOS transistor MN1 is grounded, the source of the ninth PMOS transistor MP9 is connected to the power supply, the gate is connected to bias4, and the drain is connected to the other end of the first resistor R1.

[0027] Optionally, the capacitor charging and discharging unit includes a tenth PMOS transistor, a first PMOS transistor, a second PMOS transistor, a second NMOS transistor, and a third NMOS transistor;

[0028] The gate and drain of the second NMOS transistor MN2 are connected and connected to the gate of the third NMOS transistor MN3. The source of the second NMOS transistor MN2 and the source of the third NMOS transistor MN3 are grounded. The gate and drain of the second NMOS transistor MN2 are connected to the drain of the first PMOS transistor MP1. The drain of the third NMOS transistor MN3 is connected to the drain of the second PMOS transistor MP2 and to the upper plate of the first capacitor C. The lower plate of the first capacitor C is grounded. The gate of the first PMOS transistor MP1 is connected to the output of the first inverter INV1 of the comparator unit. The gate of the second PMOS transistor MP2 is connected to the output of the second inverter INV2 of the comparator unit. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the drain of the tenth PMOS transistor MP10. The gate of the tenth PMOS transistor is connected to BIAS and the source is connected to a power supply, thereby forming a capacitor charging and discharging unit.

[0029] Optionally, the comparator unit includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eleventh PMOS transistor MO11, a twelfth PMOS transistor MP12, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6;

[0030] The gate of the fourth NMOS transistor MP4 is connected to the gate of the fifth NMOS transistor MP5. The source of the fourth NMOS transistor MP4 and the source of the fifth NMOS transistor MP5 are both grounded. The drain of the fourth NMOS transistor MN4 is connected to the drain of the third PMOS transistor MP3, the drain of the fourth PMOS transistor MP4, and the gate of the sixth NMOS transistor MN6. The gate and drain of the fifth NMOS transistor MN5 are connected, and are also connected to the drain of the fifth PMOS transistor MP5 and the drain of the sixth PMOS transistor MP6. The gate of the third PMOS transistor MP3 is connected to the upper plate of the first capacitor, and the source is connected to the drain of the seventh PMOS transistor MP7. The gate of the fifth PMOS transistor MP5 is connected to the drain of the ninth PMOS transistor, and the source is connected to the drain of the seventh PMOS transistor MP7. The source of the seventh PMOS transistor MP7 is connected to the drain of the eleventh PMOS transistor MP11, and the gate is connected to the output of the second inverter. The source of the eleventh PMOS transistor MP11 is connected to the power supply, and the gate of the eleventh PMOS transistor MP11 is connected to the power supply. BIAS, the gate of the fourth PMOS transistor MP4 is connected to the upper plate of the first capacitor, the gate of the sixth PMOS transistor MP6 is connected to the gate and drain of the first NMOS transistor, the sources of the fourth PMOS transistor MP4 and the sixth PMOS transistor MP6 are connected to the drain of the eighth PMOS transistor MP8, the gate of the eighth PMOS transistor MP8 is connected to the output of the first inverter, the source of the eighth PMOS transistor MP8 is connected to the drain of the eleventh PMOS transistor MP11, the gate of the sixth NMOS transistor MN6 is connected to the drain of the fourth NMOS transistor MN4, the source is grounded, and the drain is connected to the input of the first inverter and to the drain of the twelfth PMOS transistor MP12, the gate of the twelfth PMOS transistor MP12 is connected to BIAS, and the source is connected to the power supply, the output of the first inverter is connected to the input of the second inverter, and to the gates of the first PMOS transistor MP1 and the eighth PMOS transistor MP8, and the output of the second inverter is connected to the gates of the second PMOS transistor MP2 and the seventh PMOS transistor MP7.

[0031] The beneficial effects of the present invention are as follows: the present invention can control the rate of change of current with temperature to below ±0.6% at -40°C to 125°C, and this bias current can also be provided to other modules of the chip to achieve good temperature characteristics of the entire chip.

[0032] The present invention can achieve control of the central oscillation frequency range of the oscillator within 100K±1K, i.e., within ±1%, at a temperature of -40°C to 125°C. The main error comes from the temperature characteristics of the capacitor and the temperature characteristics of the limiter circuit unit. The limiter circuit unit also has a certain adjustment space, and the temperature characteristics of the oscillator can be further optimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 A circuit diagram of a conventional relaxation oscillator according to an embodiment of the present invention;

[0035] Figure 2 This is a circuit structure diagram of a reference module according to an embodiment of the present invention;

[0036] Figure 3 This is a diagram showing the core circuit structure of a relaxation oscillator according to an embodiment of the present invention;

[0037] Figure 4 FIG1 is a circuit structure diagram of a second bias unit according to an embodiment of the present invention;

[0038] Figure 5 A block diagram of the working principle of a relaxation oscillator according to an embodiment of the present invention;

[0039] Figure 6 Schematic diagram of fine-tuning current of the second bias unit according to an embodiment of the present invention;

[0040] Figure 7 Schematic diagram of a relaxation oscillator according to an embodiment of the present invention;

[0041] Figure 8 FIG. 4 is a schematic diagram of a coarse adjustment current of a first bias unit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0043] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] This embodiment provides a relaxation oscillator whose oscillation frequency is independent of temperature, comprising: a reference module, a bias current source module, and an oscillator core circuit module;

[0045] A reference module for outputting a zero temperature coefficient current;

[0046] A bias current source module is used to fine-tune the zero temperature coefficient current and output the zero temperature coefficient current after fine-tuning;

[0047] The oscillator core circuit module is used to use the zero temperature coefficient current after fine-tuning as the charging and discharging current for charging and discharging.

[0048] Furthermore, the reference module includes a reference core unit and a first bias unit; the reference core unit is used to provide a reference voltage for the first bias unit and a bias current for the first bias unit; the first bias unit is used to coarsely adjust the bias current, output a zero temperature coefficient current, and provide a limiting current for the oscillator core circuit module.

[0049] like Figure 2 As shown, the reference module includes: a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a first triode T1, a second triode T2, a third triode T3, a fourth triode T4, a fifth triode T5, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a second capacitor Cc.

[0050] Furthermore, the reference core unit includes a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a second resistor R2, a third resistor R3, and a fourth resistor R4. The base of the first transistor T1 is connected to the collector and is connected to one end of the second resistor R2 and the base of the second transistor T2. The other end of the second resistor R2 is connected to the emitter of the fourth transistor T4. The emitter of the first transistor T1 is grounded. The emitter of the second transistor T2 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is grounded. The collector of the second transistor T2 is connected to the base of the third transistor T3 and is connected to one end of the third resistor R3 and the second capacitor C. C The other end of the third resistor R3 is connected to the emitter of the fourth transistor T4, the collector of the fourth transistor T4 is connected to the drain and gate of the thirteenth PMOS transistor MP13, and is connected to bias1, and the base of the fourth transistor T4 is connected to the collector of the third transistor T3 and the second capacitor C C The upper plate is connected to the base of the fifth transistor T5 in the first bias unit, the source of the thirteenth PMOS transistor MP13 is connected to the power supply, the gate and drain are interconnected and connected to the gate of the fourteenth PMOS transistor MP14, the source of the fourteenth PMOS transistor MP14 is connected to the power supply, and the drain is connected to the collector of the third transistor T3, forming a reference core circuit.

[0051] The first bias unit includes a fifth transistor T5, a fifth resistor R5, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a fifteenth PMOS transistor MP15, a ninth transistor T9, an eighth resistor R8, and a twenty-fourth PMOS transistor MP24. The emitter of the fifth transistor T5 is connected to the fifth resistor R5, the other end of the fifth resistor R5 is grounded, the collector of the fifth transistor T5 is connected to the gate and drain of the sixteenth PMOS transistor MP16, the gate of the seventeenth PMOS transistor MP17, and bias2, the sources of the sixteenth PMOS transistor MP16 and the seventeenth PMOS transistor MP17 are both connected to the power supply, the drain of the seventeenth PMOS transistor MP17 is connected to the gate and drain of the seventh NMOS transistor MN7, the drain of the eighth NMOS transistor MN8, and bias3, the source of the seventh NMOS transistor MN7 is grounded, the gate of the eighth NMOS transistor MN8 is connected to the gate and drain of the ninth NMOS transistor MN9, the source of the eighth NMOS transistor MN8 is grounded, the source of the ninth NMOS transistor MN9 is grounded, and the source of the ninth NMOS transistor MN9 is grounded. The gate and drain of MN9 are connected to the drain of the fifteenth PMOS transistor. The gate of the fifteenth PMOS transistor MP15 is connected to the gates of the thirteenth PMOS transistor MP13 and the fourteenth PMOS transistor MP14, and is connected to bias1. The source of the fifteenth PMOS transistor MP15 is connected to the power supply. One end of the eighth resistor R8 is connected to the ground, and the other end is connected to the emitter of the ninth transistor T9. The base of the ninth transistor T9 is connected to the base of the fifth transistor T5, and is connected to the drain of the fourteenth PMOS transistor MP14 of the reference core unit and the collector of the third transistor T3. The collector of the ninth transistor T9 is connected to the gate and drain of the twenty-fourth PMOS transistor MP24. The source of the twenty-fourth PMOS transistor MP24 is connected to the power supply. The gate and drain of the twenty-fourth PMOS transistor MP24 are connected to the bias4 line.

[0052] Further, such as Figure 4 As shown, the bias current source module includes a second bias unit, and the second bias unit is used to fine-tune the bias current.

[0053] The second bias unit includes a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighteenth PMOS transistor MP18, a nineteenth PMOS transistor MP19, a twentieth PMOS transistor MP20, a twenty-first PMOS transistor MP21, a twenty-second PMOS transistor MP22, a twenty-third PMOS transistor MP23, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a sixth resistor R6, a seventh resistor R7, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, and a sixteenth NMOS transistor MN16.The gate of the eighteenth PMOS transistor MP18 is connected to the thirteenth PMOS transistor MP13 and the fourteenth PMOS transistor MP14. The gate of the fifteenth PMOS transistor MP15 is bias1. The nineteenth PMOS transistor MP19 is connected to the gates of the sixteenth PMOS transistor MP16 and the seventeenth PMOS transistor MP17, bias2. The source of the eighteenth PMOS transistor MP18 and the source of the nineteenth PMOS transistor MP19 are both connected to the power supply. The drain of the eighteenth PMOS transistor MP18 and the drain of the nineteenth PMOS transistor MP19 are both connected to the collector and base of the sixth transistor T6. The emitter of the sixth transistor T6 is connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is grounded. The base and collector of the transistor T6 are connected to each other and are also connected to the base of the seventh transistor T7. The emitter of the seventh transistor T7 is connected to one end of the seventh resistor R7, and the other end of the seventh resistor R7 is grounded. The collector of the seventh transistor T7 is connected to the drain and gate of the 20th PMOS transistor MP20, the gate of the 21st PMOS transistor MP21, the gate of the 22nd PMOS transistor MP22, and the collector and base of the eighth transistor T8. The source of the 20th PMOS transistor MP20 is connected to the power supply, the source of the 21st PMOS transistor MP21 is connected to the power supply, the drain of the 21st PMOS transistor MP21 is connected to the gate and drain of the 12th NMOS transistor MN12, and the emitter of the eighth transistor T8 is connected to the 10th NMOS transistor MN12. The drain of the OS transistor MN10 and the drain of the seventh PMOS transistor MP7, the gate of the tenth NMOS transistor MN10 is connected to the gate and drain of the seventh NMOS transistor MN7, the source of the tenth NMOS transistor MN10 is grounded, the gate of the seventh PMOS transistor MP7 is connected to the gate and drain of the eighth PMOS transistor MP8, the source of the seventh PMOS transistor MP7 and the source of the eighth PMOS transistor MP8 are both connected to a high potential, the gate and drain of the eighth PMOS transistor MP8 are connected and connected to the drain of the eleventh NMOS transistor MN11, the source of the eleventh NMOS transistor MN11 is grounded, the gate of the eleventh NMOS transistor MN11 is connected to the gate and drain of the twelfth NMOS transistor MN12, and the twelfth NMOS transistor MN12 is connected. The source of the OS transistor MN12 is grounded. The source of the twenty-second PMOS transistor MP22 is connected to the power supply, and the drain is connected to the gate and drain of the fifteenth NMOS transistor MN15 and the gate of the sixteenth NMOS transistor MN16. The source of the fifteenth NMOS transistor MN15 is connected to the drain and gate of the thirteenth NMOS transistor and the gate of the fourteenth NMOS transistor MN14. The source of the thirteenth NMOS transistor MN13 is grounded. The source of the fourteenth NMOS transistor MN14 is grounded. The drain of the fourteenth NMOS transistor MN14 is connected to the source of the sixteenth NMOS transistor MN16. The drain of the sixteenth NMOS transistor MN16 is connected to the drain and gate of the twenty-third PMOS transistor MP23 and connected to the BIAS line.

[0054] Further, such as Figure 3As shown, the oscillator core circuit module includes a limiting circuit unit, a capacitor charging and discharging unit, and a comparator unit.

[0055] The limiting circuit unit is used to provide a limiting voltage for the capacitor charge and discharge unit according to the limiting current, thereby limiting the magnitude of the oscillation voltage at the Vc point of the oscillator core circuit. The capacitor charge and discharge unit is used to charge and discharge the capacitor C. The comparator unit is used to compare the capacitor voltage with the limiting voltage to control the charging and discharging of the capacitor charge and discharge unit.

[0056] The oscillator core module includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a first resistor R1, a first capacitor C, a first inverter INV1, and a second inverter INV2.

[0057] The limiting circuit unit includes a first NMOS transistor MN1, a first resistor R1, and a ninth PMOS transistor MP9. The gate and drain of the first NMOS transistor MN1 are connected to the first resistor R1, and the source is grounded. The source of the ninth PMOS transistor MP9 is connected to the power supply, the gate is connected to bias4, and the drain is connected to the other end of the first resistor R1, forming the limiting circuit unit.

[0058] The capacitor charging and discharging unit includes a tenth PMOS transistor MP10, a first PMOS transistor MP1, a second PMOS transistor MP2, a second NMOS transistor MN2, and a third NMOS transistor MN3. The gate and drain of the second NMOS transistor MN2 are connected and connected to the gate of the third NMOS transistor MN3. The source of the second NMOS transistor MN2 and the source of the third NMOS transistor MN3 are grounded. The gate and drain of the second NMOS transistor MN2 are connected to the drain of the first PMOS transistor MP1. The drain of the third NMOS transistor MN3 is connected to the drain of the second PMOS transistor MP2 and to the upper plate of the first capacitor C. The lower plate of the first capacitor C is grounded. The gate of the first PMOS transistor MP1 is connected to the output of the first inverter INV1 of the comparator unit. The gate of the second PMOS transistor MP2 is connected to the output of the second inverter INV2 of the comparator unit. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the drain of the tenth PMOS transistor MP10. The gate of the tenth PMOS transistor is connected to BIAS, and the source is connected to the power supply, thereby forming the capacitor charging and discharging unit.

[0059] The comparator unit includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eleventh PMOS transistor MO11, a twelfth PMOS transistor MP12, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6. The gate of the fourth NMOS transistor MP4 is connected to the gate of the fifth NMOS transistor MP5, the source of the fourth NMOS transistor MP4 and the source of the fifth NMOS transistor MP5 are both grounded, the drain of the fourth NMOS transistor MN4 is connected to the drain of the third PMOS transistor MP3, the drain of the fourth PMOS transistor MP4, and the gate of the sixth NMOS transistor MN6, the gate and drain of the fifth NMOS transistor MN5 are connected, and are connected to the drain of the fifth PMOS transistor MP5 and the drain of the sixth PMOS transistor MP6, the gate of the third PMOS transistor MP3 is connected to the upper plate of the first capacitor, and the source is connected to the drain of the seventh PMOS transistor MP7, the gate of the fifth PMOS transistor MP5 is connected to the drain of the ninth PMOS transistor, and the source is connected to the The drain of the seventh PMOS transistor MP7, the source of the seventh PMOS transistor MP7 is connected to the drain of the eleventh PMOS transistor MP11, and the gate is connected to the output of the second inverter. The source of the eleventh PMOS transistor MP11 is connected to the power supply. The gate of the eleventh PMOS transistor MP11 is connected to BIAS. The gate of the fourth PMOS transistor MP4 is connected to the upper plate of the first capacitor. The gate of the sixth PMOS transistor MP6 is connected to the gate and drain of the first NMOS transistor. The sources of the fourth PMOS transistor MP4 and the sixth PMOS transistor MP6 are connected to the drain of the eighth PMOS transistor MP8. The gate of the eighth PMOS transistor MP8 is connected to the output of the first inverter. The source of the eighth PMOS transistor MP8 is connected to the drain of the eleventh PMOS transistor MP11. The gate of the sixth NMOS transistor MN6 is connected to the drain of the fourth NMOS transistor MN4, the source is grounded, the drain is connected to the input of the first inverter, and is also connected to the drain of the twelfth PMOS transistor MP12. The gate of the twelfth PMOS transistor MP12 is connected to BIAS, and the source is connected to the power supply. The output of the first inverter is connected to the input of the second inverter and is connected to the gates of the first PMOS transistor MP1 and the eighth PMOS transistor MP8. The output of the second inverter is connected to the gates of the second PMOS transistor MP2 and the seventh PMOS transistor MP7. This constitutes a comparator unit.

[0060] like Figure 2 As shown, when the reference core unit is working normally, the voltage at point A is equal to the voltage at point B, and the ratio of T1 to T2 is 1:n. By adjusting the ratio of R3 and R4, point D can be adjusted to the zero temperature drift point, that is, Vref.

[0061] The voltage at point E is Vref+Vbe T4, the current flowing through R5 is:

[0062]

[0063] a is the ratio of the width to length of MP15 to MP13, and the current flowing through MP15 is:

[0064]

[0065] b is the ratio of the width to length ratio of MP17 to MP16, and c is the ratio of the width to length ratio of MN8 to MN9.

[0066] Then the current flowing through MN7 is:

[0067]

[0068] The conduction voltage drop of transistor T4 is:

[0069]

[0070] The conduction voltage drop of transistor T5 is:

[0071]

[0072] R0 is the resistance of the resistor at temperature T0, and the temperature characteristic formula of the resistor value is (the second-order temperature characteristic of the resistor is not considered for the time being):

[0073] R(T)=R0(1+α(T-T0)) (6)

[0074] The combined formula 123456 can be simplified to:

[0075]

[0076] make Derivative of the above formula with respect to temperature:

[0077]

[0078] Let equation (8) be 0, and we can solve it:

[0079]

[0080] The solution does not include the temperature variable T, and the solution is relatively complex. The resistance ratio can be determined by simulation scanning. The rough adjustment result is as follows Figure 8 shown.

[0081] In order to make the solution positive, both R5 and R4 need to be negative temperature coefficient resistors.

[0082] Then by adjusting the proportional relationship between R5 and R4 at temperature T0, the current flowing through MN7 can be roughly adjusted to a zero temperature coefficient current, as shown in the schematic diagram. Figure 8 As shown, I MP17 is the PTAT current flowing through MP17, I MN8 is the PTAT current flowing through MN8. The first bias unit is set so that the slopes of the two PTAT currents are the same. They can be subtracted to obtain a current with zero temperature coefficient I MN7 .

[0083] The current flowing through MN7 is copied to MN10 through the current mirror. The temperature coefficient of the copied current still has room for optimization, so the second bias unit can be used to fine-tune the current to further optimize the temperature characteristics of the current.

[0084] Assume that the ratio of the width to length of MN10 to MN7 is d.

[0085] Through the current mirror replication effect of MP7, MP8, MN11, MN12, MP20, and MP21, it can be deduced that the current flowing through MP20 is: e is the ratio of the current flowing through MP20 to the sum of the currents flowing through T7 and MN10.

[0086] f is the ratio of the current flowing through MP18 to the current flowing through MP13, g is the ratio of the current flowing through MP19 to the current flowing through MP16, then:

[0087]

[0088] The above analysis shows that:

[0089]

[0090] I T6 Obviously it is a PTAT current, so Equation 10 is expressed as:

[0091]

[0092] In formula 12, The term can be regarded as a PTAT current with adjustable size. The term is a function related to temperature. In a preferred embodiment of the present invention, R7 and R6 need to use resistors with the same temperature coefficient. The resistance value of R7 and R6 can be adjusted to adjust I T7 The current can be adjusted by increasing the number of T7 in parallel. T7 The slope of the current versus temperature. R7 uses a large resistor to T7 Adjusting to a low current can fine-tune the MP18's current versus temperature curve.

[0093] Then the current flowing through MP18 is:

[0094]

[0095] I can easily MP18 Adjust to zero temperature drift current to provide the relaxation oscillator with charge and discharge current, as shown in the following example: Figure 6 As shown, the dotted line represents the ideal current curve, and the solid line represents the actual current curve, I T8 is the current flowing through transistor T8, I T7 is the current flowing through transistor T7, and the second bias unit outputs the current I T8 Based on this, a very small PTAT current I T7 , so that the output current I MP18 The temperature coefficient is better.

[0096] like Figure 3 As shown in , when the chip is just powered on and the capacitor C is not charged, that is, when the potential at point Vc is 0, MP3 and MP4 are turned on. Since signal A and signal AN are inverse signals, one of them must be able to turn on MP7 and MP8. Since the potential at point Vc is lower than both Vref2 and Vref1 in the initial state, current flows through MP4 or MP3. At this time, MP5 and MP6 are turned off, so MN5 and MN4 are turned off, and the gate potential of MN6 is pulled high, so that MN6 is turned on, and the potential at point E is pulled down. Then the output A=1, AN=0, the five tubes OTA where MP3 and MP5 are located work, and at the same time, the capacitor charging and discharging unit MP2 is turned on, and the bias current source charges the capacitor C.

[0097] Capacitor C is continuously charged, and the potential of point C on the upper plate of the capacitor rises to close to Vref1. Since A=1 and AN=0, MP7 is turned on and MP8 is turned off. The current mainly flows through MP5, and the five-transistor OTA composed of MP5, MP4, MN3, MN4, and MP11 works. The potential at point C exceeds Vref1, and the output of the five-transistor OTA flips, causing MN6 to turn off and the potential at point E to rise. Then the output A=0 and AN=1, and the bias current discharges capacitor C through MN3.

[0098] Capacitor C discharges, and the potential of point C on the upper plate of the capacitor drops to close to Vref2. Since A=0 and AN=1, MP8 is turned on and MP7 is turned off. The current flows through MP6, and the five-transistor OTA composed of MP6, MP4, MN3, and MN4 works. When the potential at point C is lower than Vref1, the output of the five-transistor OTA flips, causing MN6 to turn on, and then outputs A=1 and AN=0, causing the capacitor charging and discharging unit MP2 to turn on, and the bias current charges the capacitor, and so on.

[0099] In a preferred embodiment of the present invention, the first resistor R1 in the amplitude limiting circuit unit and the eighth resistor R8 in the first bias unit need to be resistors of the same type and have the same temperature coefficient.

[0100] in:

[0101]

[0102] in:

[0103]

[0104] The clipping amplitude is:

[0105]

[0106] Capacitor charging time:

[0107]

[0108] Capacitor discharge time:

[0109]

[0110] The oscillation frequency is:

[0111]

[0112] Where I1 is the charging current, I2 is the discharging current, and the capacitance is C. From the above analysis, we can know that the oscillation frequency of the oscillator mainly depends on the size of the capacitance C, the size of the charging and discharging current I, and the voltage amplitude difference between Vref1 and Vref2.

[0113] The overall structure of the present invention is as follows Figure 5 As shown, the reference core unit provides a reference voltage Vref for the first bias unit; the first bias unit roughly adjusts the current to generate a zero temperature coefficient current, which enters the second bias unit, and the first bias unit provides a limiting current for the oscillator core; the second bias unit fine-tunes the current input by the first bias unit to generate a zero temperature coefficient current with a better temperature coefficient. Figure 7 As shown, in the present invention, comp1 and comp2 of the traditional relaxation oscillator are merged, and the RS trigger is replaced by MN6, which saves the number of transistors and simplifies the circuit structure.

[0114] The embodiments described above are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by persons skilled in the art should fall within the scope of protection defined by the claims of the present invention.

Claims

1. A relaxation oscillator whose oscillation frequency is independent of temperature, characterized in that: include: Reference module, bias current source module, oscillator core circuit module; The reference module is used to output a zero temperature coefficient current; The bias current source module is used to fine-tune the zero temperature coefficient current and output the fine-tuned zero temperature coefficient current; The oscillator core circuit module is used to charge and discharge the capacitor C using the fine-tuned zero temperature coefficient current as the charging and discharging current.

2. The relaxation oscillator with an oscillation frequency independent of temperature according to claim 1, characterized in that: The reference module includes a reference core unit and a first bias unit; The reference core unit is used to provide a reference voltage and a bias current; The first bias unit is used for coarsely adjusting the bias current, outputting a zero temperature coefficient current, and outputting a limited current to the oscillator core circuit module.

3. The relaxation oscillator with an oscillation frequency independent of temperature according to claim 2, characterized in that: The reference core unit includes a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a second resistor R2, a third resistor R3, and a fourth resistor R4; Among them, the thirteenth PMOS transistor MP13, the fourteenth PMOS transistor MP14, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the second resistor R2, the third resistor R3, and the fourth resistor R4, the base of the first transistor T1 is connected to the collector, and is connected to one end of the second resistor R2 and the base of the second transistor T2, the other end of the second resistor R2 is connected to the emitter of the fourth transistor T4, the emitter of the first transistor T1 is grounded, the emitter of the second transistor T2 is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is grounded, the collector of the second transistor T2 is connected to the base of the third transistor T3, and is connected to one end of the third resistor R3 and the second capacitor C C The other end of the third resistor R3 is connected to the emitter of the fourth transistor T4, the collector of the fourth transistor T4 is connected to the drain and gate of the thirteenth PMOS transistor MP13, and is connected to bias1, and the base of the fourth transistor T4 is connected to the collector of the third transistor T3 and the second capacitor C C The upper plate is connected to the base of the fifth transistor T5 in the first bias unit. The source of the thirteenth PMOS transistor MP13 is connected to the power supply. The gate and drain are interconnected and connected to the gate of the fourteenth PMOS transistor MP14. The source of the fourteenth PMOS transistor MP14 is connected to the power supply, and the drain is connected to the collector of the third transistor T3.

4. The relaxation oscillator with an oscillation frequency independent of temperature according to claim 3, characterized in that: The first bias unit includes a fifth transistor T5, a fifth resistor R5, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a fifteenth PMOS transistor MP15, a ninth transistor T9, an eighth resistor R8, and a twenty-fourth PMOS transistor MP24; The emitter of the fifth transistor T5 is connected to the fifth resistor R5, the other end of the fifth resistor R5 is grounded, the collector of the fifth transistor T5 is connected to the gate and drain of the sixteenth PMOS transistor MP16, the gate of the seventeenth PMOS transistor MP17, and bias2, the sources of the sixteenth PMOS transistor MP16 and the seventeenth PMOS transistor MP17 are both connected to the power supply, the drain of the seventeenth PMOS transistor MP17 is connected to the gate and drain of the seventh NMOS transistor MN7, the drain of the eighth NMOS transistor MN8, and bias3, the source of the seventh NMOS transistor MN7 is grounded, the gate of the eighth NMOS transistor MN8 is connected to the gate and drain of the ninth NMOS transistor MN9, the source of the eighth NMOS transistor MN8 is grounded, the source of the ninth NMOS transistor MN9 is grounded, and the source of the ninth NMOS transistor MN9 is grounded. The gate and drain of N9 are connected to the drain of the fifteenth PMOS transistor. The gate of the fifteenth PMOS transistor MP15 is connected to the gates of the thirteenth PMOS transistor MP13 and the fourteenth PMOS transistor MP14, and is connected to bias1. The source of the fifteenth PMOS transistor MP15 is connected to the power supply. One end of the eighth resistor R8 is connected to the ground, and the other end is connected to the emitter of the ninth transistor T9. The base of the ninth transistor T9 is connected to the base of the fifth transistor T5, and is connected to the drain of the fourteenth PMOS transistor MP14 of the reference core unit and the collector of the third transistor T3. The collector of the ninth transistor T9 is connected to the gate and drain of the twenty-fourth PMOS transistor MP24. The source of the twenty-fourth PMOS transistor MP24 is connected to the power supply. The gate and drain of the twenty-fourth PMOS transistor MP24 are connected to the bias4 line.

5. The relaxation oscillator with an oscillation frequency independent of temperature according to claim 4, characterized in that: The bias current source module includes a second bias unit, which includes a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighteenth PMOS transistor MP18, a nineteenth PMOS transistor MP19, a twentieth PMOS transistor MP20, a twenty-first PMOS transistor MP21, a twenty-second PMOS transistor MP22, a twenty-third PMOS transistor MP23, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a sixth resistor R6, a seventh resistor R7, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, and a sixteenth NMOS transistor MN16; The gate of the eighteenth PMOS transistor MP18 is connected to the thirteenth PMOS transistor MP13 and the fourteenth PMOS transistor MP14; the gate of the fifteenth PMOS transistor MP15 is bias1; the nineteenth PMOS transistor MP19 is connected to the gates of the sixteenth PMOS transistor MP16 and the seventeenth PMOS transistor MP17 is bias2; the source of the eighteenth PMOS transistor MP18 and the source of the nineteenth PMOS transistor MP19 are both connected to the power supply; the drain of the eighteenth PMOS transistor MP18 and the drain of the nineteenth PMOS transistor MP19 are both connected to the collector and base of the sixth transistor T6; the emitter of the sixth transistor T6 is connected to one end of the sixth resistor R6; the other end of the sixth resistor R6 is grounded; The base and collector of the sixth transistor T6 are connected and connected to the base of the seventh transistor T7. The emitter of the seventh transistor T7 is connected to one end of the seventh resistor R7. The other end of the seventh resistor R7 is grounded. The collector of the seventh transistor T7 is connected to the drain and gate of the 20th PMOS transistor MP20, the gate of the 21st PMOS transistor MP21, the gate of the 22nd PMOS transistor MP22, and the collector and base of the eighth transistor T8. The source of the 20th PMOS transistor MP20 is connected to the power supply. The source of the 21st PMOS transistor MP21 is connected to the power supply. The drain of the 21st PMOS transistor MP21 is connected to the gate and drain of the 12th NMOS transistor MN12. The emitter of the eighth transistor T8 is connected to the 10th The drain of the NMOS transistor MN10 and the drain of the seventh PMOS transistor MP7, the gate of the tenth NMOS transistor MN10 is connected to the gate and drain of the seventh NMOS transistor MN7, the source of the tenth NMOS transistor MN10 is grounded, the gate of the seventh PMOS transistor MP7 is connected to the gate and drain of the eighth PMOS transistor MP8, the source of the seventh PMOS transistor MP7 and the source of the eighth PMOS transistor MP8 are both connected to a high potential, the gate and drain of the eighth PMOS transistor MP8 are connected and connected to the drain of the eleventh NMOS transistor MN11, the source of the eleventh NMOS transistor MN11 is grounded, the gate of the eleventh NMOS transistor MN11 is connected to the gate and drain of the twelfth NMOS transistor MN12, and the gate of the twelfth NMOS transistor MN12 is connected. The source of the NMOS transistor MN12 is grounded, the source of the twenty-second PMOS transistor MP22 is connected to the power supply, and the drain is connected to the gate and drain of the fifteenth NMOS transistor MN15 and the gate of the sixteenth NMOS transistor MN16. The source of the fifteenth NMOS transistor MN15 is connected to the drain and gate of the thirteenth NMOS transistor and the gate of the fourteenth NMOS transistor MN14. The source of the thirteenth NMOS transistor MN13 is grounded, the source of the fourteenth NMOS transistor MN14 is grounded, the drain of the fourteenth NMOS transistor MN14 is connected to the source of the sixteenth NMOS transistor MN16, the drain of the sixteenth NMOS transistor MN16 is connected to the drain and gate of the twenty-third PMOS transistor MP23, and is also connected to the line BIAS.

6. The relaxation oscillator with an oscillation frequency independent of temperature according to claim 2, characterized in that: The oscillator core circuit module includes: a limiter circuit unit, a capacitor charging and discharging unit, and a comparator unit; The amplitude limiting circuit unit is used to generate an amplitude limiting voltage according to the amplitude limiting current to limit the oscillation voltage at point Vc; The capacitor charging and discharging unit is used to charge and discharge the capacitor C; The comparator unit is used to compare the capacitor voltage with the limiting voltage to control the charging and discharging of the capacitor charging and discharging unit.

7. The relaxation oscillator with an oscillation frequency independent of temperature according to claim 6, characterized in that: The amplitude limiting circuit unit includes a first NMOS transistor MN1, a first resistor R1, and a ninth PMOS transistor MP9; The gate and drain of the first NMOS transistor MN1 are connected to one end of the first resistor R1, the source of the first NMOS transistor MN1 is grounded, the source of the ninth PMOS transistor MP9 is connected to the power supply, the gate is connected to bias4, and the drain is connected to the other end of the first resistor R1.

8. The relaxation oscillator with an oscillation frequency independent of temperature according to claim 7, characterized in that: The capacitor charging and discharging unit includes a tenth PMOS transistor, a first PMOS transistor, a second PMOS transistor, a second NMOS transistor, and a third NMOS transistor; The gate and drain of the second NMOS transistor MN2 are connected and connected to the gate of the third NMOS transistor MN3. The source of the second NMOS transistor MN2 and the source of the third NMOS transistor MN3 are grounded. The gate and drain of the second NMOS transistor MN2 are connected to the drain of the first PMOS transistor MP1. The drain of the third NMOS transistor MN3 is connected to the drain of the second PMOS transistor MP2 and to the upper plate of the first capacitor C. The lower plate of the first capacitor C is grounded. The gate of the first PMOS transistor MP1 is connected to the output of the first inverter INV1 of the comparator unit. The gate of the second PMOS transistor MP2 is connected to the output of the second inverter INV2 of the comparator unit. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the drain of the tenth PMOS transistor MP10. The gate of the tenth PMOS transistor is connected to BIAS and the source is connected to a power supply, thereby forming a capacitor charging and discharging unit.

9. The relaxation oscillator with an oscillation frequency independent of temperature according to claim 8, characterized in that: The comparator unit includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eleventh PMOS transistor MO11, a twelfth PMOS transistor MP12, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6; The gate of the fourth NMOS transistor MP4 is connected to the gate of the fifth NMOS transistor MP5. The source of the fourth NMOS transistor MP4 and the source of the fifth NMOS transistor MP5 are both grounded. The drain of the fourth NMOS transistor MN4 is connected to the drain of the third PMOS transistor MP3, the drain of the fourth PMOS transistor MP4, and the gate of the sixth NMOS transistor MN6. The gate and drain of the fifth NMOS transistor MN5 are connected, and are also connected to the drain of the fifth PMOS transistor MP5 and the drain of the sixth PMOS transistor MP6. The gate of the third PMOS transistor MP3 is connected to the upper plate of the first capacitor, and the source is connected to the drain of the seventh PMOS transistor MP7. The gate of the fifth PMOS transistor MP5 is connected to the drain of the ninth PMOS transistor, and the source is connected to the drain of the seventh PMOS transistor MP7. The source of the seventh PMOS transistor MP7 is connected to the drain of the eleventh PMOS transistor MP11, and the gate is connected to the output of the second inverter. The source of the eleventh PMOS transistor MP11 is connected to the power supply, and the gate of the eleventh PMOS transistor MP11 is connected to the power supply. BIAS, the gate of the fourth PMOS transistor MP4 is connected to the upper plate of the first capacitor, the gate of the sixth PMOS transistor MP6 is connected to the gate and drain of the first NMOS transistor, the sources of the fourth PMOS transistor MP4 and the sixth PMOS transistor MP6 are connected to the drain of the eighth PMOS transistor MP8, the gate of the eighth PMOS transistor MP8 is connected to the output of the first inverter, the source of the eighth PMOS transistor MP8 is connected to the drain of the eleventh PMOS transistor MP11, the gate of the sixth NMOS transistor MN6 is connected to the drain of the fourth NMOS transistor MN4, the source is grounded, and the drain is connected to the input of the first inverter and to the drain of the twelfth PMOS transistor MP12, the gate of the twelfth PMOS transistor MP12 is connected to BIAS, and the source is connected to the power supply, the output of the first inverter is connected to the input of the second inverter, and to the gates of the first PMOS transistor MP1 and the eighth PMOS transistor MP8, and the output of the second inverter is connected to the gates of the second PMOS transistor MP2 and the seventh PMOS transistor MP7.

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