3D packaged low parasitic inductance SiC power module

Abstract

The invention discloses a 3D packaged low parasitic inductance SiC power module, which comprises a substrate layer, a chip layer, a connecting layer, a middle layer and a decoupling capacitor, the chip layer is electrically connected with the substrate layer; the middle layer is located between the upper chip layer and the lower chip layer, and the upper connecting layer and the lower connecting layer are windowing type copper blocks, are externally connected with DC terminals and are used for connecting the upper substrate layer and the decoupling capacitor; and the decoupling capacitors are two groups of capacitors arranged beside the middle layer and are electrically connected with the upper connecting layer and the lower connecting layer. By adopting the copper material with high conductivity to be connected with the copper layers in the laminated layer and the substrate to form the middle layer, the inductance of the machine body is obviously reduced, the heat dissipation effect is improved, the machine body has obvious advantages in high-frequency, high-voltage and high-power applications, and the overall performance and reliability of a power electronic system can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a 3D packaged low parasitic inductance SiC power module. Background Art

[0002] SiC power modules are currently widely used in the power electronics field. Their system architecture typically includes the chip, substrate, interconnects, and package. The chip is responsible for power conversion, the substrate provides mechanical support and electrical connections, the interconnects connect the chip to the substrate, decoupling capacitors reduce overshoot voltage during chip switching, buffer blocks reduce thermal stress between connection surfaces, and extend module life, while the package provides protection. In terms of algorithms, traditional electromagnetic field simulation algorithms are primarily used to predict and optimize module performance.

[0003] CN107170714A discloses a low parasitic inductance power module, comprising input power terminals, output power terminals, a top metal insulating substrate, a bottom metal insulating substrate, and a plastic-encapsulated housing. The input power terminals include a positive power terminal and a negative power terminal. The top and bottom metal insulating substrates are stacked, each having a chip sintered on its opposing surfaces. The positive power terminal, the negative power terminal, and the output power terminal are all electrically connected to the chip. The output power terminal includes a welding portion and a connecting portion located outside the plastic-encapsulated housing, the welding portion being located between the top and bottom metal insulating substrates. This invention reduces loop parasitic inductance, reduces the volume of the power module, saves cost, and reduces weight. It is particularly suitable for packaging SiC power chips, fully improving the overcurrent capacity and enhancing the reliability of the module.

[0004] CN118431209A discloses a low parasitic inductance SiC power module and a manufacturing method, comprising a first substrate, a second substrate, a power chip, a bonding wire, a third substrate, a drive terminal and a power terminal, wherein one side of the first substrate is the bottom, and the first substrate, the second substrate and the third substrate are stacked in sequence from bottom to top, a plurality of the power chips and a plurality of drive terminals are fixedly mounted on the second substrate, and the plurality of power chips are electrically connected to the second substrate through bonding wires, a power loop is formed between the power chips, the drive terminal and the power terminal are electrically connected to the second substrate, the input end and the output end of the second substrate for electrically connecting the power terminal are both arranged between the plurality of power chips, and the input end and the output end of the second substrate for electrically connecting the power terminal are both located within the power loop, in order to improve the stability of the SiC power module.

[0005] The defects of existing SiC power module products mainly include the following categories: 1. Parasitic inductance: Traditional packaging structures result in significant parasitic inductance, which limits device switching speeds, increases electromagnetic interference, and frequently causes voltage spikes, severely impairing module performance and reliability. For example, in high-frequency applications, voltage spikes caused by parasitic inductance can breakdown the chip, shortening module life.

[0006] 2. Insufficient heat dissipation performance: The heat dissipation design of existing modules is not perfect. When running at high power, the large amount of heat generated by the chip cannot be dissipated in time, causing the module temperature to be too high, affecting performance and stability, and may also cause thermal failure problems.

[0007] 3. Weak resistance to mechanical stress: Under some vibration or bending conditions, the traditional package has poor resistance to mechanical stress, which can easily damage the chip and interconnection structure, reducing the stability and service life of the module.

[0008] As power electronics technology develops towards high frequency, high power and high integration, higher requirements are placed on the performance of SiC power modules. Summary of the Invention

[0009] The present invention addresses the problems of high parasitic inductance and poor heat dissipation in SiC power modules. It provides a 3D-packaged low-parasitic inductance power module. By using high-conductivity copper material to connect the laminate and the copper layer in the substrate to form an intermediate layer, the body inductance is significantly reduced and the heat dissipation effect is improved. It has obvious advantages in high-frequency, high-voltage, and high-power applications, and can effectively improve the overall performance and reliability of power electronic systems.

[0010] To achieve the above object, the technical solution adopted by the present invention is: A 3D packaged low parasitic inductance SiC power module comprises an upper substrate layer, an upper chip layer, an upper connection layer, an intermediate layer, a decoupling capacitor, a lower connection layer, a lower chip layer and a lower substrate layer stacked in sequence; The chip layer is electrically connected to the substrate layer; the upper chip layer is stacked and arranged on the inner side of the upper substrate layer, and the lower chip layer is stacked and arranged on the inner side of the lower substrate layer; The middle layer is located between the upper chip layer and the lower chip layer, and both sides of the middle layer are electrically connected to the chip layer through molybdenum copper blocks as buffer layers; the middle layer is also provided with AC connection terminals; the molybdenum copper blocks do not completely cover the chip layer when connected to the chip layer, and the uncovered portion is used to set the gate of the chip layer; The upper connection layer and the lower connection layer are window-type copper blocks, externally connected to DC terminals. The upper connection layer is located between the middle layer and the upper substrate layer, and is used to connect the upper substrate layer and the decoupling capacitor; the lower connection layer is located between the middle layer and the lower substrate layer, and is used to connect the lower substrate layer and the decoupling capacitor; The decoupling capacitors are two groups of capacitors arranged beside the middle layer and electrically connected to the upper connection layer and the lower connection layer.

[0011] The operating principle of the 3D-packaged SiC power module in this invention is as follows: through an innovative stacking structure and interconnection technology, a close connection and efficient electrical transmission between the chip and substrate are achieved. During operation, current enters the module at the DC+ terminal, passes through the upper connection layer and the copper cladding inside the upper DBC layer to the substrate layer, then passes through the wiring layer and silver sintering layer on the substrate layer to the upper chip layer, and is output from the AC terminal through the intermediate layer or to the lower chip layer, and then flows through the lower substrate layer, the connecting copper block, the lower connection layer, and the copper cladding inside the lower DBC layer to the DC- terminal.

[0012] The stacked chip structure significantly shortens the current path and reduces parasitic inductance. The mutual inductance between the upper and lower connection layers further reduces the module's parasitic inductance. Integrated decoupling capacitors reduce chip overshoot voltage, saving circuit space, improving chip electrical performance, and promoting overall module miniaturization.

[0013] Preferably, the chip layer and substrate layer are electrically connected via silver sintering. Vertical interconnection technology, typically silver sintering, is used to achieve electrical connection between the chip and substrate. The material and structural design of the interconnect layer can further reduce parasitic inductance and improve signal transmission efficiency. During multiple reflow soldering cycles, the solder melting point requirement increases with each soldering step. In the present invention, silver sintering is preferred for electrical connection between the chip layer and substrate layer to reduce parasitic inductance.

[0014] Preferably, the upper substrate layer and the lower substrate layer respectively include an outer copper layer, a ceramic layer and an inner copper layer.

[0015] Preferably, the chip layer is connected to the inner copper layer of the substrate layer.

[0016] Preferably, the chip layer is any one of SiC MOSFET, Si MOSFET, and CoolSiC MOSFET. Preferably, the chip layer is SiC MOSFET, which has the advantages of low on-resistance, high switching speed, and high withstand voltage.

[0017] Preferably, the ceramic layer is a ceramic material with good insulation properties such as aluminum nitride ceramic substrate, aluminum oxide or beryllium oxide.

[0018] Preferably, the decoupling capacitor is electrically connected to the upper and lower connection layers via reflow soldering. The decoupling capacitor can absorb the overshoot voltage generated by the parasitic inductance when the chip is turned on, stabilizing the voltage across the chip and significantly improving the chip's operational stability.

[0019] Preferably, the intermediate layer is composed of copper blocks.

[0020] Preferably, the upper and lower connection layers are externally connected to DC terminals, through which DC current flows from the upper connection layer and out of the lower connection layer, thereby changing the current path and canceling the mutual inductance of the current loop, further reducing parasitic inductance. The AC connection terminals are soldered to the middle layer by reflow soldering.

[0021] Preferably, the outer copper layers of the upper and lower substrate layers are provided with etched heat dissipation microchannels. This can further improve the heat dissipation performance and reliability of the module, enabling stable operation under harsh operating conditions of higher power and higher frequency, thereby extending the module's service life.

[0022] Preferably, the inner copper layer is wired using a Kelvin wiring method.

[0023] Preferably, the molybdenum-copper block is an alloy block with molybdenum accounting for 50-80% by mass and copper accounting for 20-50% by mass. Preferably, the molybdenum-copper spacer is a combination alloy of 70% molybdenum and 30% copper, which takes into account the stress buffering performance of molybdenum and the heat dissipation performance of copper.

[0024] The inner copper layer of the substrate uses Kelvin wiring to avoid overshoot voltage on the gate. Furthermore, the 3D packaged module enables double-sided heat dissipation. Heat generated by the chip is quickly transferred to the external heat sink through the highly thermally conductive substrate and package housing, ensuring the module's normal operating temperature.

[0025] Compared to traditional SiC power modules, this invention utilizes a 3D stacked packaging structure. The tight integration of the chip, substrate, and interconnect layers, and the mutual inductance cancellation between interconnect layers, significantly reduces parasitic inductance. Internally integrated decoupling capacitors reduce chip overshoot voltage, increasing chip stability. Internal copper layer wiring utilizes Kelvin wiring to separate the source of the drain-source current path from the source of the gate-source current path, significantly reducing the overshoot voltage on the gate during chip switching. Furthermore, optimized wiring and interconnect technologies further enhance electrical performance and signal transmission efficiency. The double-sided heat dissipation structure also significantly improves the module's heat dissipation capacity.

[0026] The SiC power module of the present invention is mainly used in high-frequency, high-voltage, high-power power electronic equipment, such as electric vehicles, industrial motor drives, renewable energy systems, etc. When in use, the module is installed on a radiator and connected to other parts of the system through an external circuit.

[0027] Compared with the prior art, the present invention has the following beneficial effects: (1) The SiC power module of the present invention can significantly reduce the parasitic inductance of the SiC power module, improve switching speed and performance, reduce electromagnetic interference and voltage spikes, and enhance reliability and stability.

[0028] (2) The SiC power module of the present invention can improve the heat dissipation performance of the module, ensure stable operation under high power and high frequency conditions, have better electromagnetic compatibility, reduce the impact of electromagnetic interference on the system, and improve the reliability and stability of the entire power electronic system. The buffer layer can also enhance the module's ability to resist mechanical stress and adapt to different working environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a circuit diagram of a bridge arm of a 3D packaged low parasitic inductance SiC power module half-bridge power module according to the present invention.

[0030] FIG2 is a schematic diagram of an overall explosion of the 3D packaged low parasitic inductance SiC power module of Example 1.

[0031] FIG3 is a side cross-sectional view of the lower bridge arm of the 3D packaged low parasitic inductance SiC power module of Example 1.

[0032] FIG4 is a diagram of the current path of the lower bridge arm in the low parasitic inductance SiC power module of Example 1.

[0033] FIG5 is a current path diagram of the low parasitic inductance SiC power module of Example 1 using the inner copper layer Kelvin wiring method.

[0034] FIG6 shows the terminalless DC-DC parasitic inductance simulation results of the low parasitic inductance SiC power module of Example 1.

[0035] Figure 7 This is the heat dissipation of the low parasitic inductance SiC power module of Example 1.

[0036] Figure 8 This is the heat dissipation of a single chip in the low parasitic inductance SiC power module in Example 1.

[0037] Among them, 11 is the upper substrate layer, 12 is the lower substrate layer, 13 is the outer copper layer, 14 is the ceramic layer, 15 is the inner copper layer, 21 is the upper chip layer, 22 is the lower chip layer, 31 is the upper connection layer, 32 is the lower connection layer, 4 is the middle layer, 5 is the decoupling capacitor, 6 is the molybdenum copper block, and 7 is the AC connection terminal. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with embodiment. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Those skilled in the art will make modifications or equivalent substitutions based on understanding the technical solution of the present invention, without departing from the spirit and scope of the technical solution of the present invention, and all should be encompassed within the protection scope of the present invention.

[0039] Example 1 High-performance SiC MOSFETs are used as the chip layer. The size and number of chips are selected and configured according to the power level and application requirements of the module. The substrate layer is made of Al2O3 ceramic material, which has high thermal conductivity (170-200 W / m・K) and good insulation properties. Copper foil is bonded on both sides of the substrate through the DBC (Direct Bonded Copper) process to form a metal wiring layer with inner and outer copper layers. The bridge arm circuit diagram of the 3D packaged low parasitic inductance SiC half-bridge power module is shown below. Figure 1 shown.

[0040] Figure 2 This is an overall exploded diagram of a 3D-packaged low parasitic inductance SiC power module, including an upper substrate layer 11, an upper chip layer 21, an upper connection layer 31, an intermediate layer 4, a decoupling capacitor 5, a lower connection layer 32, a lower chip layer 22 and a lower substrate layer 12 stacked in sequence; the upper substrate layer 11 and the lower substrate layer 12 respectively include an outer copper layer 13, a ceramic layer 14 and an inner copper layer 15.

[0041] The chip layer and substrate layer are fixed to the inner copper layer 15 of the substrate via silver paste sintering, achieving electrical and thermal contact. The upper chip layer 21 is stacked on the inner copper layer 15 of the upper substrate layer 11, while the lower chip layer 21 is stacked on the inner cylindrical layer 15 of the lower substrate layer 12. The inner copper layer is wired using Kelvin wiring, and the outer copper layer is equipped with etched heat dissipation microchannels. These provide electrical connection between the chip and external pins, while also providing excellent heat dissipation, effectively conducting heat generated by the chip.

[0042] The intermediate layer 4 is located between the upper chip layer 21 and the lower chip layer 22. Both sides of the intermediate layer 4 are electrically connected to the chip layer through molybdenum copper blocks 6 as buffer layers. The intermediate layer 4 is also provided with AC connection terminals 7. When the molybdenum copper blocks 6 are connected to the chip layer, they do not completely cover the chip layer. The uncovered portion is used to set the gate of the chip layer. The upper connection layer 31 and the lower connection layer 32 are window-type copper blocks, which are externally connected to DC terminals. The upper connection layer 31 is located between the middle layer 4 and the upper substrate layer 11, and is used to connect the upper substrate layer 11 and the decoupling capacitor 5; the lower connection layer 32 is located between the middle layer 4 and the lower substrate layer 12, and is used to connect the lower substrate layer 12 and the decoupling capacitor 5; The decoupling capacitors 5 are two sets of capacitors arranged beside the middle layer 4, and are electrically connected to the upper connection layer 31 and the lower connection layer 32; the decoupling capacitors 5 are electrically connected to the upper connection layer 31 and the lower connection layer 32 by reflow soldering; FIG3 is a side cross-sectional view of the lower bridge arm of the 3D packaged low parasitic inductance SiC power module of Example 1. Figure 4This is the current loop of the lower bridge arm of the module. The arrow indicates the direction of current flow. This loop makes full use of the mutual inductance cancellation characteristics to reduce inductance, while avoiding the chip flip-chip process commonly used in 3D modules, making the module manufacturing simpler.

[0043] Figure 5 The module's gate Kelvin loop is also shown. This design separates the gate-source loop from the drain-source loop, preventing the high current flowing through the chip's source from generating a large reverse electromotive force on the gate-source inductor and affecting the gate voltage, thereby accelerating the chip's turn-on speed.

[0044] Figure 6 Q3D simulation analysis shows that compared to other 3D packaged modules, this module's parasitic inductance is reduced by approximately 50%, reducing EMI interference. Compared to traditional modules, the parasitic inductance is only one-fifth that of traditional SiC power modules, the junction-to-case thermal resistance is significantly reduced, and the heat dissipation capacity is improved by approximately 35%. These technical results demonstrate that the power module of this invention has significant advantages in high-frequency, high-voltage, and high-power applications, and can effectively improve the overall performance and reliability of power electronics systems.

[0045] Figure 7 and Figure 8 is the heat dissipation data of the module, Figure 7 This is the heat dissipation condition when the convection heat dissipation coefficient is 5000h and the single chip power is 100W. Figure 8 The figure shows the heat dissipation of the chip. As can be seen from the figure, the chip thermal resistance of the module is only 0.15C / W, which is lower than the industrial standard of 0.3C / W.

Claims

1. A 3D packaged low parasitic inductance SiC power module, characterized in that: It includes an upper substrate layer, an upper chip layer, an upper connection layer, an intermediate layer, a decoupling capacitor, a lower connection layer, a lower chip layer and a lower substrate layer stacked in sequence; The chip layer is electrically connected to the substrate layer; the upper chip layer is stacked and arranged on the inner side of the upper substrate layer, and the lower chip layer is stacked and arranged on the inner side of the lower substrate layer; The middle layer is located between the upper chip layer and the lower chip layer, and both sides of the middle layer are electrically connected to the chip layer through molybdenum copper blocks as buffer layers; the middle layer is also provided with AC connection terminals; the molybdenum copper blocks do not completely cover the chip layer when connected to the chip layer, and the uncovered portion is used to set the gate of the chip layer; The upper connection layer and the lower connection layer are window-type copper blocks, externally connected to DC terminals. The upper connection layer is located between the middle layer and the upper substrate layer, and is used to connect the upper substrate layer and the decoupling capacitor; the lower connection layer is located between the middle layer and the lower substrate layer, and is used to connect the lower substrate layer and the decoupling capacitor; The decoupling capacitors are two groups of capacitors arranged beside the middle layer and electrically connected to the upper connection layer and the lower connection layer.

2. The 3D packaged low parasitic inductance SiC power module according to claim 1, characterized in that: The chip layer and the substrate layer are electrically connected via silver sintering.

3. The 3D packaged low parasitic inductance SiC power module according to claim 1, characterized in that: The upper substrate layer and the lower substrate layer respectively include an outer copper layer, a ceramic layer and an inner copper layer.

4. The 3D packaged low parasitic inductance SiC power module according to claim 3, characterized in that: The chip layer is connected to the inner copper layer of the substrate layer.

5. The 3D packaged low parasitic inductance SiC power module according to claim 1, characterized in that: The chip layer is any one of SiC MOSFET, Si MOSFET, and CoolSiC MOSFET; and the ceramic layer is any one of aluminum nitride ceramic substrate, aluminum oxide, or beryllium oxide.

6. The 3D packaged low parasitic inductance SiC power module according to claim 1, characterized in that: The middle layer is composed of copper blocks.

7. The 3D packaged low parasitic inductance SiC power module according to claim 1, characterized in that: The decoupling capacitor is electrically connected to the upper connection layer and the lower connection layer by reflow soldering; The AC connection terminal is soldered on the middle layer by reflow soldering.

8. The 3D packaged low parasitic inductance SiC power module according to claim 1, characterized in that: The molybdenum-copper block is an alloy block in which molybdenum accounts for 50-80% by mass and copper accounts for 20-50% by mass.

9. The 3D packaged low parasitic inductance SiC power module according to claim 1, characterized in that: Etched heat dissipation microchannels are provided on the outer copper layers of the upper substrate layer and the lower substrate layer.

10. The 3D packaged low parasitic inductance SiC power module according to claim 1, characterized in that: The inner copper layer is wired using the Kelvin wiring method.

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