3D packaged low parasitic inductance sic power module

Abstract

The application discloses a 3D packaged low parasitic inductance SiC power module, which comprises a substrate layer, a chip layer, a connecting layer, an intermediate layer and a decoupling capacitor; the chip layer is electrically connected with the substrate layer; the intermediate layer is located between the upper chip layer and the lower chip layer; the upper connecting layer and the lower connecting layer are windowed copper blocks, and are externally connected with DC terminals and used for connecting the upper substrate layer and the decoupling capacitor; the decoupling capacitor is two groups of capacitors arranged on the side of the intermediate layer and electrically connected with the upper connecting layer and the lower connecting layer. By adopting the copper material with high conductivity, the intermediate layer is connected with the copper layer in the laminated layer and the substrate, the body inductance is obviously reduced, the heat dissipation effect is improved, obvious advantages are obtained in high-frequency, high-voltage and high-power applications, and the overall performance and reliability of the power electronic system can be effectively improved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of power electronics, and in particular to a 3D packaged low parasitic inductance SiC power module. BACKGROUND

[0002] At present, SiC power modules are widely used in the field of power electronics, and the system structure thereof generally comprises a chip, a substrate, an interconnection and a packaging shell. The chip is responsible for power conversion, the substrate provides mechanical support and electrical connection, the interconnection realizes electrical connection of the chip and the substrate, the decoupling capacitor realizes the function of reducing the overshoot voltage when the chip switches, the buffer pad realizes the function of reducing the thermal stress between the connecting surfaces, prolongs the service life of the module, and the packaging shell plays a protective role. In the algorithm aspect, the traditional electromagnetic field simulation algorithm is mainly used to predict and optimize the performance of the module.

[0003] CN107170714A discloses a low parasitic inductance power module, comprising an input power terminal, an output power terminal, a top metal insulation substrate, a bottom metal insulation substrate and a plastic packaging shell, the input power terminal comprises a positive power terminal and a negative power terminal, the top metal insulation substrate and the bottom metal insulation substrate are arranged in a stack, the top metal insulation substrate and the bottom metal insulation substrate are sintered with chips on the opposite surfaces thereof, and the positive power terminal, the negative power terminal and the output power terminal are electrically connected with the chips; the output power terminal comprises a welding portion and a connecting portion located outside the plastic packaging shell, and the welding portion is located between the top metal insulation substrate and the bottom metal insulation substrate. The application reduces the loop parasitic inductance, reduces the volume of the power module, saves the cost, reduces the weight, is especially suitable for packaging of SiC power chips, fully improves the overcurrent capacity and improves the reliability of the module.

[0004] CN118431209A discloses a low parasitic inductance SiC power module and a manufacturing method, comprising a first substrate, a second substrate, a power chip, a bonding lead, a third substrate, a driving terminal and a power terminal, one side of the first substrate is lower, the first substrate, the second substrate and the third substrate are arranged in a stack from lower to upper, a plurality of power chips and a plurality of driving terminals are fixedly installed on the second substrate, and the plurality of power chips are electrically connected with the second substrate through the bonding lead, the power chips form a power loop, the driving terminal and the power terminal are electrically connected with the second substrate, the input end and the output end of the power terminal electrically connected with the second substrate are arranged between the plurality of power chips, and the input end and the output end of the power terminal electrically connected with the second substrate are located within the power loop, so as to improve the stability of the SiC power module.

[0005] The defects of the existing SiC power module products mainly include the following types:

[0006] 1. Parasitic inductance problem: The traditional packaging structure leads to large parasitic inductance, which limits the switching speed of the device, increases electromagnetic interference, and causes problems such as voltage spikes, which seriously weakens the performance and reliability of the module. For example, when used at high frequencies, the voltage spike caused by parasitic inductance will break down the chip, reducing the service life of the module.

[0007] 2. Insufficient heat dissipation performance: The heat dissipation design of existing modules is not perfect. When running at high power, the large amount of heat generated by the chip cannot be dissipated in time, causing the module temperature to be too high, affecting performance and stability, and may also cause thermal failure problems.

[0008] 3. Weak mechanical stress resistance: In some vibration or bending working conditions, the mechanical stress resistance of traditional packaging is poor, which easily damages the chip and interconnection structure, reduces the stability and service life of the module.

[0009] With the development of power electronics technology towards high frequency, high power and high integration, higher requirements are put forward for the performance of SiC power modules. SUMMARY

[0010] The present application provides a 3D packaged low parasitic inductance power module to solve the problems of high parasitic inductance and poor heat dissipation effect of SiC power modules. By using high-conductivity copper material, the intermediate layer is connected with the copper layer in the stack and the substrate, which significantly reduces the body inductance and improves the heat dissipation effect. It has obvious advantages in high-frequency, high-voltage and high-power applications, and can effectively improve the overall performance and reliability of the power electronic system.

[0011] To achieve the above purpose, the technical scheme adopted by the present application is:

[0012] A 3D packaged low parasitic inductance SiC power module, comprising upper substrate layer, upper chip layer, upper connection layer, intermediate layer, decoupling capacitor, lower connection layer, lower chip layer and lower substrate layer stacked in sequence;

[0013] The chip layer is electrically connected with the substrate layer; the upper chip layer is stacked and arranged on the inner side of the upper substrate layer, and the lower chip layer is stacked and arranged on the inner side of the lower substrate layer;

[0014] The intermediate layer is located between the upper chip layer and the lower chip layer, and the two sides of the intermediate layer are electrically connected with the chip layer through molybdenum copper blocks as buffer layers; the intermediate layer is also provided with an AC connection terminal; when the molybdenum copper block is connected with the chip layer, it does not completely cover the chip layer, and the uncovered part is used to set the gate of the chip layer;

[0015] The upper connection layer and the lower connection layer are windowed copper blocks, and are externally connected with DC terminals; the upper connection layer is located between the intermediate layer and the upper substrate layer, and is used to connect the upper substrate layer and the decoupling capacitor; the lower connection layer is located between the intermediate layer and the lower substrate layer, and is used to connect the lower substrate layer and the decoupling capacitor;

[0016] The decoupling capacitors are two groups of capacitors arranged on the sides of the intermediate layer and electrically connected with the upper and lower connecting layers.

[0017] The working principle of the 3D packaged SiC power module in the application is that: through the innovative stacking structure and interconnection technology, the close connection and efficient electrical transmission between the chip and the substrate are realized. In the working process, the current enters the module from the DC+ end, reaches the substrate layer through the upper connecting layer and the inner copper of the upper layer DBC, reaches the upper chip layer through the wiring layer and the silver sintering layer on the substrate layer, is output from the AC end through the intermediate layer, or reaches the lower chip layer, and then flows out from the DC- end through the lower substrate layer, the connecting copper block and the inner copper of the lower layer DBC.

[0018] Due to the stacking structure of the chip layer, the current path is greatly shortened, and the parasitic inductance is significantly reduced; the mutual inductance effect between the upper and lower connecting layers is utilized to further reduce the parasitic inductance of the module. The internal integration of the decoupling capacitor reduces the overshoot voltage of the chip, saves the circuit space, improves the electrical performance of the chip, and promotes the overall miniaturization of the module.

[0019] Preferably, the electrical connection between the chip layer and the substrate layer is achieved by silver sintering electrical connection, and the electrical connection between the chip and the substrate is achieved by vertical interconnection technology. Silver sintering is usually selected, and the material and structure design of the interconnection layer can further reduce the parasitic inductance and improve the signal transmission efficiency. During multiple reflow soldering, the requirement for the melting point of the solder increases gradually each time. In the application, the electrical connection between the chip layer and the substrate layer is preferably achieved by silver sintering, which reduces the parasitic inductance.

[0020] Preferably, the upper and lower substrate layers each comprise an outer copper layer, a ceramic layer and an inner copper layer.

[0021] Preferably, the inner copper layers of the chip layer and the substrate layer are connected.

[0022] Preferably, the chip layer is any one of SiC MOSFET, Si MOSFET and CoolSiC MOSFET, and preferably, the chip layer is SiC MOSFET, which has the advantages of low on-resistance, high switching speed and high withstand voltage.

[0023] Preferably, the ceramic layer is a ceramic material with good insulation performance, such as aluminum nitride ceramic substrate, aluminum oxide or beryllium oxide.

[0024] Preferably, the decoupling capacitors are electrically connected with the upper and lower connecting layers by reflow soldering. The decoupling capacitors can be used to absorb the overshoot voltage generated on the parasitic inductance during the conduction of the chip, play a role in stabilizing the voltage across the chip, and significantly improve the stability of the chip operation.

[0025] Preferably, the intermediate layer is a copper block composition.

[0026] Preferably, the upper and lower connecting layers are connected with DC terminals, and the DC current flows into the upper connecting layer and flows out of the lower connecting layer through the terminals, so as to change the current path and realize mutual inductance cancellation of the current loop, thereby further reducing the parasitic inductance.

[0027] Preferably, the outer copper layer of the upper and lower substrate layers is provided with etched heat dissipation microchannels, so as to further improve the heat dissipation performance and reliability of the module, so that the module can still stably operate under harsh working conditions of higher power and higher frequency, and the service life of the module is prolonged.

[0028] Preferably, the inner copper layer is wired by using the Kelvin wiring method.

[0029] Preferably, the molybdenum copper block is an alloy block with a molybdenum mass ratio of 50-80% and a copper mass ratio of 20-50%. Preferably, the molybdenum copper block adopts a combined alloy with a molybdenum mass ratio of 70% and a copper mass ratio of 30%, which takes into account the stress buffering of molybdenum and the heat dissipation performance of copper.

[0030] The inner copper layer of the substrate is wired by using the Kelvin wiring method, so as to avoid the overshoot voltage generated on the gate. At the same time, the 3D packaged module can realize double-sided heat dissipation, and the heat generated by the chip is quickly conducted to the external heat sink through the high-thermal-conductivity substrate and packaging shell, so as to ensure the normal working temperature of the module.

[0031] Compared with the traditional SiC power module, the 3D stacked packaging structure is adopted in the present application, the close integration of the chip layer, the substrate layer and the interconnection layer and the mutual inductance cancellation between the interconnection layers significantly reduce the parasitic inductance; the internally integrated decoupling capacitor can reduce the overshoot voltage of the chip and increase the stability of the chip; the Kelvin wiring method is used for wiring the internal copper layer to separate the source of the current path between the drain and the source from the source of the current path between the gate and the source, thereby greatly reducing the overshoot voltage generated on the gate when the chip is switched on. At the same time, the optimized wiring and interconnection technology further improve the electrical performance and signal transmission efficiency; the double-sided heat dissipation structure also greatly improves the heat dissipation capacity of the module.

[0032] The SiC power module of the present application is mainly applied to high-frequency, high-voltage and high-power power electronic devices, such as electric vehicles, industrial motor drives, renewable energy systems, etc. In use, the module is mounted on a heat sink and connected with other parts of the system through an external circuit.

[0033] Compared with the prior art, the present application has the following beneficial effects:

[0034] (1) The SiC power module of the present application can significantly reduce the parasitic inductance of the SiC power module, improve the switching speed and performance, reduce electromagnetic interference and voltage spikes, and enhance reliability and stability.

[0035] (2) The SiC power module of the present application can improve the heat dissipation performance of the module, ensure stable operation under high power and high frequency conditions, better electromagnetic compatibility, reduce the influence of electromagnetic interference on the system, improve the reliability and stability of the entire power electronic system, and the buffer layer can also enhance the mechanical stress resistance of the module, and adapt to different working environments. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a bridge arm circuit diagram of the 3D packaged low parasitic inductance SiC power module half-bridge power module in the present application.

[0037] Figure 2 is an overall exploded schematic diagram of the 3D packaged low parasitic inductance SiC power module of Example 1.

[0038] Figure 3 is a side sectional view of the lower bridge arm of the 3D packaged low parasitic inductance SiC power module of Example 1.

[0039] Figure 4 is a current path diagram of the lower bridge arm in the low parasitic inductance SiC power module of Example 1.

[0040] Figure 5 is a current path diagram under the Kelvin wiring method of the inner copper layer in the low parasitic inductance SiC power module of Example 1.

[0041] Figure 6 is the simulation result of the terminal-free DC-DC parasitic inductance of the low parasitic inductance SiC power module of Example 1.

[0042] Figure 7 The heat dissipation of the low parasitic inductance SiC power module of Example 1.

[0043] Figure 8 The heat dissipation of the low parasitic inductance SiC power module of Example 1.

[0044] Wherein, 11 is the upper substrate layer, 12 is the lower substrate layer, 13 is the outer copper layer, 14 is the ceramic layer, 15 is the inner copper layer, 21 is the upper chip layer, 22 is the lower chip layer, 31 is the upper connection layer, 32 is the lower connection layer, 4 is the middle layer, 5 is the decoupling capacitor, 6 is the molybdenum copper block, and 7 is the AC connection terminal. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application. Those skilled in the art can modify or replace equivalently without departing from the spirit and scope of the present application, which should be covered within the protection scope of the present application.

[0046] Embodiment 1

[0047] High-performance SiC MOSFET is used as the chip layer, and the size and number of the chip are selected and configured according to the power level and application requirements of the module; the substrate layer uses Al2O3 ceramic material, which has high thermal conductivity (170-200 W / m·K) and good insulation performance, and through the DBC (Direct Bonded Copper) process, copper foils are bonded on both sides of the substrate to form metal wiring layers to obtain inner and outer copper layers. The bridge arm circuit diagram of the 3D packaged low parasitic inductance SiC half-bridge power module is shown in Figure 1

[0048] Figure 2 It is a whole explosion schematic diagram of a 3D packaged low parasitic inductance SiC power module, which includes an upper substrate layer 11, an upper chip layer 21, an upper connection layer 31, an intermediate layer 4, a decoupling capacitor 5, a lower connection layer 32, a lower chip layer 22 and a lower substrate layer 12 stacked in sequence; the upper substrate layer 11 and the lower substrate layer 12 respectively include an outer copper layer 13, a ceramic layer 14 and an inner copper layer 15.

[0049] The chip layer and the substrate layer are fixed on the inner copper layer 15 of the substrate by silver paste sintering to realize good electrical and thermal contact. The upper chip layer 21 is stacked and arranged on the inner copper layer 15 of the upper substrate layer 11, and the lower chip layer 21 is stacked and arranged on the inner copper layer 15 of the lower substrate layer 12; the inner copper layer is wired by the Kelvin wiring method, and the outer copper layer is provided with etched heat dissipation microchannels. It can be used to realize electrical connection between the chip and the external pin, and at the same time has good heat dissipation performance, which can effectively conduct the heat generated by the chip.

[0050] The intermediate layer 4 is located between the upper chip layer 21 and the lower chip layer 22, and the intermediate layer 4 is electrically connected to the chip layer through the molybdenum copper block 6 as a buffer layer on both sides; the intermediate layer 4 is also provided with an AC connection terminal 7; when the molybdenum copper block 6 is connected to the chip layer, it does not completely cover the chip layer, and the uncovered part is used to set the gate of the chip layer;

[0051] ​The upper connection layer 31 and the lower connection layer 32 are windowed copper blocks, and external DC terminals are connected, the upper connection layer 31 is located between the intermediate layer 4 and the upper substrate layer 11, and is used for connecting the upper substrate layer 11 and the decoupling capacitor 5; the lower connection layer 32 is located between the intermediate layer 4 and the lower substrate layer 12, and is used for connecting the lower substrate layer 12 and the decoupling capacitor 5;

[0052] The decoupling capacitor 5 is two groups of capacitors arranged on the side of the intermediate layer 4, and is electrically connected with the upper connection layer 31 and the lower connection layer 32; the decoupling capacitor 5 is electrically connected with the upper connection layer 31 and the lower connection layer 32 through reflow soldering;

[0053] Fig. 3 is a side sectional view of the low parasitic inductance SiC power module lower bridge arm of the 3D package of embodiment 1. Figure 4 It is the current loop of the module lower bridge arm, the arrow indicates the current flow direction, and the loop takes advantage of the characteristic of mutual inductance cancellation to reduce inductance, while avoiding the commonly used chip flip-chip process in the 3D module, so that the manufacturing of the module is more simple.

[0054] Figure 5 The gate Kelvin loop of the module is also shown. The design separates the gate-source loop from the drain-source loop, avoiding the large reverse electromotive force generated by the large current flowing through the chip source on the gate-source inductance, which affects the gate voltage and speeds up the conduction of the chip.

[0055] Figure 6 It is shown that, compared with other 3D packaged modules, the parasitic inductance of the module is reduced by about 50%, and the EMI interference is reduced; compared with the traditional module, the parasitic inductance is only 1 / 5 of the traditional SiC power module, the junction case thermal resistance is significantly reduced, and the heat dissipation capacity is improved by about 35%. These technical effects show that the power module of the application has obvious advantages in high frequency, high voltage and high power applications, and can effectively improve the overall performance and reliability of the power electronic system.

[0056] Figure 7 And Figure 8 is the heat dissipation data of the module, Figure 7 is the heat dissipation condition under the condition of a single chip power of 100W and a convection heat dissipation coefficient of 5000h, Figure 8 is the heat dissipation condition of the chip, and it can be seen from the figure that the chip thermal resistance of the module is only 0.15C / W, which is lower than the industrial 0.3C / W.

Claims

1. A 3D-packaged low parasitic inductance SiC power module, characterized in that, It includes an upper substrate layer, an upper chip layer, an upper interconnect layer, an intermediate layer, a decoupling capacitor, a lower interconnect layer, a lower chip layer, and a lower substrate layer stacked in sequence; the intermediate layer is composed of copper blocks; The upper substrate layer and the lower substrate layer respectively include an outer copper layer, a ceramic layer and an inner copper layer; The inner copper layer connects the chip layer to the substrate layer; The chip layer is electrically connected to the substrate layer; the upper chip layer is stacked on the inner side of the upper substrate layer, and the lower chip layer is stacked on the inner side of the lower substrate layer. The intermediate layer is located between the upper chip layer and the lower chip layer. The two sides of the intermediate layer are electrically connected to the chip layer through molybdenum-copper blocks as buffer layers. The intermediate layer is also provided with AC connection terminals. The AC connection terminals are soldered onto the intermediate layer by reflow soldering. When the molybdenum-copper blocks are connected to the chip layer, they do not completely cover the chip layer. The uncovered part is used to set the gate of the chip layer. The upper and lower connection layers are windowed copper blocks with external DC terminals. The upper connection layer is located between the middle layer and the upper substrate layer and is used to connect the upper substrate layer and the decoupling capacitor. The lower connection layer is located between the middle layer and the lower substrate layer and is used to connect the lower substrate layer and the decoupling capacitor. The decoupling capacitors are two sets of capacitors located on the side of the intermediate layer and electrically connected to the upper and lower connection layers. The outer copper layers of the upper and lower substrate layers are provided with etched heat dissipation microchannels.

2. The 3D-packaged low parasitic inductance SiC power module according to claim 1, characterized in that, The electrical connection between the chip layer and the substrate layer is achieved through silver sintering.

3. The low parasitic inductance SiC power module with 3D packaging according to claim 1, characterized in that, The chip layer is any one of SiC MOSFET, Si MOSFET, or CoolSiC MOSFET; the ceramic layer is any one of aluminum nitride ceramic substrate, alumina, or beryllium oxide.

4. The 3D-packaged low parasitic inductance SiC power module according to claim 1, characterized in that, The decoupling capacitor is electrically connected to the upper and lower connection layers via reflow soldering.

5. The 3D-packaged low parasitic inductance SiC power module according to claim 1, characterized in that, The molybdenum-copper block is an alloy block with a molybdenum content of 50-80% and a copper content of 20-50%.

6. The 3D-packaged low parasitic inductance SiC power module according to claim 1, characterized in that, The inner copper layer is wired using the Kelvin wiring method.

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