A photoelectric logic gate device and its logic control method

Abstract

This application relates to an optoelectronic logic gate device and its logic control method. The optoelectronic logic gate device includes: a substrate, a waveguide layer, an upper cladding layer, an h-BN nanosheet, a semiconductor photoresponse layer, and source and drain electrodes deposited at both ends of the semiconductor photoresponse layer. The waveguide layer includes a first waveguide, a second waveguide, and a third waveguide. The semiconductor photoresponse layer is stacked directly above the h-BN nanosheet by dry transfer, forming a high-strain region on the left, a no-strain region in the middle, and a high-strain region on the right. The high-strain region on the left corresponds to the first waveguide, the no-strain region in the middle corresponds to the second waveguide, and the high-strain region on the right corresponds to the third waveguide. The device realizes all-optical input OR (or gate) and XOR (exclusive or non-or gate) logic functions in a single device without the need for additional electric field modulation.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an optoelectronic logic gate device and its logic control method. Background Technology

[0002] Electronic logic gates are a key component for precise and fast data processing in integrated circuits. However, due to insufficient switching speed and computational power consumption, processors based on electronic logic gates are severely limited when computing massive datasets. Therefore, all-optical logic gates using optical inputs and outputs are a technological alternative to replace electronic binary adders, binary counters, decision circuits, optical processors, data encoders, and bit pattern recognition circuits. These optical logic gates are complex designs based on optical components. While optical logic gate systems offer good optical gain, saturated output power, and gain bandwidth, they are costly and difficult to miniaturize.

[0003] As an important complement to all-electronic and all-optical logic devices, optoelectronic logic gates can more easily process visual data sources. Machine vision chips based on optoelectronic logic gates extract features from imaging images using Boolean algorithms, which is expected to significantly reduce redundant data.

[0004] Typical optoelectronic logic gates consist of two or more semiconductor junctions that interact with the light input and release Boolean outputs. The most studied photodiodes are pn heterojunction photodiodes or photodetectors. Because these detectors are primarily based on unidirectional carrier transport, most devices can only implement one logic function, making high-density integration difficult. Summary of the Invention

[0005] Therefore, it is necessary to provide an optoelectronic logic gate device and its logic control method to address the above-mentioned technical problems.

[0006] In a first aspect, embodiments of this application provide an optoelectronic logic gate device, the device comprising: a substrate, a waveguide layer, an upper cladding layer, h-BN nanosheets, a semiconductor photoresponse layer, and source and drain electrodes deposited at both ends of the semiconductor photoresponse layer, wherein the waveguide layer comprises a first waveguide, a second waveguide, and a third waveguide, wherein:

[0007] The semiconductor photoresponse layer is stacked on top of the h-BN nanosheet by dry transfer, so that the semiconductor photoresponse layer forms a high-strain region on the left, a no-strain region in the middle, and a high-strain region on the right. The high-strain region on the left corresponds to the first waveguide, the no-strain region in the middle corresponds to the second waveguide, and the high-strain region on the right corresponds to the third waveguide.

[0008] In one embodiment, the lateral distance between the left high-strain region and the right high-strain region is 6μm to 15μm.

[0009] In one embodiment, the thickness of the h-BN nanosheet is 80 nm to 100 nm.

[0010] In one embodiment, the semiconductor photoresponse layer is made of NbOBr2 and has a thickness of 30 nm to 50 nm.

[0011] In one embodiment, the material of the semiconductor photoresponse layer is a two-dimensional chalcogenide transition metal compound or a binary niobium oxyhalide.

[0012] In one embodiment, the waveguide layer is made of silicon nitride, silicon oxide, or lithium niobate.

[0013] Secondly, embodiments of this application provide a logic control method based on the optoelectronic logic gate device described in the first aspect above; the method includes:

[0014] According to the logic gate to be executed, the first optical signal and the second optical signal are input into the waveguide layer;

[0015] The first optical signal and the second optical signal are subjected to XOR or OR logic operations using the semiconductor photoresponse layer to obtain the photocurrent value;

[0016] The photocurrent value is output using the source electrode and the drain electrode, and the photocurrent value is used to determine the logic output level of the logic gate.

[0017] In one embodiment, when the optoelectronic logic gate device implements the OR logic gate,

[0018] The first waveguide is used as the first input terminal of the OR logic gate, and the first optical signal is input into the first waveguide.

[0019] The second waveguide is used as the second input terminal of the OR logic gate, and the second optical signal is input into the second waveguide.

[0020] In one embodiment, the optoelectronic logic gate device, when implementing the XOR logic gate,

[0021] The first waveguide is used as the first input terminal of the XOR logic gate, and the first optical signal is input into the first waveguide.

[0022] The third waveguide is used as the second input terminal of the XOR logic gate, and the second optical signal is input into the third waveguide.

[0023] In one embodiment, the wavelength range of the first optical signal and the second optical signal is 365 nm to 1550 nm.

[0024] The aforementioned optoelectronic logic gate device and its logic control method, wherein the optoelectronic logic gate device comprises: a substrate, a waveguide layer, an upper cladding layer, an h-BN nanosheet, a semiconductor photoresponse layer, and source and drain electrodes deposited at both ends of the semiconductor photoresponse layer, the waveguide layer comprising a first waveguide, a second waveguide, and a third waveguide, wherein: the semiconductor photoresponse layer is dry-transfer-stacking directly above the h-BN nanosheet, such that the semiconductor photoresponse layer forms a high-strain region on the left, a no-strain region in the middle, and a high-strain region on the right, wherein the left... The high-strain region on the side corresponds to the first waveguide, the middle strain-free region corresponds to the second waveguide, and the high-strain region on the right side corresponds to the third waveguide. Based on the flexoelectric photovoltaic effect, a single optical signal incident on the left high-strain region will generate a positive photocurrent; a single optical signal incident on the right high-strain region will generate a negative photocurrent, and the absolute value of the photocurrent is close to that of the positive photocurrent; a single optical signal incident on the middle strain-free region will generate a positive photocurrent with an absolute value slightly smaller than that of the left strain region. Therefore, the semiconductor response layer of this logic device allows bidirectional carrier transport and can realize two types of logic gates.

[0025] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0027] Figure 1 This is a schematic diagram of the structure of an optoelectronic logic gate device in one embodiment;

[0028] Figure 2 This is a flowchart illustrating the logic control method of an optoelectronic logic gate device in one embodiment;

[0029] Figure 3 This is a schematic diagram of an optoelectronic logic gate device performing OR logic in one embodiment;

[0030] Figure 4 This is a schematic diagram of an optoelectronic logic gate device performing XOR logic in one embodiment. Detailed Implementation

[0031] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is described and illustrated below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely used to explain this application and are not intended to limit this application. Based on the embodiments provided in this application, all other embodiments obtained by those of ordinary skill in the art without making any creative efforts are within the scope of protection of this application.

[0032] Obviously, the drawings described below are merely examples or embodiments of the present application. Those skilled in the art can, without inventive effort, apply the present application to other similar scenarios based on these drawings. Furthermore, it is also understood that, although the effort involved in such a development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, changes in design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as an insufficiency of the content disclosed in this application.

[0033] References to "embodiments" in this application mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this application may be combined with other embodiments unless there is a conflict.

[0034] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," and "third" used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0035] This application provides an optoelectronic logic gate device, such as... Figure 1 As shown, the optoelectronic logic gate device includes: a substrate 1, waveguide layers stacked sequentially on the substrate, the waveguide layers including a first waveguide 2, a second waveguide 3 and a third waveguide 4, an upper cladding layer 5, h-BN nanosheets 6, a semiconductor photoresponse layer 7, and source electrodes 8 and drain electrodes 9 deposited at both ends of the semiconductor photoresponse layer. The substrate provides physical support for the optoelectronic logic gate device, ensuring the stability of the device structure under high temperature, high pressure or vibration environments. The substrate is made of silicon oxide and silicon materials, which have advantages such as high thermal conductivity, ultra-low optical loss and strong chemical stability.

[0036] For example, the waveguide layer is made of silicon nitride material. 200nm silicon nitride is deposited on a 3μm silicon / silicon oxide substrate by low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition. Then, a layer of photoresist is spin-coated on the surface of the silicon nitride film. The desired waveguide pattern is patterned using electron beam lithography. After development, three waveguide structures are formed using high-precision processing methods such as ion beam etching to realize the transmission of multiple optical signals.

[0037] When implementing optoelectronic logic gate operations, the optoelectronic logic gate device in this embodiment of the application inputs a first optical signal and a second optical signal to two waveguides in the waveguide layer according to the logic gate to be executed (OR logic gate and XOR logic gate), which serve as the first input and the second input for the logic gate operation, respectively.

[0038] For example, the upper cladding is made of silicon oxide material. 200nm silicon oxide is deposited using plasma-enhanced chemical vapor deposition process, and 1μm silicon oxide is deposited after resist removal as the waveguide upper cladding to reduce the loss of optical signal transmission in the waveguide and ensure long-distance and efficient transmission of optical signal in the waveguide.

[0039] The semiconductor photoresponse layer can generate a photoelectric effect under illumination, realizing the conversion of light energy into electrical energy. An 80nm-100nm thick h-BN rectangular nanosheet is dry-transferred using an organic dielectric PDMS-assisted method between the first and third waveguides. After the semiconductor photoresponse layer is stacked directly above the h-BN nanosheets via dry transfer, due to the height of the h-BN rectangular nanosheets, the combined effect of surface energy and PDMS elastic indentation causes the semiconductor photoresponse layer above the edges of the h-BN rectangular nanosheets to bend and accumulate strain at the edges. Stress is applied to the left and right edges of the semiconductor photoresponse layer, forming two high-strain regions. This results in three regions for the semiconductor photoresponse layer: a high-strain region on the left, a no-strain region in the middle, and a high-strain region on the right. The high-strain region on the left corresponds to the first waveguide and is the light input region aligned with it; the no-strain region in the middle corresponds to the second waveguide and is the light input region aligned with it; and the high-strain region on the right corresponds to the third waveguide and is the light input region aligned with it. Based on the flexoelectric photovoltaic effect (a nonlinear photoelectric effect involved in this case, which can also convert light energy into electrical energy without the need for additional bias voltage and pn junction device structure), a single light signal incident on the left high-strain region will generate a positive photocurrent; a single light signal incident on the right high-strain region will generate a negative photocurrent, and the absolute value of the photocurrent is similar to that of the positive photocurrent; a single light signal incident on the middle unstrained region will generate a positive photocurrent with an absolute value slightly smaller than that of the left strain region. Therefore, through strain design, the semiconductor response layer allows bidirectional carrier transport, and the logic function of the optoelectronic logic gate device can be realized.

[0040] The key to the optoelectronic logic gate device in this application lies in its structure. High stress needs to be applied to the channel region of the semiconductor photoresponse layer to achieve all-optical input OR (or gate) and XOR (exclusive or opposite) logic functions in a single device without the need for additional electric field modulation. Based on strain engineering design, the bulk photovoltaic effect can be utilized to achieve logic functions under photovoltaic conditions. The semiconductor photoresponse layer is suitable for most two-dimensional semiconductor materials, and the optical input wavelength can range from ultraviolet to infrared communication bands. The optoelectronic logic gate device enables high-density on-chip integration, device miniaturization, compatibility with silicon photonics chip processes, and ease of integration.

[0041] In one embodiment, the lateral distance between the left high-strain region and the right high-strain region is 6μm to 15μm.

[0042] In implementing optoelectronic logic gate operations, the optoelectronic logic gate device of this application performs XOR or OR logic operations on the first optical signal and the second optical signal using the semiconductor photoresponse layer to obtain the photocurrent value.

[0043] The materials used in the semiconductor photoresponse layer are applicable to most two-dimensional semiconductor materials, such as two-dimensional chalcogenide transition metal compounds, binary niobium oxyhalides, and NbOBr2. The range of photoresponse varies depending on the selected material, and the optical input signal bands that can be achieved range from ultraviolet to infrared.

[0044] The optoelectronic logic gate device of this application embodiment deposits 10 nm Ti and 40 nm Au metals as source and drain electrodes at both ends of the semiconductor photoresponse layer, and detects the photocurrent value output by the source and drain electrodes. The truth value discrimination criterion for the output of the logic gate to be executed is to detect the photocurrent value output by the source and drain electrodes, compare the photocurrent value with a preset current threshold, and if the photocurrent value is greater than the preset current threshold, the logic output level of the logic gate is "1"; if the photocurrent value is less than or equal to the preset current threshold, the logic output level of the logic gate is "0".

[0045] For example, the preset current threshold is set to 10 pA.

[0046] Preferably, the lateral distance between the left high-strain region and the right high-strain region is 6μm~15μm.

[0047] Preferably, the thickness of the h-BN nanosheets is 80 nm to 100 nm.

[0048] Preferably, the semiconductor photoresponse layer is made of NbOBr2 and has a thickness of 30 nm to 50 nm.

[0049] NbOBr2 (niobium oxybromide) is a layered transition metal oxide halide with a unique crystal structure and physical properties, which has attracted widespread attention in the fields of nonlinear optics, ferroelectric materials and two-dimensional materials in recent years.

[0050] NbOBr2 is a layered material whose crystal structure is formed by niobium (Nb), oxygen (O), and bromine (Br) atoms bonded together by covalent and ionic bonds. The atoms within each layer are strongly bonded, while the interlayer interactions are weaker due to van der Waals forces. This structural characteristic makes it easy to exfoliate into two-dimensional nanosheets. The semiconductor photoresponse layer in the optoelectronic logic gate device of this application is an NbOBr2 nanosheet.

[0051] NbOBr2 has a non-centrosymmetric crystal structure, thus exhibiting a bulk photovoltaic effect. This study utilizes a design concept that applies different strain gradient directions to achieve bidirectional carrier transport in the semiconductor response layer. In contrast, most two-dimensional chalcogenide transition metal compounds are centrosymmetric and do not inherently possess a bulk photovoltaic effect; they only exhibit flexoelectric bulk photovoltaic effects after strain is applied.

[0052] Meanwhile, due to the anisotropy of NbOBr2, this material can usually be peeled into a standard rectangle, making it easier to design and fabricate devices compared to other two-dimensional semiconductor materials.

[0053] In addition, NbOBr2 has an electronic bandgap of approximately 2.2 electron volts and a photoelectric response band extending to the ultraviolet band, making it suitable for ultraviolet photoelectric logic gates and expanding the application range of visible light logic devices.

[0054] In one embodiment, the material of the semiconductor photoresponse layer is a two-dimensional chalcogenide transition metal compound or a binary niobium oxyhalide.

[0055] The semiconductor photoresponse layer in this embodiment is suitable for two-dimensional chalcogenide transition metal compounds, binary niobium oxyhalides, and most two-dimensional semiconductor materials. The range of photoresponse varies depending on the selected material, and the achievable light input signal band ranges from ultraviolet to infrared (365 nm-1550 nm).

[0056] In one embodiment, the waveguide layer is made of silicon nitride, silicon oxide, or lithium niobate.

[0057] The selection of waveguide material varies depending on the material of the semiconductor photoresponse layer. The waveguide layer material can be silicon nitride, silicon oxide, lithium niobate, etc.

[0058] In one specific embodiment, the optoelectronic logic gate device includes a silicon oxide / silicon substrate, a first silicon nitride waveguide, a second silicon nitride waveguide, a third silicon nitride waveguide, a silicon oxide cladding, an h-BN nanosheet, an NbOBr2 nanosheet, a source electrode, and a drain electrode.

[0059] This application provides a logic control method applicable to the optoelectronic logic gate device described in any of the above embodiments, such as... Figure 2 As shown, the method includes the following steps:

[0060] Step 201: Input the first optical signal and the second optical signal into the waveguide layer according to the logic gate to be executed.

[0061] In this application, the optoelectronic logic gate device can be used to implement the logic operations of XOR gate and OR gate, so the logic gate to be executed is an XOR or OR logic gate.

[0062] The waveguide layer serves as the input terminal for multiple optical signals. A laser emitter inputs a first optical signal and a second optical signal to the waveguide layer. The first optical signal and the second optical signal are transmitted through the waveguide layer. At the same time, a silicon oxide cladding is used to reduce the loss of optical signals during transmission in the device.

[0063] Step 202: Perform XOR or OR logic operations on the first optical signal and the second optical signal using the semiconductor photoresponse layer to obtain the photocurrent value.

[0064] The semiconductor photoresponse layer receives the first optical signal and the second optical signal, performs logical operations on the first optical signal and the second optical signal according to the logic gate to be executed, and then outputs the photocurrent value in the form of an electrical signal.

[0065] Photocurrent refers to the current generated within a semiconductor material in an optoelectronic device by photoexcitation under light irradiation, resulting in the directional migration of charge carriers (electron-hole pairs). It is a direct manifestation of the conversion of light energy into electrical energy.

[0066] Step 203: The photocurrent value is output using the source electrode and the drain electrode, and the photocurrent value is used to determine the output level signal of the logic gate.

[0067] The source electrode and the drain electrode output the photocurrent value, and the logic output level of the logic gate is determined based on the photocurrent value.

[0068] Specifically, when the photocurrent value is greater than the set threshold current, the logic output level of the logic gate is a high-level signal, which is "1"; if the photocurrent value is less than or equal to the set threshold current, the logic output level of the logic gate is a low-level signal, which is "0".

[0069] In one embodiment, when implementing the OR logic gate, the optoelectronic logic gate device uses the first waveguide as the first input terminal of the OR logic gate and inputs the first optical signal into the first waveguide; and uses the second waveguide as the second input terminal of the OR logic gate and inputs the second optical signal into the second waveguide.

[0070] The following is an implementation description of the OR logic gate:

[0071] like Figure 3 As shown, when executing the OR logic gate, a laser transmitter inputs a first optical signal to the first waveguide and a second optical signal to the second waveguide. The first optical signal in the first waveguide is input 1 of the OR logic gate, and the second optical signal in the second waveguide is input 2 of the OR logic gate. The truth criterion for the OR logic gate input is the laser power. When the laser power is greater than the preset laser power, the logic is "1"; when the laser power is less than or equal to the preset laser power, the logic is "0". When the first and second optical signals input to the first and second waveguides are both logic "0", the output current is less than the threshold current (10 pA), and the output is logic "0". When any optical signal in the first and second waveguides is logic "1" or both are "1", the output current is greater than the threshold current (10 pA), and the output is logic "1".

[0072] In one embodiment, when implementing the XOR logic gate, the optoelectronic logic gate device uses the first waveguide as the first input terminal of the XOR logic gate and inputs the first optical signal into the first waveguide; and uses the third waveguide as the second input terminal of the XOR logic gate and inputs the second optical signal into the third waveguide.

[0073] The following is an implementation description of the XOR logic gate:

[0074] like Figure 4As shown, when executing the XOR logic gate, a laser emitter inputs a first optical signal to the first waveguide and a second optical signal to the third waveguide. The first optical signal in the first waveguide is input 1 of the XOR logic gate, and the second optical signal in the third waveguide is input 2 of the XOR logic gate. The truth criterion for the input of the OR logic gate is the laser power. When the laser power is greater than a preset laser power, the logic is "1"; when the laser power is less than or equal to the preset laser power, the logic is "0". When the first and second optical signals input to the first and third waveguides are both logic "0", the output current is less than the threshold current (10 pA), and the output logic is "0". When the logic of the first and second optical signals in the first and third waveguides is different, the output current is greater than the threshold current (10 pA), and the output logic is "1". When the first and second optical signals input to the first and third waveguides are both logic "1", the output current is less than the threshold current (10 pA), and the output logic is "0".

[0075] In one embodiment, the wavelength range of the first optical signal and the second optical signal is 365 nm to 1550 nm.

[0076] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A photoelectric logic gate device, characterized in that, The device includes: a substrate, a waveguide layer, an upper cladding layer, h-BN nanosheets, a semiconductor photoresponse layer, and source and drain electrodes deposited at both ends of the semiconductor photoresponse layer, wherein the substrate includes silicon and silicon oxide deposited on the silicon, the upper surface of the waveguide layer is flush with the upper surface of the silicon oxide, and the waveguide layer includes a first waveguide, a second waveguide, and a third waveguide, wherein: The semiconductor photoresponse layer is dry-transfer stacked directly above the h-BN nanosheet, forming a high-strain region on the left, a strain-free region in the middle, and a high-strain region on the right. The high-strain region on the left corresponds vertically to the first waveguide, the strain-free region in the middle corresponds vertically to the second waveguide, and the high-strain region on the right corresponds vertically to the third waveguide. The semiconductor photoresponse layer above the edge of the h-BN nanosheet bends and accumulates strain at the edge. Stress is applied to the two edges of the semiconductor photoresponse layer in contact with each other, forming two high-strain regions. Thus, the semiconductor photoresponse layer forms three regions: a high-strain region on the left, a strain-free region in the middle, and a high-strain region on the right.

2. The optoelectronic logic gate device according to claim 1, characterized in that, The lateral distance between the high-strain region on the left and the high-strain region on the right is 6μm to 15μm.

3. The optoelectronic logic gate device according to claim 1, characterized in that, The thickness of the h-BN nanosheets is 80 nm to 100 nm.

4. The optoelectronic logic gate device according to claim 1, characterized in that, The semiconductor photoresponse layer is made of NbOBr2 and has a thickness of 30 nm to 50 nm.

5. The optoelectronic logic gate device according to claim 1, characterized in that, The semiconductor photoresponse layer is made of a two-dimensional chalcogenide transition metal compound or a binary niobium oxyhalide.

6. The optoelectronic logic gate device according to claim 1, characterized in that, The waveguide layer is made of one of silicon nitride, silicon oxide, or lithium niobate.

7. A logic control method applied to the optoelectronic logic gate device according to any one of claims 1 to 6, characterized in that, The method includes: According to the logic gate to be executed, the first optical signal and the second optical signal are input into the waveguide layer; The first optical signal and the second optical signal are subjected to XOR or OR logic operations using the semiconductor photoresponse layer to obtain the photocurrent value; The photocurrent value is output using the source electrode and the drain electrode, and the photocurrent value is used to determine the logic output level of the logic gate.

8. The logic control method according to claim 7, characterized in that, When the optoelectronic logic gate device implements the OR logic gate... The first waveguide is used as the first input terminal of the OR logic gate, and the first optical signal is input into the first waveguide. The second waveguide is used as the second input terminal of the OR logic gate, and the second optical signal is input into the second waveguide.

9. The logic control method according to claim 7, characterized in that, When the optoelectronic logic gate device implements the XOR logic gate... The first waveguide is used as the first input terminal of the XOR logic gate, and the first optical signal is input into the first waveguide. The third waveguide is used as the second input terminal of the XOR logic gate, and the second optical signal is input into the third waveguide.

10. The logic control method according to claim 7, characterized in that, The wavelength range of the first optical signal and the second optical signal is 365 nm to 1550 nm.

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