Display panel and display device

Abstract

The invention discloses a display panel and a display device. A pixel circuit of the display panel comprises a driving transistor, a compensation transistor and a storage capacitor which are connected, the driving transistor comprises a driving active part and a driving grid electrode, the compensation transistor comprises a compensation active part and a compensation grid electrode, and the compensation active part and the driving active part are made of different materials. The storage capacitor comprises a first pole plate and a second pole plate which are oppositely arranged, the first pole plate and the driving grid are made of the same material, and the second pole plate and the compensation grid are made of the same material; the first polar plate of the storage capacitor is prepared from the material of the driving gate, and the second polar plate of the storage capacitor is prepared from the material of the compensation gate, that is, the materials of the two capacitor polar plates of the storage capacitor are metal materials, so that the technical problem of insufficient conductor of the capacitor polar plates is eliminated, and the capacitance of the storage capacitor is ensured; and the display effect of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology is a new display technology that has gradually attracted people's attention with its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and occupies a certain position in the field of panel display technology.

[0003] In the current display device using LTPO (Low Temperature Polysilicon Oxide, LTPO) technology, one plate of the storage capacitor is made of the material of the first gate layer, and the other plate is made of the material of the oxide semiconductor layer. When a capacitor plate with a larger area is made of oxide semiconductor, there may be a technical problem in which the capacitance of the storage capacitor is reduced due to insufficient conductivity of the capacitor plate, resulting in abnormal display of the display panel. Summary of the Invention

[0004] The present application provides a display panel and a display device to improve the technical problem of abnormal display on existing display panels.

[0005] To solve the above problem, the technical solution provided by this application is as follows:

[0006] In a first aspect, the present application provides a display panel comprising a plurality of sub-pixels, at least one of the sub-pixels comprising a connected pixel circuit and a light-emitting device, wherein the pixel circuit comprises:

[0007] A driving transistor including a driving active portion and a driving gate

[0008] a compensation transistor connected to the driving transistor, the compensation transistor comprising a compensation active portion and a compensation gate, wherein the compensation active portion and the driving active portion are made of different materials;

[0009] A storage capacitor is connected to the driving transistor and the compensation transistor, and the storage capacitor includes a first plate and a second plate arranged opposite to each other, the first plate is made of the same material as the driving gate, and the second plate is made of the same material as the compensation gate.

[0010] In a second aspect, the present application also proposes a display device, which includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0012] Figure 1 A simplified structural diagram of the display panel of this application;

[0013] Figure 2 This is an equivalent circuit diagram of a pixel circuit in the display panel of this application;

[0014] Figure 3 This is a schematic diagram of the film layer in the display panel of this application;

[0015] Figure 4 A diagram showing the stacking of film layers of multiple repeating units in a display panel of this application;

[0016] Figure 5 for Figure 4 A structural diagram of the first gate layer of the repeating unit;

[0017] Figure 6 for Figure 4 A structural diagram of the first active layer of the repeating unit;

[0018] Figure 7 for Figure 4 A stacking diagram of the first gate layer and the first active layer of the repeating unit;

[0019] Figure 8 for Figure 4 Structural diagram of the light-shielding layer of the repeating unit;

[0020] Figure 9 for Figure 4 A first structural diagram of the second active layer of the repeating unit;

[0021] Figure 10 for Figure 4 A first structural diagram of the second gate layer of the repeating unit;

[0022] Figure 11 for Figure 4 A first stacking diagram of a first gate layer, a first active layer, a second active layer and a second gate layer in a repeating unit;

[0023] Figure 12 for Figure 4 A first stacking diagram of a light shielding layer, a first gate layer, a first active layer, a second active layer and a second gate layer in a repeating unit;

[0024] Figure 13 for Figure 4 A second structural diagram of the second active layer of the repeating unit;

[0025] Figure 14 for Figure 4 A second structural diagram of the second gate layer of the repeating unit;

[0026] Figure 15 for Figure 4 A second stacking diagram of the light shielding layer, the first gate layer, the first active layer, the second active layer and the second gate layer in the repeating unit;

[0027] Figure 16 for Figure 4 A structural diagram of the first source and drain layer of the repeating unit;

[0028] Figure 17 for Figure 4 A stacked diagram of a light shielding layer, a first gate layer, a first active layer, a second active layer, a second gate layer and a first source and drain layer in a repeating unit;

[0029] Figure 18 for Figure 4 A structural diagram of the second source and drain layer of the repeating unit;

[0030] Figure 19 for Figure 4 A stacked diagram of a light shielding layer, a first gate layer, a first active layer, a second active layer, a second gate layer, a first source-drain electrode layer, and a second source-drain electrode layer in a repeating unit;

[0031] Figure 20 for Figure 4 Stack diagram of the anode layer;

[0032] Figure 21 A diagram showing the film layer stacking of a single repeating unit in a panel for this application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0034] See also Figures 1 to 21The present application provides a display panel 100, which includes a plurality of sub-pixels PL, at least one sub-pixel PL includes a connected pixel circuit PC and a light-emitting device EL, and the pixel circuit PC includes a connected driving transistor T1, a compensation transistor T3 and a storage capacitor Cst.

[0035] In this embodiment, the driving transistor T1 includes a driving active portion T1A and a driving gate T1G, the compensation transistor T3 includes a compensation active portion T3A and a compensation gate T3G, the compensation active portion T3A and the driving active portion T1A are made of different materials, and the storage capacitor Cst includes a first plate Cst1 and a second plate Cst2 arranged opposite to each other, the first plate Cst1 and the driving gate T1G are made of the same material, and the second plate Cst2 and the compensation gate T3G are made of the same material.

[0036] In the present application, the first plate of the storage capacitor Cst is prepared using the material of the driving gate T1G, and the second plate Cst2 of the storage capacitor Cst is prepared using the material of the compensation gate T3G. That is, the materials of the two capacitor plates of the storage capacitor Cst are both metal materials, thereby eliminating the technical problem of insufficient conductivity of the capacitor plates, ensuring the capacitance of the storage capacitor Cst, and improving the display effect of the display panel 100.

[0037] For example, the display panel 100 may include a base substrate 110, a first active layer 123 provided on the base substrate 110, a first gate layer 125 provided on a side of the first active layer 123 away from the base substrate 110, a second active layer 127 provided on a side of the first gate layer 125 away from the base substrate 110, and a second gate layer 129 provided on a side of the second active layer 127 away from the base substrate 110. The driving active portion T1A of the present application may be located on the first active layer 123, and the driving gate T1G and the first electrode Cst1 may be located on the first active layer 123. In the first gate layer 125, the compensation active portion T3A can be located in the second active layer 127, and the compensation gate T3G and the second electrode plate Cst2 can be located in the second gate layer 129, which is equivalent to using the first gate layer 125 to prepare the first electrode plate Cst1 and using the second gate layer 129 to prepare the second electrode plate Cst2, so that the materials of the two capacitor plates of the storage capacitor Cst are both metal materials, eliminating the technical problem of insufficient conductivity of the capacitor plates, ensuring the capacitance of the storage capacitor Cst, and improving the display effect of the display panel 100.

[0038] The technical solution of this application is described below based on specific embodiments.

[0039] See also Figure 1The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display portion 200 is disposed within the display area AA. Optionally, the non-display area NA surrounds the display area AA, enclosing the display area AA. The display area AA is the region within the display panel 100 used for display functions, and contains a plurality of sub-pixels PX therein to implement these functions. The non-display area NA may be a border region of the display panel 100, and may contain functional components that assist the sub-pixels PX within the display area AA in performing display functions.

[0040] See also Figure 1 The lower side of the display area AA is provided with a binding terminal 400. The binding terminal 400 can be connected to an external circuit and transmits the signal input from the external circuit to the data line, thereby driving the display panel 100 to display the image. For example, the binding terminal 400 can be bonded to a chip or a chip-on-film to provide power and driving signals to the display panel 100.

[0041] In this embodiment, the gate circuit 300 is arranged in the non-display area NA, and the gate circuit 300 can be arranged on both sides of the display area AA; the gate circuit 300 may include multiple cascaded gate driving units, and the structure of the gate driving unit is not specifically limited in this application.

[0042] In this embodiment, a plurality of light-emitting devices EL and a pixel circuit PC for driving the light-emitting devices EL may be arranged in an array in the display area AA. The pixel circuit PC may be a 7T1C, 7T2C, 8T1C, 8T2C, 8T3C, 8T4C or other pixel circuit PC. The following embodiment uses an 8T2C pixel circuit PC as an example for description.

[0043] See also Figure 2 The pixel circuit PC may include a switching transistor T2, a driving transistor T1, a compensation transistor T3, a first reset transistor T4, a second reset transistor T7, a node reset transistor T8, a first light-emitting transistor T5, a second light-emitting transistor T6, a storage capacitor Cst and a boost capacitor Cboost, and the storage capacitor Cst includes a first plate Cst1 and a second plate Cst2.

[0044] See also Figure 2, the drain of the switching transistor T2 is connected to the data line Data, the source of the switching transistor T2 is connected to the first node A, and the switching gate T2G of the switching transistor T2 is connected to the switching control line Pscan1; the drain of the driving transistor T1 is connected to the first node A, the source of the driving transistor T1 is connected to the second node B, and the driving gate T1G of the driving transistor T1 is connected to the third node Q; the drain of the compensation transistor T3 is connected to the third node Q, the source of the compensation transistor T3 is connected to the second node B, and the compensation gate T3G of the compensation transistor T3 is connected to the compensation control line Nscan1; the drain of the first reset transistor T4 is connected to the first reset signal line Vi1, the source of the first reset transistor T4 is connected to the third node Q, and the gate T4G of the first reset transistor T4 is connected to the second reset control line Nscan2; the drain of the second reset transistor T7 is connected to the second reset signal line Vi2, the source of the second reset transistor T7 is connected to the anode of the light emitting device EL, and the gate T7G of the second reset transistor T7 is connected to the first reset control line Pscan 2; a drain of the first light-emitting transistor T5 is connected to the high potential line VDD, a source of the first light-emitting transistor T5 is connected to the first node A, and a first light-emitting gate T5G of the first light-emitting transistor T5 is connected to the light-emitting control line EM; a drain of the second light-emitting transistor T6 is connected to the second node B, a source of the second light-emitting transistor T6 is connected to the anode of the light-emitting device EL, and a second light-emitting gate T6G of the second light-emitting transistor T6 is connected to the light-emitting control line EM; a drain of the node reset transistor T8 is connected to the node reset signal line Vi3, a source of the node reset transistor T8 is connected to the first node A, and a third reset gate T8G of the node reset transistor T8 is connected to the first reset control line Pscan2; a first plate Cst1 of the storage capacitor Cst is connected to the third node Q, and a second plate Cst1 of the storage capacitor Cst is connected to the high potential line VDD; one plate of the boost capacitor Cboost is connected to the switch control line Pscan1, and the other plate of the boost capacitor Cboost is connected to the third node Q; and a cathode of the light-emitting device EL is connected to the low potential line VSS.

[0045] It should be noted that the switch transistors T2 in different sub-pixels PX are connected to different data signal lines, and this application only takes one of them as an example for description.

[0046] It should be noted that the light-emitting device EL of the present application can be an organic light-emitting diode, Mini LED, MicroLED, a conventional-sized LED or other light-emitting source.

[0047] In this embodiment, the high potential line VDD is used to provide a constant high voltage level to the pixel circuit PC, and the low potential line VSS is used to provide a constant low voltage level to the pixel circuit PC.

[0048] In this embodiment, the switching transistor T2, the driving transistor T1, the second reset transistor T7, the node reset transistor T8, the first light-emitting transistor T5, the second light-emitting transistor T6, the compensation transistor T3 and the first reset transistor T4 can be P-type transistors or N-type transistors; this application is described by taking the switching transistor T2, the driving transistor T1, the second reset transistor T7, the node reset transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 as P-type transistors, and the compensation transistor T3 and the first reset transistor T4 as N-type transistors as an example.

[0049] In this embodiment, the source is only the output end of the present application, and the drain is only the input end of the present application, and the two are only distinguished in name.

[0050] In the following embodiments, the first direction is perpendicular to the extending direction of the data line, and the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90°. For example, the first direction X is the horizontal direction, and the second direction Y is the vertical direction.

[0051] The following is for Figure 2 The structure of the pixel circuit PC of this application is described.

[0052] See also Figure 3 The display area AA and non-display area NA of the display panel 100 may include a base substrate 110 and an array drive layer 120 disposed on the base substrate 110. Within the display area AA, the display panel 100 may also include a pixel definition layer PDL disposed on the array drive layer 120, a light-emitting device layer disposed on the same layer as the pixel definition layer PDL, and an encapsulation layer TFE disposed on the pixel definition layer PDL. The following primarily describes the film layer structure within the display area AA.

[0053] In this embodiment, the base substrate 110 supports various layers provided on the base substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent base substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque base substrate as well as a transparent base substrate can be used.

[0054] In this embodiment, the base substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The base substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials for the flexible substrate include, but are not limited to, polyimide (PI).

[0055] In this embodiment, the base substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 that are stacked. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material, such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0056] See also Figure 3 The array driving layer 120 may include a plurality of thin film transistors, which may be of an etch-stop type or a back-channel etch type, or may be classified into a bottom-gate thin film transistor, a top-gate thin film transistor, and other structures according to the position of the gate electrode and the active layer, or may be classified into an N-type thin film transistor or a P-type thin film transistor according to the performance of the thin film transistor; wherein, Figure 3 The thin film transistor does not represent Figure 2 The structural diagram of any transistor is merely a schematic diagram of the various film layers of the display panel 100 of the present application.

[0057] See also Figure 3 The array driving layer 120 may include a light shielding layer 121 disposed on the base substrate 110, a blocking insulating layer BF disposed on the light shielding layer 121, a buffer layer 122 disposed on the blocking insulating layer BF, a first active layer 123 disposed on the buffer layer 122, a first insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first insulating layer 124, a second insulating layer 126 disposed on the first gate layer 125, a second active layer 127 disposed on the second insulating layer 126, and a first active layer 127 disposed on the second active layer 127. Three insulating layers 128, a second gate layer 129 arranged on the third insulating layer 128, a fourth insulating layer 130 arranged on the second gate layer 129, a first source and drain layer 131 arranged on the fourth insulating layer 130, a first flat layer 132 arranged on the first source and drain layer 131, a second source and drain layer 133 arranged on the first flat layer 132, and a second flat layer 134 arranged on the second source and drain layer 133, a light-emitting device layer and a pixel definition layer PDL arranged on the second flat layer 134, and an encapsulation layer TFE arranged on the pixel definition layer PDL.

[0058] See also Figure 3 The light shielding layer 121 is provided on the second barrier layer 114 and is used to block external light from entering the thin film transistor from the bottom. The material of the light shielding layer 121 can be made of a black light shielding material, such as a black light shielding metal or a black organic material.

[0059] See also Figure 3The buffer layer 122 is arranged on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may include a compound composed of nitrogen, silicon and oxygen elements, such as a single-layer silicon oxide film layer, or a silicon oxide-silicon nitride stacked structure.

[0060] In this embodiment, the light shielding layer 121 may also be embedded in the buffer layer 122, for example Figure 3 Two buffer layers 122 may be provided.

[0061] See also Figure 3 The first active layer 123 is arranged on the buffer layer 122, and the second active layer 127 is arranged on the second insulating layer 126. In the present application, the material of the first active layer 123 can be a silicon semiconductor, such as low-temperature polycrystalline silicon, and the material of the second active layer 127 can be an oxide semiconductor, such as metal oxide. The pixel circuit PC has N-type transistors and P-type transistors, so the display area AA of the present application is provided with metal oxide semiconductors and low-temperature polycrystalline silicon semiconductors.

[0062] See also Figure 3 The first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 are respectively arranged on the corresponding metal layer or semiconductor layer, and are separated by different layers of metal layers or semiconductor layers; the material of the first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 can be an inorganic substance composed of at least two elements in silicon oxynitride or an organic material with flatness, or it can be a stack of single or multiple film layers.

[0063] See also Figure 3 The first gate layer 125 and the second gate layer 129 are respectively disposed on corresponding insulating layers. The materials of the first gate layer 125 and the second gate layer 129 can be copper, molybdenum or molybdenum-titanium alloy.

[0064] See also Figure 3 The first source-drain electrode layer 131 is arranged on the fourth insulating layer 130, and the second source-drain electrode layer 133 is arranged on the first flat layer 132. The materials of the first source-drain electrode layer 131 and the second source-drain electrode layer 133 can be copper, molybdenum, titanium or molybdenum-titanium alloy, or a titanium-aluminum-titanium stacked structure.

[0065] See also Figure 3 The first flat layer 132 and the second flat layer 134 are laid as a whole layer to ensure the flatness of the film layer of the array driving layer 120. The materials of the first flat layer 132 and the second flat layer 134 can be inorganic substances composed of nitride oxide silicon or organic materials with flatness.

[0066] See also Figure 3The light emitting device layer may include a plurality of light emitting devices EL, each of which includes an anode AN connected to a pixel circuit, a light emitting unit, and a cathode CA.

[0067] See also Figure 4 The display panel 100 includes a plurality of repeating units RU arranged along a first direction X and a second direction Y, each repeating unit RU having two sub-pixels PX, and patterns of at least part of the film layers in two pixel circuits PC in one repeating unit RU are symmetrically arranged with a center line of the repeating unit RU as an axis, and the center line may be parallel to the second direction Y.

[0068] It should be noted that due to limitations such as process and equipment, there are slight differences in the film layer patterns in different pixel circuits PC of this application in actual products. Therefore, the symmetrical setting of this application is only a symmetrical setting within the error range; at the same time, in order to set the connection points with the upper structure, some structures widen the pattern in the area where the connection points are located, resulting in an asymmetric pattern setting, which is also within the error range.

[0069] It should be noted that the structure and film layer structure of the above-mentioned pixel circuit PC of the present application are applicable to all sub-pixels PX of the present application.

[0070] In the following embodiments, the structure of each film layer in two pixel circuits PC in a repeating unit RU is taken as an example to describe the technical solution of the present application.

[0071] See also Figure 5 The first gate layer 125 includes a first reset signal line Vi1, a switch control line Pscan1, a light emitting control line EM and a first reset control line Pscan2 extending along the first direction X. The first reset signal line Vi1, the switch control line Pscan1, the light emitting control line EM and the first reset control line Pscan2 are arranged in sequence along the second direction Y, and the first reset signal line Vi1, the switch control line Pscan1, the light emitting control line EM and the first reset control line Pscan2 in a repeating unit RU are connected to each other.

[0072] See also Figure 5 The first gate layer 125 also includes a first plate Cst1 of a storage capacitor Cst arranged between the switch control line Pscan1 and the light-emitting control line EM. The first plate Cst1 and the switch control line Pscan1 and the light-emitting control line EM are spaced apart, and the distance between the first plate Cst1 and the switch control line Pscan1 is greater than the distance between the first plate Cst1 and the light-emitting control line EM; at the same time, the two first plates Cst1 in a repeating unit RU are spaced apart.

[0073] See also Figure 6The first active layer 123 includes a switch active portion T2A of the switch transistor T2, a first light emitting active portion T5A of the first light emitting transistor T5, a driving active portion T1A of the driving transistor T1, a second light emitting active portion T6A of the second light emitting transistor T6, a second reset active portion T7A of the second reset transistor T7, a third reset active portion T8A of the node reset transistor T8, a first extension segment ET1, and a second extension segment ET2.

[0074] See also Figure 6 The switch active portion T2A, the first light-emitting active portion T5A, and the driving active portion T1A are connected to the first connection point N1, the driving active portion T1A and the second light-emitting active portion T6A are connected to the second connection point N2, the first extension segment ET1, the second light-emitting active portion T6A, and the second reset active portion T7A are connected to the third connection point N3, the first extension segment ET1 extends from the third connection point N3 to a side close to the first light-emitting active portion T5A, the third reset active portion T8A is spaced apart from the above active portions and is located between the first extension segment ET1 and the first light-emitting active portion T5A, the second extension segment ET2 is connected to the first connection point N1, and is located between the driving active portion T1A and the first light-emitting active portion T5A, and the two first light-emitting active portions T5A in a repeating unit RU are connected at the end away from the first node.

[0075] See also Figure 6 The switch active portion T2A, the first light emitting active portion T5A, the second light emitting active portion T6A, the second reset active portion T7A, and the third reset active portion T8A extend along the second direction Y and are strip-shaped, the first extension segment ET1 extends along the first direction X and is strip-shaped, and the driving active portion T1A can be U-shaped.

[0076] See also Figure 7 The light emitting control line EM and the first light emitting active portion T5A have an overlapping portion. The light emitting control line EM in the overlapping portion is multiplexed as the first light emitting gate T5G. The first light emitting active portion T5A in the overlapping portion is the channel of the first light emitting transistor T5. An end of the first light emitting active portion T5A away from the first connection point N1 is multiplexed as the drain T5D of the first light emitting transistor T5, and an end of the first light emitting active portion T5A close to the first connection point N1 is multiplexed as the source T5S of the first light emitting transistor T5. That is, the structure in the area where the first connection point N1 is located is the first node A in the pixel circuit PC.

[0077] See also Figure 7The light emitting control line EM and the second light emitting active portion T6A have an overlapping portion. The light emitting control line EM in the overlapping portion is multiplexed as the second light emitting gate T6G. The second light emitting active portion T6A in the overlapping portion is the channel of the second light emitting transistor T6. An end of the second light emitting active portion T6A away from the second connection point N2 is multiplexed as the source T6S of the second light emitting transistor T6, and an end of the second light emitting active portion T6A close to the second connection point N2 is multiplexed as the drain T6D of the second light emitting transistor T6. That is, the structure of the area where the second connection point N2 is located is the second node B in the pixel circuit PC, and the structure of the area where the third connection point N3 is located is the position connected to the anode AN in the pixel circuit PC.

[0078] See also Figure 7 The first reset control line Pscan2 and the second reset active portion T7A have an overlapping portion. The first reset control line Pscan2 in the overlapping portion is multiplexed as the second reset gate T7G. The second reset active portion T7A in the overlapping portion is the channel of the second reset transistor T7. An end of the second reset active portion T7A close to the third connection point N3 is multiplexed as the source T7S of the second reset transistor T7, and an end of the second reset active portion T7A far from the third connection point N3 is multiplexed as the drain T7D of the second reset transistor T7.

[0079] See also Figure 7 The first reset control line Pscan2 and the third reset active portion T8A have an overlapping portion. The first reset control line Pscan2 in the overlapping portion is multiplexed as the third reset gate T8G. The third reset active portion T8A in the overlapping portion is the channel of the node reset transistor T8. An end of the third reset active portion T8A close to the emission control line EM is multiplexed as the source T8S of the node reset transistor T8, and an end of the third reset active portion T8A far from the emission control line EM is multiplexed as the drain T8D of the node reset transistor T8.

[0080] See also Figure 7 The switch control line Pscan1 and the switch active portion T2A have an overlapping portion. The switch control line Pscan1 in the overlapping portion is multiplexed as the switch gate T2G. The switch active portion T2A in the overlapping portion is the channel of the switch transistor T2. One end of the switch active portion T2A close to the first connection point N1 is multiplexed as the source T2S of the switch transistor T2, and one end of the switch active portion T2A far from the first connection point N1 is multiplexed as the drain T2D of the switch transistor T2.

[0081] See also Figure 8The light-shielding layer 121 includes a reset light-shielding portion T4L, a compensation light-shielding portion T3L, and a drive light-shielding portion T1L. The reset light-shielding portion T4L and the compensation light-shielding portion T3L both extend along the first direction X, and in the first direction X, the drive light-shielding portions T1L in two adjacent sub-pixels PX are connected, the reset light-shielding portions T4L in two adjacent sub-pixels PX are connected, and the compensation light-shielding portions T3L in two adjacent sub-pixels PX are connected.

[0082] exist Figure 8 In the structure, the light-shielding layer 121 further includes two first connecting segments CT1 provided on both sides of the driven light-shielding portion T1L along the second direction Y. The first connecting segments CT1 extend along the second direction Y, and the first connecting segments CT1 connect the driven light-shielding portion T1, the reset light-shielding portion T4L and the compensation light-shielding portion T3L. At the same time, the two driven light-shielding portions T1 along the second direction Y are connected through the first connecting segments CT1, that is, the driven light-shielding portion T1, the reset light-shielding portion T4L and the compensation light-shielding portion T3L in different sub-pixels PL in the light-shielding layer 121 are connected to each other.

[0083] It should be noted that the first connecting section CT1, the driving shading portion T1, the reset shading portion T4L and the compensation shading portion T3L can transmit the same signal, for example, transmit a constant voltage, and serve as a shielding structure of the above-mentioned device; alternatively, the driving shading portion T1, the reset shading portion T4L and the compensation shading portion T3L are not connected, and they can transmit different control signals, for example, the reset shading portion T4L can serve as the bottom gate of the first reset transistor T4, and the compensation shading portion T3L can serve as the bottom gate of the compensation transistor T3.

[0084] exist Figure 9 In the structure, the second active layer 127 includes a first reset active portion T4A of the first reset transistor T4 and a compensation active portion T3A of the compensation transistor T3. The first reset active portion T4A and the compensation active portion T3A both extend along the second direction Y and are in a long strip shape. The first reset active portion T4A and the compensation active portion T3A are connected to a fourth connection point N4.

[0085] exist Figure 9 In the structure, the second active layer 127 further includes a third extension segment ET3, and the third extension segment ET3 connects ends of adjacent compensation active portions T3A in two adjacent repeating units RU that are away from the fourth connection point N4.

[0086] exist Figure 10 In the structure, the second gate layer 129 includes second reset control lines Nscan2 and compensation control lines Nscan1 arranged at intervals along the second direction Y, and the second reset control lines Nscan2 and compensation control lines Nscan1 both extend along the first direction X.

[0087] exist Figure 12In the structure, the second reset control line Nscan2 and the reset light shielding portion T4L both have an overlapping portion with the first reset active portion T4A, and the second reset control line Nscan2 in the overlapping portion is multiplexed as the first reset gate T4G. The first reset active portion T4A in the overlapping portion is the channel of the first reset transistor T4, and an end of the first reset active portion T4A close to the fourth connection point N4 is multiplexed as the source T4S of the first reset transistor T4, and an end of the first reset active portion T4A far from the fourth connection point N4 is multiplexed as the drain T4D of the first reset transistor T4. That is, the structure in the area where the fourth connection point N4 is located is the third node Q in the pixel circuit PC.

[0088] exist Figure 12 In the structure, the compensation light shielding portion T3L and the compensation control line Nscan1 both have an overlapping portion with the compensation active portion T3A of the compensation transistor T3, and the compensation control line Nscan1 in the overlapping portion is multiplexed as the compensation gate T3G, the compensation active portion T3A in the overlapping portion is the channel of the compensation transistor T3, an end of the compensation active portion T3A close to the fourth connection point N4 is multiplexed as the drain T3D of the compensation transistor T3, and an end of the compensation active portion T3A far from the fourth connection point N4 is multiplexed as the source T3S of the compensation transistor T3.

[0089] exist Figure 12 In the structure, the second reset control line Nscan2 overlaps with the reset light shielding portion T4L, and the compensation control line Nscan1 overlaps with the compensation light shielding portion T3L. Furthermore, the area of ​​the overlap between the second reset control line Nscan2 and the active portion of the first reset transistor T4 is greater than the area of ​​the overlap between the reset light shielding portion T4L and the active portion of the first reset transistor T4. Furthermore, the area of ​​the overlap between the compensation light shielding portion T3L and the active portion of the compensation transistor T3 is greater than the area of ​​the overlap between the compensation control line Nscan1 and the active portion of the compensation transistor T3.

[0090] exist Figure 10 and Figure 11 In the structure, the second gate layer 129 also includes a second plate Cst2 of the storage capacitor Cst, the second plate Cst2 is arranged between the compensation control line Nscan1 and the node reset signal line Vi3, and the two second plates Cst2 in a repeating unit RU are connected, and the second plate Cst2 is arranged opposite to the first plate Cst1, the outer contour area of ​​the first plate Cst1 can be smaller than the outer contour area of ​​the second plate Cst2, and the outer contour area of ​​the second plate Cst2 is smaller than the outer contour area of ​​the driving light shielding portion T1L.

[0091] exist Figure 10 and Figure 11In the structure, the second gate layer 129 also includes a node reset signal line Vi3, the node reset signal line Vi3 and the light-emitting control line EM have an overlapping portion, and a fourth extension segment ET4 is also provided on the node reset signal line Vi3, and the fourth extension segment ET4 extends along the second direction toward a direction away from the first reset active portion T4A and the compensation active portion T3A.

[0092] It should be noted that the fourth extension segment ET4 can be the reset extension segment of the present application, which extends to one end away from the storage capacitor Cst, and the reset extension segment is away from one end of the node reset signal line Vi3 and is arranged adjacent to the drain of the node reset transistor T8.

[0093] exist Figure 13 In the structure, the second active layer 127 includes a first reset active portion T4A of the first reset transistor T4 and a compensation active portion T3A of the compensation transistor T3. The first reset active portion T4A and the compensation active portion T3A both extend along the second direction Y and are in a long strip shape. The first reset active portion T4A and the compensation active portion T3A are connected to a fourth connection point N4.

[0094] exist Figure 13 In the structure, the second active layer 127 further includes a third extension segment ET3, and the third extension segment ET3 connects ends of adjacent compensation active portions T3A in two adjacent repeating units RU that are away from the fourth connection point N4.

[0095] exist Figure 13 and Figure 15 In the structure, the second active layer 127 also includes a node reset signal line Vi3, the node reset signal line Vi3 and the light-emitting control line EM have an overlapping portion, and a fourth extension segment ET4 is also provided on the node reset signal line Vi3, and the fourth extension segment ET4 extends along the second direction toward a direction away from the first reset active portion T4A and the compensation active portion T3A.

[0096] It should be noted that the fourth extension segment ET4 can be the reset extension segment of the present application, which extends to one end away from the storage capacitor Cst, and the reset extension segment is away from one end of the node reset signal line Vi3 and is arranged adjacent to the drain of the node reset transistor T8.

[0097] exist Figure 14 In the structure, the second gate layer 129 includes second reset control lines Nscan2 and compensation control lines Nscan1 arranged at intervals along the second direction Y, and the second reset control lines Nscan2 and compensation control lines Nscan1 both extend along the first direction X.

[0098] Please refer to the following for details: Figure 12The second reset control line Nscan2 and the reset light shielding portion T4L both have an overlapping portion with the first reset active portion T4A, and the second reset control line Nscan2 in the overlapping portion is multiplexed as the first reset gate T4G. The first reset active portion T4A in the overlapping portion is the channel of the first reset transistor T4. An end of the first reset active portion T4A close to the fourth connection point N4 is multiplexed as the source T4S of the first reset transistor T4, and an end of the first reset active portion T4A far from the fourth connection point N4 is multiplexed as the drain T4D of the first reset transistor T4. That is, the structure in the area where the fourth connection point N4 is located is the third node Q in the pixel circuit PC.

[0099] Please refer to the following for details: Figure 12 The compensation light shielding portion T3L and the compensation control line Nscan1 both have an overlapping portion with the compensation active portion T3A of the compensation transistor T3, and the compensation control line Nscan1 in the overlapping portion is multiplexed as the compensation gate T3G. The compensation active portion T3A in the overlapping portion is the channel of the compensation transistor T3, and one end of the compensation active portion T3A close to the fourth connection point N4 is multiplexed as the drain T3D of the compensation transistor T3, and one end of the compensation active portion T3A far from the fourth connection point N4 is multiplexed as the source T3S of the compensation transistor T3.

[0100] Please refer to the following for details: Figure 12 The second reset control line Nscan2 overlaps with the reset light shielding portion T4L, and the compensation control line Nscan1 overlaps with the compensation light shielding portion T3L. Furthermore, the area of ​​the overlap between the second reset control line Nscan2 and the active portion of the first reset transistor T4 is greater than the area of ​​the overlap between the reset light shielding portion T4L and the active portion of the first reset transistor T4. Furthermore, the area of ​​the overlap between the compensation light shielding portion T3L and the active portion of the compensation transistor T3 is greater than the area of ​​the overlap between the compensation control line Nscan1 and the active portion of the compensation transistor T3.

[0101] exist Figure 14 and Figure 15 In the structure, the second gate layer 129 also includes a second plate Cst2 of the storage capacitor Cst, the second plate Cst2 is arranged between the compensation control line Nscan1 and the node reset signal line Vi3, and the two second plates Cst2 in a repeating unit RU are connected, and the second plate Cst2 is arranged opposite to the first plate Cst1, the outer contour area of ​​the first plate Cst1 can be smaller than the outer contour area of ​​the second plate Cst2, and the outer contour area of ​​the second plate Cst2 is smaller than the outer contour area of ​​the driving light shielding portion T1L.

[0102] See also Figure 11 and Figure 15In order to compress the space in the second direction Y, in the present application, in two adjacent repeating units RU in the second direction Y, the first reset control line Pscan2, the first reset signal line Vi1, the second reset control line Nscan2, the switch control line Pscan1, and the compensation control line Nscan1 are arranged along the second direction Y, and the spacing between the first reset signal line Vi1, the second reset control line Nscan2, the switch control line Pscan1, and the compensation control line Nscan1 is small, for example, it can be smaller than the spacing between the first reset control line Pscan2 and the first reset signal line Vi1.

[0103] At the same time, the first reset control line Pscan2 and the first reset signal line Vi1 of the present application are provided with more connection holes. In order to avoid the control line or the signal line from overlapping with the connection holes, the present application sets the node reset signal line Vi3 between the first reset control line Pscan2 and the storage capacitor Cst, for example Figure 11 and Figure 15 In the embodiment, the node reset signal line Vi3 may overlap with the light emitting control line EM.

[0104] The present application moves the node reset signal line Vi3, which was originally set between the first reset control line Pscan2 and the first reset signal line Vi1, to between the first reset control line Pscan2 and the storage capacitor Cst, thereby reducing the distance between the first reset control line Pscan2 and the first reset signal line Vi1, thereby compressing the space of the present application in the second direction Y, improving the arrangement density of the pixel circuit PC, and thus improving the PPI of the product.

[0105] At the same time, Figure 11 and Figure 15 In the structure, the two compensation active portions T3A in the repeating unit RU are spaced apart in the first direction X, and in the first direction X, the distance between the second electrode plate Cst2 and the compensation active portion T3A is smaller than the distance between the two compensation active portions T3A in the same repeating unit RU.

[0106] Since the second electrode Cst2 is located in the second gate layer 129 and the compensation active part T3A is in the second active layer 127, the two are different layer structures, so the distance between the second electrode Cst2 and the compensation active part T3A can be reduced, and the distance between the two compensation active parts T3A in the same repeating unit RU is the minimum safety distance in design. Therefore, the distance between the second electrode Cst2 and the compensation active part T3A of the present application is smaller than the distance between the two compensation active parts T3A located in the same repeating unit RU. For example, the edge of the second electrode Cst2 and the boundary of the compensation active part T3A can coincide, but in order to avoid the generation of parasitic capacitance, the two cannot overlap.

[0107] That is, the present application reduces the distance between the second electrode plate Cst2 and the compensation active portion T3A, thereby compressing the space of the present application in the first direction X, improving the arrangement density of the pixel circuit PC, and thus improving the PPI of the product.

[0108] exist Figures 9 to 11 In the structure, the node reset signal line Vi3 is located in the second gate layer 129, and the second plate Cst2 of the storage capacitor Cst is also located in the second gate layer 129, so a minimum safety distance needs to be set between the node reset signal line Vi3 and the second plate Cst2; Figures 13 to 15 In the structure, the node reset signal line Vi3 is located in the second active layer 127, and the second plate Cst2 of the storage capacitor Cst is also located in the second gate layer 129. Therefore, there is no need to set a minimum safety distance between the node reset signal line Vi3 and the second plate Cst2. Figure 11 The distance between the node reset signal line Vi3 and the second plate Cst2 must be greater than Figure 15 The distance between the node reset signal line Vi3 and the second plate Cst2, that is, Figure 11 The second electrode Cst2 in the relative node reset signal line Vi3 moves upward, so that Figure 11 The switch control line Pscan1 and the compensation control line Nscan1 have an overlapping portion, and Figure 15 The middle switch control line Pscan1 and the compensation control line Nscan1 may be arranged to be non-overlapping.

[0109] See also Figures 5 to 11 In the structure, the switch control line Pscan1 includes a first switch segment P1a and a second switch segment P1b that are alternately arranged and connected. In the second direction Y, the distance between the second switch segment P1b and the second electrode plate Cst2 is smaller than the distance between the first switch segment P1a and the second electrode plate Cst2.

[0110] In this embodiment, the switch control line Pscan1 is used to control the conduction and cutoff of the switch transistor T2, and the extension line of the first switch segment P1a of the present application in the first direction X overlaps with the connection point between the switch active portion T2A and the data line in the switch transistor T2. Therefore, in order to avoid the influence of the switch control line Pscan1 on the connection point, the present application moves part of the switch control line Pscan1 downward, that is, the second switch segment P1b avoids the connection point between the switch active portion T2A and the data line.

[0111] See also Figures 9 to 11 , the compensation control line Nscan1 may overlap with the second switching segment P1b.

[0112] See also Figures 9 to 11The compensation control line Nscan1 includes a first compensation segment N1a and a second compensation segment N1b that are alternately arranged and connected. In the second direction Y, the distance between the second compensation segment N1b and the second electrode plate Cst2 is smaller than the distance between the first compensation segment N1a and the second electrode plate Cst2. The first compensation segment N1a and the second switching segment P1b have an overlapping portion.

[0113] In this embodiment, the second compensation segment N1b is moved downward relative to the first compensation segment N1a to avoid the connection point between the compensation active portion T3A and the first reset active portion T4A. At the same time, the second compensation segment N1b overlaps with the compensation active portion T3A to control the on and off state of the compensation transistor T3.

[0114] See also Figure 5 、 Figures 9 to 15 The first reset signal line Vi1 includes a first reset segment V1a and a second reset segment V1b that are alternately arranged and connected. The line width of the first reset segment V1a is greater than the line width of the second reset segment V1b, and the first reset segment V1a has an overlapping portion with the first reset active portion T4A.

[0115] In this embodiment, the first reset active portion T4A is electrically connected to the first reset segment V1a through the via hole. In order to reduce the contact impedance of the via hole, the present application increases the area of ​​the first reset segment V1a to increase the area corresponding to the contact via hole.

[0116] See also Figure 5 、 Figures 9 to 15 The first reset control line Pscan2 includes a first control segment P2a, a second control segment P2b, and a third control segment P2c, which are connected to each other. The line width of the second control segment P2b is smaller than the line width of the first control segment P2a and the line width of the third control segment P2c. The first control segment P2a and the second reset active portion T7A of the second reset transistor T7 have an overlapping portion, and the third control segment P2c and the third reset active portion T8A of the node reset transistor T8 have an overlapping portion.

[0117] In this embodiment, the line width of the second control segment P2b is reduced because the second control segment P2b and the fourth extension segment ET4 have an overlapping portion. In order to reduce the coupling capacitance between the second control segment P2b and the fourth extension segment ET4, the present application reduces the line width of the second control segment P2b.

[0118] The following examples Figures 9 to 11 The remaining film layer structure is explained by taking the structure of as an example.

[0119] See also Figure 16 and Figure 17The first source-drain layer 131 includes a second reset signal line Vi2 , which is disposed on a side of the node reset signal line Vi3 away from the compensation control line Nscan1 , and the second reset signal line Vi2 and the first reset control line Pscan2 have an overlapping portion.

[0120] See also Figure 16 and Figure 17 The first source-drain layer 131 further includes a third connection segment CT3. The third connection segments CT3 in two adjacent repeating units RU are continuous, and the third connection segments CT3 in the same repeating unit RU are arranged at intervals. One end of the third connection segment CT3 is connected to the first reset signal line Vi1 through a via hole, and the other end of the third connection segment CT3 is connected to the end of the first reset active portion T4A away from the fourth connection point N4 through a via hole; that is, the third connection segments CT3 in two adjacent repeating units RU are continuous and connected to the first reset signal line Vi1 through the same via hole.

[0121] It should be noted that the third connecting segments CT3 in two adjacent pixel circuits PC are different.

[0122] See also Figure 16 and Figure 17 The first source-drain layer 131 further includes a fourth connection segment CT4, one end of which is connected to the data line Data through a via hole, and the other end of which is connected to an end of the switch active portion T2A away from the first connection point N1 through a via hole.

[0123] See also Figure 16 and Figure 17 The first source-drain layer 131 further includes a fifth connection segment CT5, one end of the fifth connection segment CT5 is connected to one end of the fourth connection point N4 of the compensation active portion T3A through a via hole, and the other end of the fifth connection segment CT5 is connected to the first electrode plate Cst1 through a via hole, and the via hole passes through the avoidance hole HL0 in the second electrode plate Cst2 of the storage capacitor Cst.

[0124] See also Figure 17 The first source-drain layer 131 further includes a sixth connection segment CT6, one end of the sixth connection segment CT6 is connected to an end of the compensation active portion T3A away from the fourth connection point N4 through a via hole, and the other end of the sixth connection segment CT6 is connected to an end of the second light-emitting active portion T6A away from the third connection point N3 through a via hole.

[0125] See also Figure 17 The first source-drain layer 131 further includes a seventh connection segment CT7, one end of the seventh connection segment CT7 is connected to the end of the first extension segment ET1 away from the third connection point N3 through a via hole, and the other end of the seventh connection segment CT7 is connected to the upper metal layer through a via hole.

[0126] See also Figure 17 The first source-drain layer 131 further includes an eighth connection segment CT8, one end of the eighth connection segment CT8 is connected to the second extension segment ET2 through a via hole, and the other end of the eighth connection segment CT8 is connected to an end of the third reset active portion T8A close to the light emitting control line EM through a via hole.

[0127] See also Figure 17 The first source-drain layer 131 further includes a ninth connection segment CT9. The two ninth connection segments CT9 in the same repeating unit RU are continuously and symmetrically arranged in the first direction X, and one end of the ninth connection segment CT9 is connected to the fourth extension segment ET4 through a via hole, and the other end of the ninth connection segment CT9 is connected to the end of the third reset active portion T8A away from the light-emitting control line EM through a via hole.

[0128] See also Figure 17 The first source-drain layer 131 further includes a tenth connection segment CT10. The two tenth connection segments CT10 in the same repeating unit RU are continuously and symmetrically arranged in the first direction X, and one end of the tenth connection segment CT10 passes through the via hole and is connected to the upper high potential line VDD. Figure 19 The other end of the tenth connecting segment CT10 is connected to one end of the upper eleventh connecting segment CT11 through a via hole; and the first source and drain layer 131 also includes a sixth extension segment ET6 connected to the tenth connecting segment CT10, and the sixth extension segment ET6 extends along the second direction Y, and the sixth extension segment ET6 is connected to the second plate of the storage capacitor Cst through a via hole.

[0129] See also Figure 17 The first source-drain electrode layer 131 further includes a twelfth connecting segment CT12. One twelfth connecting segment CT12 is provided in the same repeating unit RU, and one end of the twelfth connecting segment CT12 passes through the via hole and is connected to the other end of the eleventh connecting segment CT11. Figure 19 The other end of the twelfth connecting segment CT12 passes through the via hole and is connected to the end of the first light emitting active portion T5A away from the light emitting control line EM, and the two first light emitting active portions T5A in the same repeating unit RU share a connection point.

[0130] See also Figure 4 、 Figure 18 and Figure 19 The second source-drain layer 133 includes a high potential line VDD and a data line Data arranged along the first direction X, and both the high potential line VDD and the data line Data extend along the second direction Y.

[0131] In this embodiment, the second source-drain layer 133 further includes eleven connection segments CT11 disposed between two adjacent vertical data lines Data. The same repeating unit RU shares one eleventh connection segment CT11, which is used to transmit the signal of the high potential line VDD to the first light-emitting active portion T5A.

[0132] See also Figure 18 The high potential lines VDD in the same repeating unit RU are arranged at intervals, and the high potential lines VDD in two adjacent repeating units RU are connected; at the same time, a gap is provided at the end of the high potential line VDD away from the data line Data, and a thirteenth connecting segment CT13 is provided in the gap. One end of the thirteenth connecting segment CT13 is connected to the seventh connecting segment CT7 of the lower layer, and the other end of the thirteenth connecting segment CT13 is connected to the anode layer AN of the upper layer.

[0133] See also Figure 20 and Figure 21 The anode layer AN includes multiple first anodes AN1, multiple second anodes AN2 and multiple third anodes AN3, as well as a first lead LW1 connected to the first anode AN1, a second lead LW2 connected to the second anode AN2, and a third lead LW3 connected to the third anode AN3. The first lead LW1 and the third lead LW3 extend along the first direction X, and the second lead LW2 extends along the second direction Y. The first lead LW1, the second lead LW2 and the third lead LW3 are connected to thirteen connection segments CT13 in the corresponding pixel circuit.

[0134] In this embodiment, the first anodes AN1 and the third anodes AN3 are located in the same row and are alternately arranged along the first direction X. The second anodes AN2 are alternately arranged along the first direction X and are staggered with the row where the first anodes AN1 and the third anodes AN3 are located.

[0135] See also Figure 4 The repeating unit RU may include a first pixel circuit and a second pixel circuit, and a first anode AN1 connected to the first pixel circuit and a second anode AN2 connected to the second pixel circuit, and the first anode overlaps with the first pixel circuit and the second pixel circuit.

[0136] In this embodiment, the first pixel circuit may be one of a red sub-pixel or a blue sub-pixel PX, and the second pixel circuit may be a green sub-pixel.

[0137] It should be noted that the signal transmission wires of the present application extend along the first direction X or the second direction Y, which only means that the wires extend in that direction, and does not mean that the wires are straight lines. For example, the wires of the present application may be bent curves or broken lines.

[0138] The present application also provides a display device, comprising the above-mentioned display panel. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0139] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0140] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The device comprises a plurality of sub-pixels, at least one of which comprises a connected pixel circuit and a light-emitting device, wherein the pixel circuit comprises: A driving transistor including a driving active portion and a driving gate; a compensation transistor connected to the driving transistor, the compensation transistor comprising a compensation active portion and a compensation gate, wherein the compensation active portion and the driving active portion are made of different materials; A storage capacitor is connected to the driving transistor and the compensation transistor, and the storage capacitor includes a first plate and a second plate arranged opposite to each other, the first plate is made of the same material as the driving gate, and the second plate is made of the same material as the compensation gate.

2. The display panel according to claim 1, wherein: The pixel circuit further includes: a switch transistor connected to the driving transistor at a first node, wherein a gate of the switch transistor is connected to a switch control line; a node reset transistor connected to the first node, a gate of the node reset transistor connected to a first reset control line, and a drain of the node reset transistor connected to the node reset signal line; The compensation gate is connected to a compensation control line, and the switch control line, the compensation control line, the node reset signal line and the first reset control line all extend along a first direction and are arranged at intervals along a second direction.

3. The display panel according to claim 2, wherein: The node reset signal line and the compensation active portion are located in the same layer, and the switch control line and the compensation control line are arranged to be non-overlapping.

4. The display panel according to claim 2, wherein: The node reset signal line and the compensation gate are located in the same layer, and the switch control line and the compensation control line have an overlapping portion.

5. The display panel according to claim 4, wherein: The switch control line includes alternately arranged and connected first switch segments and second switch segments. In the second direction, a distance between the second switch segments and the second electrode plate is smaller than a distance between the first switch segments and the second electrode plate.

6. The display panel according to claim 5, wherein: The compensation control line overlaps with the second switching segment.

7. The display panel according to claim 6, wherein: The compensation control line includes a first compensation segment and a second compensation segment that are alternately arranged and connected, and in the second direction, the distance between the second compensation segment and the second electrode plate is smaller than the distance between the first compensation segment and the second electrode plate; The first compensation segment and the second switching segment have an overlapping portion.

8. The display panel according to claim 2, wherein: The pixel circuit further includes a first light emitting transistor connected to the first node, wherein a gate of the first light emitting transistor is connected to a light emitting control line; The light emitting control line and the node reset signal line have an overlapping portion.

9. The display panel according to any one of claims 2 to 8, characterized in that: The display panel further includes a reset extension segment connected to the node reset signal line, and the reset extension segment extends toward an end away from the storage capacitor.

10. The display panel according to any one of claims 2 to 8, characterized in that: The pixel circuit further includes a first reset transistor connected to the compensation transistor, the storage capacitor, and the driving transistor, wherein a drain of the first reset transistor is connected to a first reset signal line, and the first reset signal line is located between the switch control line and the first reset control line; The first reset signal line includes a first reset segment and a second reset segment that are alternately arranged and connected, the line width of the first reset segment is greater than the line width of the second reset segment, and the first reset segment has an overlapping portion with the active portion of the first reset transistor.

11. The display panel according to any one of claims 2 to 8, characterized in that: The pixel circuit further includes a second reset transistor connected to the anode terminal of the light emitting device, and the gate of the second reset transistor is connected to the first reset control line; The first reset control line includes a first control segment, a second control segment, and a third control segment connected to each other, the line width of the second control segment is smaller than the line width of the first control segment and the line width of the third control segment, and the first control segment and the active part of the second reset transistor have an overlapping part, and the third control segment and the active part of the node reset transistor have an overlapping part.

12. The display panel according to any one of claims 1 to 8, characterized in that: The display panel includes a plurality of repeating units, each of the repeating units includes two sub-pixels, and the two compensation active portions in the repeating unit are spaced apart in a first direction; Wherein, in the first direction, the distance between the second electrode plate and the compensation active portion is smaller than the distance between two compensation active portions located in the same repeating unit.

13. A display device, characterized in that: The display device includes the display panel described in any one of items 1 to 12 above.

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