Memory management method and storage device

Abstract

The invention provides a memory management method and a storage device. The method comprises: in response to an access event, obtaining first address information corresponding to a first physical address of a memory module; confirming whether the first address information meets a critical condition; if the first address information meets the critical condition, determining correction information according to feature information and mask information corresponding to the first address information; obtaining second address information corresponding to a second physical address of the memory module according to the first address information and the correction information; and executing access operation on the first physical address and the second physical address according to the first address information and the second address information. Therefore, the operation stability of the storage device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a storage device. Background Art

[0002] In order to improve data writing performance, most storage devices support continuous data writing. That is, when performing data writing for a certain physical address, the write address of the next data is predicted in advance based on the write address of the current data. However, since the address information is represented in binary, if the address information corresponding to the current write operation is simply added by 1 to obtain the address information corresponding to the next write operation, invalid address information may be obtained. Taking a 3-plane memory module as an example, the information segment used to represent the plane in the address information may include two bits. The legal states of these two bits are "00" (corresponding to plane 0), "01" (corresponding to plane 1) and "10" (corresponding to plane 2), and their illegal state is "11" (corresponding to the non-existent plane 3). Once these two bits are in an illegal state, the address information is invalid address information.

[0003] Traditionally, the memory controller needs to perform complex operations on the address information corresponding to the current write operation to avoid the predicted address information corresponding to the next write operation being invalid address information. For example, the memory controller needs to first split the address information into multiple information segments, and then perform an accumulation test (for example, adding 1) starting from the end of these information segments. When the accumulated information segment involves a binary carry, it is necessary to further determine whether the information segment after the carry reaches a preset value (or maximum value). If the maximum value is reached, the next accumulation needs to carry to the next information segment again. After a series of accumulation tests, all the information segments are combined into new address information, which is very cumbersome and time-consuming to operate. Summary of the Invention

[0004] The present invention provides a memory management method and a storage device, which can improve the above-mentioned problem, thereby enhancing the operation stability of the storage device and improving the efficiency.

[0005] An embodiment of the present invention provides a memory management method for a storage device, wherein the storage device includes a memory module, and the memory management method includes: obtaining first address information in response to an access event, wherein the first address information corresponds to a first physical address of the memory module; confirming whether the first address information meets a critical condition; if the first address information meets the critical condition, determining correction information based on feature information and mask information corresponding to the first address information; obtaining second address information based on the first address information and the correction information, wherein the second address information corresponds to a second physical address of the memory module; and performing access operations on the first physical address and the second physical address based on the first address information and the second address information.

[0006] An embodiment of the present invention further provides a storage device comprising a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to: obtain first address information in response to an access event, wherein the first address information corresponds to a first physical address of the memory module; confirm whether the first address information meets a critical condition; if the first address information meets the critical condition, determine correction information based on feature information and mask information corresponding to the first address information; obtain second address information based on the first address information and the correction information, wherein the second address information corresponds to a second physical address of the memory module; and perform access operations on the first physical address and the second physical address based on the first address information and the second address information. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0008] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0009] Figure 3 is a schematic diagram of address information according to an embodiment of the present invention;

[0010] Figure 4 is a schematic diagram of obtaining second address information when first address information meets a critical condition according to an embodiment of the present invention;

[0011] Figure 5 is a schematic diagram of obtaining second address information when first address information meets a critical condition according to an embodiment of the present invention;

[0012] Figure 6 FIG. 4 is a flowchart of a memory management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0014] Figure 1 Schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, a tablet computer, a laptop computer, a desktop computer, an industrial computer, a game console, a server, or a computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to this. In addition, the storage device 12 can include a solid-state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0015] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 may support an embedded Multi-Media Card (eMMC), Universal Flash Storage (UFS), Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (e.g., exchange signals, instructions, and / or data) via the connection interface 121.

[0016] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of a voltage (also known as a threshold voltage). For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, and / or other memory modules having the same or similar characteristics.

[0017] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be considered the control core of the memory device 12 and is used to control the memory device 12. For example, the memory controller 123 can be used to control or manage all or part of the operation of the memory device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar devices or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0018] The memory controller 123 can send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, and the present invention is not limited thereto. The memory module 122 can receive the command sequence from the memory controller 123 and access the memory cells within the memory module 122 according to the command sequence.

[0019] Figure 2 FIG is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0020] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage all or part of the operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 via the host interface 21 and access the memory module 122 via the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0021] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0022] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data accuracy. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits), and the present invention is not limited thereto.

[0023] In one embodiment, the memory control circuit 23 can detect an access event to the memory module 122. The access event can indicate accessing at least one physical address of the memory module 122. For example, the access event can indicate performing a read operation, a write operation, or an erase operation on at least one physical address of the memory module 122. For example, the read operation is used to read data from the at least one physical address. The write operation is used to write data to the at least one physical address. The erase operation is used to erase data stored at the at least one physical address.

[0024] In one embodiment, the memory control circuit 23 may obtain address information (also referred to as first address information) in response to the access event. The first address information corresponds to a physical address (also referred to as the first physical address) of the memory module 122. For example, the access event may indicate access to the first physical address.

[0025] In one embodiment, the first address information may include multiple information segments. These information segments may reflect the first physical address based on a combination of multiple physical management units. For example, the multiple physical management units may include at least two of a block (also known as a virtual block), a page (also known as a physical page), a chip enable (CE) (also known as a chip enable region), a page type, a plane (also known as a memory plane), and a node (also known as a physical node). For example, the multiple information segments may be used to carry numbers or other identification information of the multiple physical management units.

[0026] Figure 3 is a schematic diagram of address information according to an embodiment of the present invention. Figure 3, assuming that the first address information includes address information 31. Address information 31 includes multiple information segments 301 to 306. Information segments 301 to 306 can reflect the first physical address based on a combination of multiple physical management units. For example, from the highest bit to the lowest bit of address information 31, information segments 301 to 306 can correspond to virtual blocks (VB), pages, chip enables (CE), page types (Type), planes (Plane), and nodes (Node) in sequence. For example, in information segment 301, bit positions 0-1 can be used to reflect the number of the node corresponding to the first physical address; bit positions 2-3 can be used to reflect the number of the plane corresponding to the first physical address; bit positions 4-5 can be used to reflect the number of the subpage corresponding to the first physical address; bit positions 6-7 can be used to reflect the number of the chip enable corresponding to the first physical address; bit positions 8-20 can be used to reflect the number of the page corresponding to the first physical address; and bit positions 21-31 can be used to reflect the number of the virtual block corresponding to the first physical address. For example, the combination of information segments 301 - 306 may reflect the first physical address.

[0027] It should be noted that in Figure 3 In the embodiment, the node corresponding to the first physical address is reflected by the bit value of 2 bits in information segment 306, the plane corresponding to the first physical address is reflected by the bit value of 2 bits in information segment 305, the type of page corresponding to the first physical address is reflected by the bit value of 2 bits in information segment 304, the chip enable corresponding to the first physical address is reflected by the bit value of 2 bits in information segment 303, the page corresponding to the first physical address is reflected by the bit value of 13 bits in information segment 302, and the virtual block corresponding to the first physical address is reflected by the bit value of 11 bits in information segment 301. However, in another embodiment, the total number of bits included in any information segment in address information 31 can also be adjusted according to practical needs. In addition, the overall information content of address information 31 can also be adjusted according to practical needs.

[0028] In one embodiment, after obtaining the first address information, the memory control circuit 23 may confirm whether the first address information meets the critical condition. In one embodiment, if the address information obtained after adding the preset information (e.g., 1) to the first address information (also referred to as the second address information) includes error information (also referred to as illegal information), the memory control circuit 23 may determine that the first address information meets the critical condition. The second address information may correspond to the physical address of the memory module 122 (also referred to as the second physical address). The second address information is different from the first address information, and the second physical address is different from the first physical address. However, in one embodiment, if the address information obtained after adding the preset information (e.g., 1) to the first address information (i.e., the second address information) does not include error information (i.e., illegal information), the memory control circuit 23 may determine that the first address information does not meet the critical condition.

[0029] by Figure 3 For example, in one embodiment, assuming that the memory module 122 supports a maximum of three page types (e.g., assuming that the memory module 122 operates in TLC mode, the three page types may be upper page, middle page, and lower page), the information carried by the information segment 304 may be "00," "01," and "10," but not "11." When the information carried by the information segment 304 is one of "00," "01," and "10," the information carried by the information segment 304 may be considered valid (also known as legal). However, when the information carried by the information segment 304 is "11," the information carried by the information segment 304 may be considered incorrect (i.e., illegal).

[0030] Or, similarly Figure 3 For example, assuming that the memory module 122 supports a maximum of three planes of access, the information carried by the information segment 305 can be "00," "01," and "10," but cannot be "11." When the information carried by the information segment 305 is any one of "00," "01," and "10," the information carried by the information segment 305 can be considered valid (i.e., legal). However, when the information carried by the information segment 305 is "11," the information carried by the information segment 305 can be considered incorrect (i.e., illegal).

[0031] In one embodiment, after obtaining the first address information, the memory control circuit 23 may determine a target information segment from the first address information. For example, the target information segment may be Figure 3 At least one of the information segments 301 to 306 in .

[0032] In one embodiment, the memory control circuit 23 may move a sampling window starting from one end point of the first address information (also referred to as the first end point) toward the other end point of the first address information (also referred to as the second end point). For example, the first end point may be the location of the most significant bit of the first address information, and the second end point may be the location of the least significant bit of the first address information. Figure 3 For example, the first endpoint of the address information 31 may be the 31st bit position in the address information 31 , and the second endpoint of the address information 31 may be the 0th bit position in the address information 31 .

[0033] In one embodiment, after setting or moving the sampling window, the memory control circuit 23 can determine the target information segment according to the coverage of the sampling window in the first address information. Figure 3 For example, assuming that after setting or shifting the sampling window, the sampling window covers the 4th and 5th bit positions in the address information 31, the memory control circuit 23 may determine that the information segment 304 is the target information segment. Alternatively, assuming that after setting or shifting the sampling window, the sampling window covers the 2nd and 3rd bit positions in the address information 31, the memory control circuit 23 may determine that the information segment 305 is the target information segment.

[0034] In one embodiment, after determining the target information segment, the memory control circuit 23 may confirm whether the target information segment contains critical information. Figure 3 For example, assuming that the memory module 122 supports at most three page types and the information segment 304 is the target information segment, the critical information corresponding to the information segment 304 may be "10". When the information carried by the information segment 304 is "10", the memory control circuit 23 may determine that the target information segment contains critical information. Alternatively, Figure 3 For example, assuming that memory module 122 supports a maximum of three planes of access and information segment 305 is the target information segment, the critical information corresponding to information segment 305 may be "10." When the information carried by information segment 305 is "10," memory control circuit 23 may determine that the target information segment contains critical information.

[0035] In one embodiment, the memory control circuit 23 may further determine the mask information corresponding to the target information segment according to the target information segment. Figure 3For example, if the target information segment is information segment 304, then in the mask information corresponding to information segment 304 (i.e., the target information segment), the bit values ​​at bit positions 0-5 are all "1," while the bit values ​​at the remaining bit positions 6-31 are all "0." Alternatively, if the target information segment is information segment 305, then in the mask information corresponding to information segment 305 (i.e., the target information segment), the bit values ​​at bit positions 0-3 are all "1," while the bit values ​​at the remaining bit positions 4-31 are all "0." Thus, the purpose of using this mask information to verify the low-order bits starting from the target information segment in the first address information can be achieved, thereby shielding irrelevant high-order bits higher than the target information segment.

[0036] In one embodiment, if the target information segment includes critical information, the memory control circuit 23 may perform mask processing on the first address information using mask information corresponding to the target information segment to obtain the masked first address information. For example, the mask processing is used to shield the bit positions in the first address information that are higher than the target information segment. For example, in the masked first address information, the bit values ​​of the bit positions higher than the target information segment may all be updated to "0". Then, the memory control circuit 23 may compare the masked first address information with the characteristic information to obtain a comparison result. For example, the characteristic information is defined as follows: after adding preset information (e.g., 1) to the characteristic information, the target information segment in the obtained information (e.g., the second address information) will inevitably contain error information (i.e., illegal information).

[0037] In one embodiment, if the comparison result indicates that the masked first address information is identical to the characteristic information, the memory control circuit 23 may determine that the first address information meets the critical condition. However, in one embodiment, if at least one candidate information segment in the first address information (i.e., all information segments in the first address information that can be set as target information segments) does not contain corresponding critical information, the memory control circuit 23 may determine that the first address information does not meet the critical condition. Alternatively, in one embodiment, even if a target information segment contains critical information, if the comparison result indicates that the masked first address information is different from the characteristic information, the memory control circuit 23 may determine that the first address information does not meet the critical condition.

[0038] In one embodiment, after determining the target information segment, the memory control circuit 23 may query a management table based on the type or location of the target information segment to obtain a query result. For example, the management table may be used to record different critical information, characteristic information, and / or mask information corresponding to different types of target information segments or target information segments located at different locations. The memory control circuit 23 may determine the critical information, characteristic information, and / or mask information based on the query result.

[0039] In one embodiment, after determining that the first address information meets the critical condition, the memory control circuit 23 may determine correction information based on the characteristic information corresponding to the first address information and the mask information. The memory control circuit 23 may then obtain the second address information based on the first address information and the correction information.

[0040] In one embodiment, the memory control circuit 23 may perform access operations on the first physical address and the second physical address based on the first address information and the second address information. For example, the memory control circuit 23 may continuously perform operations indicated by the aforementioned access events, such as a write operation, a read operation, or an erase operation, on the first physical address and the second physical address based on the first address information and the second address information.

[0041] It should be noted that if the first address information meets the critical condition, simply adding the aforementioned preset information (e.g., 1) to the first address information will result in the obtained second address information including error information (i.e., illegal information). The second address information including error information (i.e., illegal information) cannot be used to access the memory module 122. However, if the second address information is obtained based on the first address information and the correction information, even if the first address information meets the critical condition, the obtained second address information will not include error information, thereby ensuring that the memory module 122 can be successfully accessed based on the second address information. This effectively improves the operational stability of the storage device 12 without significantly increasing computational complexity.

[0042] In one embodiment, if the first address information does not meet the critical condition, the memory control circuit 23 may directly add the predetermined information (e.g., 1) to the first address information to obtain the second physical address. Thus, the memory control circuit 23 may also perform the aforementioned access operations on the first physical address and the second physical address based on the first address information and the second address information.

[0043] In one embodiment, after determining that the first address information meets the critical condition, the memory control circuit 23 may perform a specific operation (also referred to as a first operation) based on the mask information and the preset information to obtain transient information (also referred to as the first transient information). For example, the first transient information may reflect the result of executing the first operation. For example, the first operation may include binary addition of the mask information and the preset information. For example, in the first operation, the memory control circuit 23 may add the mask information to the preset information to obtain the first transient information.

[0044] In one embodiment, after obtaining the first transient state information, the memory control circuit 23 may perform another operation (also referred to as a second operation) based on the first transient state information and the characteristic information to obtain the correction information. For example, the correction information may reflect the result of the second operation. For example, the second operation may include binary subtraction of the first transient state information and the characteristic information. For example, in the second operation, the memory control circuit 23 may subtract the characteristic information from the first transient state information to obtain the correction information.

[0045] In one embodiment, after obtaining the correction information, the memory control circuit 23 may perform another operation (also referred to as a third operation) based on the first address information and the correction information to obtain the second address information. For example, the second address information may reflect the result of the third operation. For example, the third operation may include binary addition of the first address information and the correction information. For example, in the third operation, the memory control circuit 23 may add the correction information to the first address information to obtain the second address information.

[0046] Figure 4 This is a schematic diagram of obtaining the second address information when the first address information meets the critical condition according to an embodiment of the present invention. Figure 4 , assuming that the address information 41 is the first address information, and the target information segment 401 includes the 4th-5th bit positions in the address information 41.

[0047] In one embodiment, assume that the target information segment 401 includes critical information (i.e., "10"). In response to the target information segment 401 including the critical information, the memory control circuit 23 may mask the address information 41 using the mask information 43 corresponding to the target information segment 401 and compare the masked address information 41 with the characteristic information 42. If the masked address information 41 is identical to the characteristic information 42, the memory control circuit 23 may determine that the address information 41 meets the critical condition.

[0048] After determining that address information 41 meets the critical condition, memory control circuit 23 may add predetermined information (e.g., 1) to mask information 43 and subtract characteristic information 42 from mask information 43 to obtain correction information 44. Furthermore, memory control circuit 23 may add correction information 44 to address information 41 to obtain address information 45 (i.e., second address information). Specifically, address information 45 does not contain erroneous information (i.e., illegal information).

[0049] Figure 5 This is a schematic diagram of obtaining the second address information when the first address information meets the critical condition according to an embodiment of the present invention. Figure 5, assuming that the address information 51 is the first address information, and the target information segment 501 includes the 2nd-3rd bit positions in the address information 51.

[0050] In one embodiment, assume that the target information segment 501 includes critical information (i.e., "10"). In response to the target information segment 501 including the critical information, the memory control circuit 23 may mask the address information 51 using the mask information 53 corresponding to the target information segment 501 and compare the masked address information 51 with the characteristic information 52. If the masked address information 51 is identical to the characteristic information 52, the memory control circuit 23 may determine that the address information 51 meets the critical condition.

[0051] After determining that the address information 51 meets the critical condition, the memory control circuit 23 may add the preset information (e.g., 1) to the mask information 53 and subtract the characteristic information 52 to obtain the correction information 54. However, the memory control circuit 23 may add the correction information 54 to the address information 51 to obtain the address information 55 (i.e., the second address information). Figure 4 In the embodiment, the address information 45 also does not contain erroneous information (ie, illegal information).

[0052] Figure 6 FIG is a flow chart of a memory management method according to an embodiment of the present invention. Figure 6 In step S601, in response to an access event, first address information is obtained, wherein the first address information corresponds to a first physical address of the memory module. In step S602, it is confirmed whether the first address information meets a critical condition. If the first address information meets the critical condition, in step S603, correction information is determined based on the feature information and mask information corresponding to the first address information. In step S604, second address information is obtained based on the first address information and the correction information, wherein the second address information corresponds to a second physical address of the memory module. In step S605, an access operation is performed on the first physical address and the second physical address based on the first address information and the second address information. However, if the first address information does not meet the critical condition, in step S606, the first address information is added with preset information to obtain the second physical address.

[0053] However, Figure 6 The steps have been described in detail above and will not be repeated here. Figure 6 Each step can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 6 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0054] In summary, the memory management method and storage device proposed in the embodiments of the present invention can ensure that the address information predicted for the current access event does not contain erroneous information through simple logical operations. This effectively improves the operational stability of the storage device and enhances access efficiency without significantly increasing computational complexity.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For use in a storage device, wherein the storage device includes a memory module, and the memory management method includes: In response to an access event, obtaining first address information, wherein the first address information corresponds to a first physical address of the memory module; confirming whether the first address information meets a critical condition; If the first address information meets the critical condition, determining correction information according to the feature information and mask information corresponding to the first address information; Obtaining second address information according to the first address information and the calibration information, wherein the second address information corresponds to a second physical address of the memory module; and An access operation is performed on the first physical address and the second physical address according to the first address information and the second address information.

2. The memory management method according to claim 1 , wherein the step of confirming whether the first address information meets a critical condition comprises: determining a target information segment from the first address information; If the target information segment includes critical information, masking the first address information using mask information corresponding to the target information segment to obtain masked first address information; Comparing the masked first address information with the characteristic information to obtain a comparison result; as well as If the comparison result indicates that the masked first address information is identical to the characteristic information, it is determined that the first address information meets the critical condition.

3. The memory management method according to claim 2, wherein the step of determining the target information segment from the first address information comprises: Starting from the first end point of the first address information, moving the sampling window toward the second end point of the first address information; as well as The target information segment is determined according to a coverage range of the sampling window in the first address information. 4 . The memory management method according to claim 3 , wherein the first endpoint is a location of a most significant bit of the first address information, and the second endpoint is a location of a least significant bit of the first address information.

5. The memory management method according to claim 2, further comprising: According to the type or location of the target information segment, query the management table to obtain the query result; as well as At least one of the critical information, the feature information, and the mask information is determined according to the query result.

6. The memory management method according to claim 1 , wherein the step of determining the correction information according to the feature information corresponding to the first address information and the mask information comprises: Performing a first operation according to the mask information and preset information to obtain first transient information; as well as A second operation is performed according to the first transient information and the characteristic information to obtain the correction information.

7. The memory management method according to claim 6, wherein the step of obtaining the second address information according to the first address information and the correction information comprises: A third operation is performed according to the first address information and the correction information to obtain the second address information.

8. The memory management method according to claim 1, further comprising: If the first address information does not meet the critical condition, the first address information is added with preset information to obtain the second physical address.

9. The memory management method according to claim 2, wherein the first address information includes a plurality of information segments, the plurality of information segments reflect the first physical address based on a combination of a plurality of physical management units, and the target information segment is at least one of the plurality of information segments.

10. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory controller is configured to: In response to an access event, obtaining first address information, wherein the first address information corresponds to a first physical address of the memory module; confirming whether the first address information meets a critical condition; If the first address information meets the critical condition, determining correction information according to the feature information and mask information corresponding to the first address information; Obtaining second address information according to the first address information and the calibration information, wherein the second address information corresponds to a second physical address of the memory module; and An access operation is performed on the first physical address and the second physical address according to the first address information and the second address information.

11. The storage device according to claim 10, wherein the operation of the memory controller confirming whether the first address information meets the critical condition comprises: determining a target information segment from the first address information; If the target information segment includes critical information, masking the first address information using mask information corresponding to the target information segment to obtain masked first address information; Comparing the masked first address information with the characteristic information to obtain a comparison result; as well as If the comparison result indicates that the masked first address information is identical to the characteristic information, it is determined that the first address information meets the critical condition.

12. The storage device according to claim 11, wherein the operation of the memory controller determining the target information segment from the first address information comprises: Starting from the first end point of the first address information, moving the sampling window toward the second end point of the first address information; as well as The target information segment is determined according to a coverage range of the sampling window in the first address information. 13 . The storage device according to claim 12 , wherein the first endpoint is where the most significant bit of the first address information is located, and the second endpoint is where the least significant bit of the first address information is located.

14. The storage device according to claim 11, wherein the memory controller is further configured to: Querying the management table according to the type or location of the target information segment to obtain a query result; and At least one of the critical information, the feature information, and the mask information is determined according to the query result.

15. The storage device according to claim 10 , wherein the memory controller determines the correction information according to the feature information corresponding to the first address information and the mask information, comprising: Performing a first operation according to the mask information and preset information to obtain first transient information; as well as A second operation is performed according to the first transient information and the characteristic information to obtain the correction information.

16. The storage device according to claim 15, wherein the memory controller obtains the second address information according to the first address information and the correction information, comprising: A third operation is performed according to the first address information and the correction information to obtain the second address information.

17. The storage device according to claim 10, wherein the memory controller is further configured to: If the first address information does not meet the critical condition, the first address information is added with preset information to obtain the second physical address.

18. The storage device according to claim 11, wherein the first address information includes a plurality of information segments, the plurality of information segments reflect the first physical address based on a combination of a plurality of physical management units, and the target information segment is at least one of the plurality of information segments.

Images