A chip interrupt processing method, device, equipment and storage medium

Abstract

The application discloses a chip interrupt processing method and device, equipment and storage medium, and comprises the following steps: after detecting that a target interrupt is triggered in a CPU chip, determining a target priority according to an interrupt number corresponding to the target interrupt in a hash table; a mapping relationship between each interrupt number and the priority in the CPU chip is stored in the hash table in advance; determining a target array value according to the target priority in an interrupt enable register array table; the interrupt enable register array table stores different register array values corresponding to each interrupt and peripheral interrupt under different priorities in the CPU chip, and the register array value is used for indicating the opening or closing function of each interrupt response process; and processing the target interrupt according to the target array value. The technical scheme of the embodiment of the application can realize the separate setting of the priority of all original interrupts and peripheral interrupts in the CPU chip, realizes interrupt nesting, and greatly reduces the software maintenance difficulty.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a chip interrupt processing method, device, equipment and storage medium. BACKGROUND

[0002] At present, the central processing unit (CPU) chip based on TMS320C28X architecture only supports 32 native interrupt lines (RESET, INT1~14, DLOGINT, RTOSINT, Reserved, NMI, ILLEGAL, USER1~12), and has to use intellectual property (IP) core to expand the interrupt lines INT1~12 into 12 groups of interrupts, and each group of interrupts is expanded into 16 interrupt lines, so as to meet the interrupt requirement of peripherals. However, the priorities of these interrupts are fixed and cannot be programmed, and do not have the ability of interrupt nesting, that is, during the execution process of the current interrupt, the interrupt with a higher priority than the current interrupt cannot interrupt it, and cannot effectively meet the requirement of real-time sensitive application scenarios.

[0003] In the prior art, a software development kit for realizing interrupt nesting is provided, but the kit can only set the interrupt priorities according to groups, and cannot set the priority of each interrupt individually, and the priority is set by manually setting a mask bit in the interrupt, so the setting result is not intuitive, and greatly increases the difficulty of software maintenance. SUMMARY

[0004] The present application provides a chip interrupt processing method, device, equipment and storage medium, which can realize individual setting of the priorities of all native interrupts and peripheral interrupts in the CPU chip, realizes interrupt nesting, and greatly reduces the difficulty of software maintenance.

[0005] According to an aspect of the present application, a chip interrupt processing method is provided, which comprises:

[0006] After detecting that a target interrupt in a CPU chip is triggered, a target priority corresponding to the target interrupt is determined in a hash table constructed in advance according to an interrupt number corresponding to the target interrupt;

[0007] In the hash table, a mapping relationship between each interrupt number and priority in the CPU chip is pre-stored;

[0008] According to the target priority, a target array value corresponding to the target interrupt is determined in a pre-constructed interrupt enable register array table;

[0009] The interrupt enable register array table pre-stores different register array values corresponding to each interrupt in the CPU chip and interrupts in the peripheral device under different priorities, and the register array values are used to indicate the opening or closing function of the interrupt response process.

[0010] According to the target array value corresponding to the target interrupt, the target interrupt is processed.

[0011] Optionally, before detecting that the target interrupt in the CPU chip is triggered, the method further comprises:

[0012] After detecting that the user triggers an interrupt priority setting request, the interrupt number and the priority carried in the setting request are obtained.

[0013] The mapping relationship between the interrupt number and the priority is stored in a hash table.

[0014] After detecting that the user triggers a registration function request, the interrupt number corresponding to the registration function request is queried in the hash table, and the interrupt processing function matched with the interrupt number according to the registration function request is registered.

[0015] Optionally, after the interrupt processing function matched with the interrupt number is registered, the method further comprises:

[0016] After detecting that the user triggers an interrupt enable request, the interrupt number in the interrupt enable request is obtained, and the interrupt corresponding to the interrupt number is enabled.

[0017] The priority corresponding to the interrupt enable request is queried in the hash table.

[0018] According to the priority corresponding to the interrupt enable request, the register array value matched with the interrupt enable request in the interrupt enable register array table is configured.

[0019] Optionally, according to the priority corresponding to the interrupt enable request, the register array value matched with the interrupt enable request in the interrupt enable register array table is configured, comprising:

[0020] In the interrupt enable register array table, the peripheral register bit corresponding to the interrupt enable request and the CPU register bit belonging to the peripheral register bit are queried.

[0021] In the peripheral register bit and the CPU register bit, the bit value lower than the priority is set to 1, and the bit value higher than or equal to the priority is set to 0.

[0022] Optionally, the method further comprises:

[0023] After detecting the user triggering the interrupt disable request, the priority corresponding to the interrupt disable request is queried in the hash table, and the priority corresponding to the interrupt disable request is updated to the lowest priority.

[0024] According to the lowest priority, a register array value matched with the interrupt disable request in an interrupt enable register array table is configured.

[0025] Optionally, according to the target array value corresponding to the target interrupt, the target interrupt is processed, including:

[0026] According to the interrupt number corresponding to the target interrupt, the interrupt processing function corresponding to the target interrupt is queried;

[0027] According to the target array value corresponding to the target interrupt and the interrupt processing function, the target interrupt is processed.

[0028] According to another aspect of the present application, a chip interrupt processing device is provided, the device comprising:

[0029] A priority determination module is configured to, after detecting that a target interrupt in a CPU chip is triggered, determine a target priority corresponding to the target interrupt in a pre-constructed hash table according to an interrupt number corresponding to the target interrupt.

[0030] The hash table pre-stores a mapping relationship between each interrupt number and priority in the CPU chip.

[0031] An array value determination module is configured to determine a target array value corresponding to the target interrupt in a pre-constructed interrupt enable register array table according to the target priority.

[0032] The interrupt enable register array table pre-stores different register array values corresponding to each interrupt and peripheral interrupt at different priorities in the CPU chip, and the register array value is used to indicate the opening or closing function of each interrupt response process.

[0033] An interrupt processing module is configured to process the target interrupt according to the target array value corresponding to the target interrupt.

[0034] According to another aspect of the present application, an electronic device is provided, the electronic device comprising:

[0035] At least one processor; and

[0036] A memory in communication connection with the at least one processor; wherein,

[0037] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the chip interrupt processing method according to any one of the embodiments of the application.

[0038] According to another aspect of the application, a computer readable storage medium is provided, which stores computer instructions for enabling a processor to implement the chip interrupt processing method according to any one of the embodiments of the application when executed by the processor.

[0039] According to another aspect of the application, a computer program product is provided, which implements the chip interrupt processing method according to any one of the embodiments of the application when executed by a processor.

[0040] The technical solution provided by the embodiments of the application comprises the following steps: after detecting that a target interrupt is triggered in a CPU chip, determining a target priority corresponding to the target interrupt in a hash table constructed in advance according to an interrupt number corresponding to the target interrupt; determining a target array value corresponding to the target interrupt in an interrupt enable register array table constructed in advance according to the target priority; and processing the target interrupt according to the target array value corresponding to the target interrupt. The technical solution can realize separate setting of priorities for all native interrupts and peripheral interrupts in the CPU chip, and greatly reduces the difficulty of software maintenance while realizing interrupt nesting.

[0041] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the application, nor is it used to limit the scope of the application. Other features of the application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0043] Figure 1 is a flowchart of a chip interrupt processing method according to an embodiment of the application;

[0044] Figure 2a is a flowchart of another chip interrupt processing method according to an embodiment of the application;

[0045] Figure 2b is a schematic diagram of configuring an interrupt enable register array table according to an embodiment of the application;

[0046] Figure 3 Fig. 1 is a structural schematic diagram of a chip interrupt processing device according to an embodiment of the present application;

[0047] Figure 4 Fig. 1 is a structural schematic diagram of a chip interrupt processing device according to an embodiment of the present application; DETAILED DESCRIPTION

[0048] In order to make the personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0049] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0050] Figure 1 Fig. 1 is a structural schematic diagram of a chip interrupt processing device according to an embodiment of the present application; Figure 1 As shown in the figure, the method comprises:

[0051] Step 110, after detecting that a target interrupt of a CPU chip is triggered, determining a target priority corresponding to the target interrupt in a hash table constructed in advance according to an interrupt number corresponding to the target interrupt.

[0052] In the embodiment, the CPU chip includes 32 native interrupt lines, wherein INT1-12 are extended to 12 groups of interrupts, and each group of interrupts is extended to 16 interrupt lines. Before the actual operation of the CPU chip, an interrupt priority hash table can be constructed in advance, and the hash table stores the mapping relationship between each interrupt number and the priority in the CPU chip. The interrupt number can be a fixed data value preset by the manufacturer corresponding to the interrupt line. Specifically, the hash table can be as shown in Table 1:

[0053]

[0054] Table 1

[0055] As shown in Table 1, each row of elements in the hash table includes the mapping relationship between the interrupt number (interruptNumber) and the interrupt priority (priority), and each interrupt number and the corresponding priority can be stored in the form of a key-value pair (Key-Value).

[0056] In this step, during the actual operation of the CPU chip, if it is detected that any interrupt is triggered, the interrupt can be taken as a target interrupt, and then the target priority corresponding to the target interrupt can be queried in the hash table according to the interrupt number of the target interrupt.

[0057] In a specific embodiment, if the priority corresponding to the target interrupt does not exist in the hash table, the target interrupt is processed by using an assertion mechanism.

[0058] Step 120, determining the target array value corresponding to the target interrupt in the pre-constructed interrupt enable register array table according to the target priority.

[0059] In the embodiment, the interrupt enable register array table can be as shown in Table 2, and the register array table pre-stores different register array values corresponding to different priorities of each interrupt (i.e., the 32 native interrupt lines) and peripheral interrupts (i.e., the 12 groups of extended interrupts) in the CPU chip, and the register array value is used to indicate the opening or closing function of the interrupt response process.

[0060]

[0061] Table 2

[0062] As shown in Table 2, each row in the array table of the interrupt enable register represents an array element, the index value of each array element is the priority, and each array element includes the CPU register (CPU IER) value corresponding to the native 32 interrupt lines and the peripheral register (PIE IER [1~12]) value corresponding to the peripheral interrupt. For example, in Table 2, the 0th bit of CPU IER corresponds to the interrupt line INT1, the 1st bit corresponds to the interrupt line INT2, the 2nd bit corresponds to the interrupt line INT3, and so on. PIE IER [1] corresponds to the extended interrupt line of the interrupt line INT1, PIE IER [2] corresponds to the extended interrupt line of the interrupt line INT2, and PIE IER

[12] corresponds to the extended interrupt line of the interrupt line INT12. The bit value in Table 2 is used to indicate the opening or closing of the response function of the corresponding interrupt. For example, when the bit value is 0, the response function of the corresponding interrupt is closed, and when the bit value is 1, the response function of the corresponding interrupt is opened.

[0063] In this step, the corresponding array element can be queried in the array table of the interrupt enable register with the target priority as the index, and then the array value corresponding to the array element is taken as the target array value.

[0064] Step 130, processing the target interrupt according to the target array value corresponding to the target interrupt.

[0065] In this step, specifically, 12 16-bit spaces can be allocated in the preset stack, the values of the 12 PIE IER registers in the target array value are pushed into the stack, then the target array value is written into the hardware register, and finally the global interrupt is enabled according to the array value in the hardware register, and the processing of the target interrupt is completed.

[0066] In this embodiment, after detecting that the user triggers the exit interrupt request, the global interrupt can be disabled, and then the values of the 12 PIE IER registers are popped out and written into the hardware register, so that the CPU chip exits the interrupt operation.

[0067] In this embodiment, by constructing the hash table and the array table of the interrupt enable register in the interrupt initialization process, a simple interrupt initialization method is provided. Compared with the prior art method of setting the interrupt priority and the interrupt mask bit by group, the priority of all native interrupts and peripheral interrupts can be set individually, the interrupt nesting is realized, the flexibility of the interrupt configuration process is improved, and the software maintenance difficulty is greatly reduced.

[0068] The technical scheme provided by the embodiment of the present application can realize separate setting of priorities of all native interrupts and peripheral interrupts in a CPU chip, while realizing interrupt nesting, and greatly reduce software maintenance difficulty.

[0069] Figure 2a The flow chart of another chip interrupt processing method provided by the embodiment of the present application is shown in FIG. 2, and the method comprises the following steps. Figure 2a

[0070] In step 210, after detecting that a user triggers an interrupt priority setting request, the interrupt number and the priority carried in the setting request are acquired, and the mapping relationship between the interrupt number and the priority is stored in a hash table.

[0071] In this step, the interrupt priority setting request can include the interrupt number and the corresponding priority. After the setting request is acquired, the hash table is queried for the interrupt number. If the hash table contains a consistent interrupt number, the priority corresponding to the interrupt number is modified to the priority specified in the setting request. If the hash table does not contain a consistent interrupt number, a new element is created in the hash table, and the mapping relationship between the interrupt number and the priority is stored in the new element.

[0072] In step 220, after detecting that a user triggers a registration function request, the hash table is queried for the interrupt number corresponding to the registration function request, and the interrupt processing function matched with the interrupt number is registered according to the registration function request.

[0073] In this step, the registration function request can include the interrupt number and the corresponding interrupt processing function. After the registration function request is acquired, the hash table is queried for the interrupt number. If the hash table contains a consistent interrupt number, the interrupt processing function matched with the interrupt number is registered. If the hash table does not contain a consistent interrupt number, a new element is created in the hash table, the interrupt number corresponding to the lowest priority is set in the new element, and then the interrupt processing function matched with the interrupt number is registered.

[0074] ​Step 230, after detecting that the user triggers the interrupt enable request, obtaining the interrupt number in the interrupt enable request, and enabling the interrupt corresponding to the interrupt number, querying the priority corresponding to the interrupt enable request in the hash table, and configuring the register array value in the interrupt enable register array table matched with the interrupt enable request according to the priority corresponding to the interrupt enable request.

[0075] In this step, specifically, the interrupt enable request can include an interrupt number. After obtaining the interrupt enable request, the interrupt number can be queried from the hash table. If there is a consistent interrupt number in the hash table, the register array value in the interrupt enable register array table is configured according to the priority corresponding to the interrupt number. If there is no consistent interrupt number in the hash table, a new element is created in the hash table, and the interrupt number corresponding to the lowest priority is set in the newly created element. Then, the register array value in the interrupt enable register array table is configured according to the lowest priority.

[0076] In one embodiment of the present embodiment, configuring the register array value in the interrupt enable register array table according to the priority corresponding to the interrupt enable request comprises: querying the peripheral register bit corresponding to the interrupt enable request and the CPU register bit belonging to it in the interrupt enable register array table; in the peripheral register bit and the CPU register bit, the bit value lower than the priority is set to 1, and the bit value higher than or equal to the priority is set to 0.

[0077] In a specific embodiment, Figure 2b A schematic diagram of configuring the interrupt enable register array table in the present embodiment can be as shown in Figure 2b As shown in the figure, assuming that the interrupt number corresponding to the priority 4 in the interrupt enable request triggered by the user includes the interrupt line indicated by the third bit in the PIE IER2 register, since the PIE IER2.Bit3 belongs to the CPU IER.Bit1, the values equal to or higher than 4 in the PIE IER2.Bit3 and the CPU IER.Bit1 can be set to 0, and the values lower than 4 can be set to 1.

[0078] Step 240, after detecting that the target interrupt in the CPU chip is triggered, determining the target priority corresponding to the target interrupt in the pre-constructed hash table according to the interrupt number corresponding to the target interrupt.

[0079] Step 250, determining the target array value corresponding to the target interrupt in the pre-constructed interrupt enable register array table according to the target priority.

[0080] Step 260, according to the interrupt number corresponding to the target interrupt, querying the interrupt processing function corresponding to the target interrupt; according to the target array value and the interrupt processing function corresponding to the target interrupt, processing the target interrupt.

[0081] The technical scheme provided by the embodiment of the application, after detecting that a user triggers an interrupt priority setting request, an interrupt number and a priority carried in the setting request are acquired; a mapping relationship between the interrupt number and the priority is stored in a hash table; after detecting that a user triggers a registration function request, the registration function request corresponding interrupt number is queried in the hash table; the interrupt processing function matched with the interrupt number according to the registration function request is registered; after detecting that a user triggers an interrupt enable request, the interrupt corresponding to the interrupt number is enabled; the priority corresponding to the interrupt enable request is queried in the hash table; the matched register array value is configured in the interrupt enable register array table according to the priority; after detecting that a target interrupt in a CPU chip is triggered, the target priority corresponding to the target interrupt is determined in the hash table according to the interrupt number corresponding to the target interrupt; the target array value corresponding to the target priority is determined in the interrupt enable register array table; the interrupt processing function is queried according to the interrupt number corresponding to the target interrupt; and the target interrupt is processed according to the target array value and the interrupt processing function corresponding to the target interrupt. The technical means can realize separate setting of priorities of all native interrupts and peripheral interrupts in the CPU chip, realize interrupt nesting, and greatly reduce software maintenance difficulty.

[0082] On the basis of the above embodiment, the method further comprises: after detecting that a user triggers an interrupt disable request, querying the priority corresponding to the interrupt disable request in the hash table, and updating the priority corresponding to the interrupt disable request to the lowest priority; according to the lowest priority, configuring the register array value matched with the interrupt disable request in the interrupt enable register array table.

[0083] Figure 3 A structure diagram of a chip interrupt processing device provided by the embodiment of the application is provided, and the device is applied to an electronic device, as shown in the figure, the device comprises a priority determination module 310, an array value determination module 320 and an interrupt processing module 330. Figure 3 The priority determination module 310 is configured to, after detecting that a target interrupt in a CPU chip is triggered, determine the target priority corresponding to the target interrupt in a pre-constructed hash table according to the interrupt number corresponding to the target interrupt.

[0084] The priority determination module 310 is configured to, after detecting that a target interrupt in a CPU chip is triggered, determine the target priority corresponding to the target interrupt in a pre-constructed hash table according to the interrupt number corresponding to the target interrupt.

[0085] The hash table pre-stores the mapping relationship between each interrupt number and the priority in the CPU chip.

[0086] The array value determination module 320 is configured to determine a target array value corresponding to the target interrupt in a pre-constructed interrupt enable register array table according to the target priority.

[0087] The interrupt enable register array table pre-stores different register array values corresponding to each interrupt and peripheral interrupt at different priorities in a CPU chip, and the register array value is used to indicate the opening or closing function of each interrupt response process.

[0088] The interrupt processing module 330 is configured to process the target interrupt according to the target array value corresponding to the target interrupt.

[0089] The technical scheme provided by the embodiment of the application can realize the separate setting of priorities for all native interrupts and peripheral interrupts in a CPU chip, realize interrupt nesting, and greatly reduce the difficulty of software maintenance by detecting that a target interrupt in the CPU chip is triggered, determining a target priority corresponding to the target interrupt in a pre-constructed hash table according to an interrupt number corresponding to the target interrupt, determining a target array value corresponding to the target interrupt in a pre-constructed interrupt enable register array table according to the target priority, and processing the target interrupt according to the target array value corresponding to the target interrupt.

[0090] On the basis of the above-mentioned embodiment, the device further comprises:

[0091] The priority setting module is configured to detect that a user triggers an interrupt priority setting request, acquire an interrupt number and a priority carried in the setting request, and store a mapping relationship between the interrupt number and the priority in a hash table.

[0092] The registration function module is configured to detect that a user triggers a registration function request, query an interrupt number corresponding to the registration function request in the hash table, and register an interrupt processing function matched with the interrupt number according to the registration function request.

[0093] The array value configuration module is configured to detect that a user triggers an interrupt enable request, acquire an interrupt number in the interrupt enable request, enable an interrupt corresponding to the interrupt number, query a priority corresponding to the interrupt enable request in the hash table, and configure a register array value matched with the interrupt enable request in an interrupt enable register array table according to the priority corresponding to the interrupt enable request.

[0094] The interrupt disabling module is configured to, after detecting that the user triggers the interrupt disabling request, query the priority corresponding to the interrupt disabling request in the hash table, and update the priority corresponding to the interrupt disabling request as the lowest priority; and configure the register array value matched with the interrupt disabling request in the interrupt enable register array table according to the lowest priority.

[0095] The array value configuration module comprises:

[0096] The bit position query unit is configured to query the peripheral register bit position corresponding to the interrupt enable request and the CPU register bit position belonging to the peripheral register bit position in the interrupt enable register array table.

[0097] The bit value setting unit is configured to set the bit value lower than the priority as 1 and the bit value higher than or equal to the priority as 0 in the peripheral register bit position and the CPU register bit position.

[0098] The interrupt processing module 330 comprises:

[0099] The interrupt response unit is configured to query the interrupt processing function corresponding to the target interrupt according to the interrupt number corresponding to the target interrupt, and process the target interrupt according to the target array value corresponding to the target interrupt and the interrupt processing function.

[0100] The device can perform the method provided by all the foregoing embodiments of the application, and has the corresponding function modules and beneficial effects of performing the foregoing method. Technical details not described in detail in the embodiments of the application can be referred to the method provided by all the foregoing embodiments of the application.

[0101] Figure 4 A structural diagram of an electronic device 10 that can be used to implement embodiments of the application is shown. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, tablets, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smart phones, wearable devices (e.g., headsets, glasses, watches, etc.), and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not intended to limit the implementations of the applications described and / or claimed in this document.

[0102] As Figure 4As shown, the electronic device 10 includes at least one processor 11, and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., communicatively connected to the at least one processor 11, where the memory stores a computer program executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or loaded into the random access memory (RAM) 13 from the storage unit 18. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0103] Various components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc., an output unit 17, such as various types of displays, a speaker, etc., a storage unit 18, such as a magnetic disk, an optical disk, etc., and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0104] The processor 11 can be various general and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs various methods and processes described above, such as the chip interrupt handling method.

[0105] In some embodiments, the chip interrupt handling method can be implemented as a computer program tangibly embodied in a computer readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the chip interrupt handling method described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform the chip interrupt handling method by any other appropriate means, such as by means of firmware.

[0106] The various embodiments of the systems and techniques described above can be implemented in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a load programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0107] Computer programs used to implement the processes of the application can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer program, when executed, can cause instructions defined in the flow charts and / or block diagrams to be implemented. The computer program can be executed entirely on a machine, partially on a machine, partially on a machine as a standalone software package and partially on a remote machine or entirely on a remote machine or server.

[0108] In the context of the present application, a computer-readable storage medium can be a tangible medium that can contain or store computer programs for use by or in connection with an instruction execution system, apparatus, or device. Computer-readable storage media can include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of the machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0109] To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0110] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0111] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. A server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system, to solve the defects of large management difficulty and weak business scalability in traditional physical host and VPS service.

[0112] It should be understood that the various forms of flow shown above can be re-ordered, added to, or deleted from without departing from the scope of the present disclosure. For example, the steps recited in the present disclosure can be executed in parallel, executed in sequence, or executed in a different order, as long as the desired results of the present disclosure are achieved, and the present disclosure is not limited herein.

[0113] The specific embodiments described hereinabove are illustrative only and not restrictive. One skilled in the art will appreciate that variations and modifications can be made to the specifics described herein without departing from the spirit and principles of the application. Accordingly, the scope of protection is not limited to the specific details described herein but is given by the appended claims.

Claims

1. A method of handling a chip interrupt, the method comprising: The method comprises: After detecting that a target interrupt in a central processing unit (CPU) chip is triggered, a target priority corresponding to the target interrupt is determined in a hash table constructed in advance according to an interrupt number corresponding to the target interrupt; The hash table pre-stores a mapping relationship between each interrupt number and a priority in the CPU chip; A target array value corresponding to the target interrupt is queried in a pre-constructed interrupt enable register array table with the target priority as an index; The interrupt enable register array table pre-stores different register array values corresponding to different priorities of each interrupt and peripheral interrupt in the CPU chip, and the register array value is used to indicate the opening or closing function of the interrupt response process; The target interrupt is processed according to the target array value corresponding to the target interrupt; The method further comprises: Before detecting that a target interrupt in a central processing unit (CPU) chip is triggered, an interrupt number and a priority carried in a setting request triggered by a user are acquired after detecting that the user triggers the interrupt priority setting request; a mapping relationship between the interrupt number and the priority is stored in a hash table; after detecting that a user triggers a registration function request, an interrupt number corresponding to the registration function request is queried in the hash table, and an interrupt processing function matched with the interrupt number is registered according to the registration function request; After detecting that a user triggers an interrupt enable request, an interrupt number in the interrupt enable request is acquired, and an interrupt corresponding to the interrupt number is enabled; a priority corresponding to the interrupt enable request is queried in the hash table; a register array value matched with the interrupt enable request is configured in an interrupt enable register array table according to the priority corresponding to the interrupt enable request.

2. The method of claim 1, wherein, Configuring the register array value matched with the interrupt enable request in the interrupt enable register array table according to the priority corresponding to the interrupt enable request comprises: In the interrupt enable register array table, a peripheral register bit corresponding to the interrupt enable request and a CPU register bit belonging to the peripheral register bit are queried; In the peripheral register bit and the CPU register bit, a bit value lower than the priority is set to 1, and a bit value higher than or equal to the priority is set to 0.

3. The method of claim 1, wherein, The method further comprises: After detecting that a user triggers an interrupt disable request, a priority corresponding to the interrupt disable request is queried in the hash table, and the priority corresponding to the interrupt disable request is updated to a lowest priority; According to the lowest priority, a register array value matched with the interrupt disable request is configured in an interrupt enable register array table.

4. The method of claim 1, wherein, Processing the target interrupt according to the target array value corresponding to the target interrupt comprises: According to the interrupt number corresponding to the target interrupt, an interrupt processing function corresponding to the target interrupt is queried; The target interrupt is processed according to the target array value corresponding to the target interrupt and the interrupt processing function.

5. A chip interrupt processing apparatus characterized by comprising: The device comprises: The priority determination module is configured to, after detecting that a target interrupt in a central processing unit (CPU) chip is triggered, determine a target priority corresponding to the target interrupt in a hash table constructed in advance according to an interrupt number corresponding to the target interrupt. The hash table pre-stores a mapping relationship between each interrupt number and a priority in the CPU chip. The array value determination module is configured to, taking the target priority as an index, query a target array value corresponding to the target interrupt in a pre-constructed interrupt enable register array table. The interrupt processing module is configured to process the target interrupt according to the target array value corresponding to the target interrupt. The device is further configured to, before detecting that a target interrupt in a central processing unit (CPU) chip is triggered, after detecting that a user triggers an interrupt priority setting request, acquire an interrupt number and a priority carried in the setting request; store the mapping relationship between the interrupt number and the priority in a hash table; after detecting that the user triggers a registration function request, query an interrupt number corresponding to the registration function request in the hash table, and register an interrupt processing function matched with the interrupt number according to the registration function request. After detecting that the user triggers an interrupt enable request, acquire an interrupt number in the interrupt enable request, and enable an interrupt corresponding to the interrupt number; query a priority corresponding to the interrupt enable request in the hash table; and according to the priority corresponding to the interrupt enable request, configure a register array value matched with the interrupt enable request in an interrupt enable register array table. The electronic device includes:

6. An electronic device, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the chip interrupt processing method in any one of claims 1-4. The computer readable storage medium stores computer instructions for enabling the processor to implement the chip interrupt processing method in any one of claims 1-4 when executed.

7. A computer-readable storage medium, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the chip interrupt processing method according to any one of claims 1-4.

8. A computer program product, characterised in that, The computer program product includes a computer program that, when executed by a processor, implements the chip interrupt processing method according to any one of claims 1-4.

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