Baud rate detection method, control device and storage medium

Abstract

The embodiment of the invention relates to the technical field of communication, in particular to a baud rate detection method, a control device and a storage medium, the method is applied to the control device, the control device is in communication connection with an upper computer through a communication interface, the upper computer is used for sending a baud rate detection frame to the control device, and the control device comprises a first counter. The method comprises the steps that a first count value of a first counter is acquired, the first count value represents a target period of a control device receiving a baud rate detection frame, the control device adopts the number of system clocks to represent the target period, and the baud rate of a communication interface is acquired based on the first count value. According to the embodiment of the invention, the target period of the control device for receiving the baud rate detection frame is obtained by counting through the first counter, so that the baud rate of the communication interface is detected, the baud rate detection precision is improved, the baud rate detection error of the communication interface can be reduced, and the user experience is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communication technology, and in particular to a baud rate detection method, a control device, and a storage medium. Background Art

[0002] Pin resources are extremely valuable for ASIC chips. Since serial communication requires fewer pins, it's often used to communicate between the ASIC chip and the host computer in situations where communication speed requirements aren't high. However, serial communication lacks a synchronized clock. To flexibly meet the host computer's varying baud rate requirements, the ASIC chip needs to have baud rate recognition capabilities. Furthermore, even if the baud rate between the host computer and the ASIC chip is agreed upon, the ASIC chip's internal clock often deviates from the set clock before system clock correction is performed, causing serial communication failures. Therefore, the ASIC chip also needs to have baud rate recognition capabilities to match the host computer's communication baud rate.

[0003] In related technologies, the internal clock frequency of the ASIC chip is low, and its accuracy is also low. When performing baud rate recognition, the baud rate recognition accuracy is low, which can easily lead to communication errors or failures, bring unknown risks, and reduce user experience. Summary of the Invention

[0004] In view of this, an object of an embodiment of the present invention is to provide a baud rate detection method, a control device and a storage medium, aiming to solve the technical problem in the prior art that low baud rate recognition accuracy easily leads to communication errors or failures.

[0005] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] In a first aspect, an embodiment of the present invention provides a baud rate detection method, which is applied to a control device, wherein the control device is communicatively connected to a host computer via a communication interface, and the host computer is used to send a baud rate detection frame to the control device, wherein the control device includes a first counter;

[0007] The method comprises:

[0008] Obtaining a first count value of the first counter, wherein the first count value represents a target period for the control device to receive the baud rate detection frame, and the control device uses the number of system clocks to represent the target period;

[0009] Based on the first count value, a baud rate of the communication interface is obtained.

[0010] In some embodiments, the baud rate detection frame includes multiple bits of detection data, and the control device further includes a second counter configured to count the amount of detection data received by the control device;

[0011] The obtaining the first count value of the first counter includes:

[0012] In response to receiving the first bit detection data, controlling the first counter and the second counter to start counting, wherein the second counter increases a count value each time it is detected that the control device has completed receiving a bit of detection data, and the first counter increases a count value each time a rising edge of the system clock of the control device is detected, wherein the first bit detection data is the first bit detection data in the baud rate detection frame;

[0013] obtaining a second count value of the second counter, and controlling the second counter to stop counting if the second count value is the same as the first amount of detection data in the baud rate detection frame;

[0014] In response to receiving the last bit detection data and the second count value being the same as the first number, the first counter is controlled to stop counting and the first count value of the first counter is obtained. The last bit detection data is the last bit detection data in the baud rate detection frame.

[0015] In some embodiments, the step of responding to receiving the first bit detection data includes:

[0016] The level of the communication interface is acquired, and based on the level of the communication interface, a response is made to determine that the control device has received the first bit detection data.

[0017] In some embodiments, the baud rate detection frame further includes a start bit, and the response of determining that the control device has received the first bit of detection data based on the level of the communication interface includes:

[0018] If the start bit is at a low level and the level of the communication interface changes from a low level to a high level, it is determined that the control device has received the first bit detection data; or

[0019] If the start bit is at a high level and the level of the communication interface changes from a high level to a low level, it is determined that the control device has received the first bit detection data.

[0020] In some embodiments, the baud rate detection frame further includes a stop bit, and the step of detecting the last bit of the data in response to receiving the completion bit includes:

[0021] If it is detected that the communication interface receives the stop bit, the end bit detection data is responded to determine that the reception is completed.

[0022] In some embodiments, before controlling the first counter and the second counter to start counting in response to receiving the first bit detection data, the method further includes:

[0023] Determine whether the bit width of the first counter meets a preset condition.

[0024] In some embodiments, determining whether the bit width of the first counter meets a preset condition includes:

[0025] Obtaining the minimum baud rate of the communication interface;

[0026] Obtaining a first frequency of the system clock, and determining a minimum bit width of the first counter based on the first frequency and the minimum baud rate;

[0027] The bit width of the first counter is obtained. If the bit width of the first counter is greater than or equal to the minimum bit width, it is determined that the bit width of the first counter meets a preset condition.

[0028] In some embodiments, obtaining the baud rate of the communication interface based on the first count value includes:

[0029] Dividing the first count value by the first quantity to obtain a first quotient and a first remainder;

[0030] If the first remainder is greater than or equal to a first preset value, adding the first quotient to a second preset value to obtain the baud rate of the communication interface;

[0031] If the first remainder is smaller than the first preset value, the first quotient value is determined to be the baud rate of the communication interface.

[0032] In a second aspect, an embodiment of the present invention provides a control device, including:

[0033] a processor and a memory communicatively connected to the processor, a first counter and a second counter, wherein the first counter is used to count a target period of the baud rate detection frame received by the control device, and the second counter is used to count the amount of detection data received by the control device;

[0034] The memory stores computer program instructions executable by the processor. When the computer program instructions are called by the processor, the processor executes any one of the baud rate detection methods proposed in the first aspect.

[0035] In a third aspect, an embodiment of the present invention provides a computer-readable storage medium, on which computer program instructions executable by a processor are stored. When the computer program instructions are called by the processor, the processor executes any one of the baud rate detection methods proposed in the first aspect.

[0036] The embodiments of the present invention have the following beneficial effects: Different from the existing technology, the baud rate detection method provided by the embodiments of the present invention is applied to a control device, the control device is communicatively connected to a host computer through a communication interface, the host computer is used to send a baud rate detection frame to the control device, the control device includes a first counter, and the method includes: obtaining a first count value of the first counter, the first count value represents a target period for the control device to receive the baud rate detection frame, the control device uses the number of system clocks to represent the target period, and obtains the baud rate of the communication interface based on the first count value.

[0037] The embodiment of the present invention uses the first counter to count and obtain the target period of the control device receiving the baud rate detection frame to detect the baud rate of the communication interface, thereby improving the baud rate detection accuracy, reducing the baud rate detection error, reducing or avoiding the occurrence of communication errors or failures due to low baud rate detection accuracy, reducing or avoiding unknown security risks, ensuring the smooth transmission of communication data between the control device and the host computer, and improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for describing the prior art or embodiments. Obviously, the drawings described below only illustrate certain embodiments of the present invention and should not be construed as limiting the scope of protection. Those skilled in the art can, without inventive effort, derive other relevant drawings based on these drawings.

[0039] Figure 1 Schematic diagram of application scenarios of baud rate detection in some embodiments of the present invention;

[0040] Figure 2 Schematic diagram of the serial communication principle between the ASIC chip and the host computer in some embodiments of the present invention;

[0041] Figure 3 is a schematic structural diagram of a control device provided by some embodiments of the present invention;

[0042] Figure 4 is a flow chart of a baud rate detection method provided by some embodiments of the present invention;

[0043] Figure 5 is a schematic diagram of the format of serial communication data in some embodiments of the present invention;

[0044] Figure 6 is a schematic diagram of a control device receiving a baud rate detection frame in some embodiments of the present invention;

[0045] Figure 7 is a schematic diagram of a system clock in some embodiments of the present invention;

[0046] Figure 8 is a schematic structural diagram of a baud rate detection device provided by some embodiments of the present invention;

[0047] Figure 9 Schematic diagram of the structure of the baud rate detection device provided by other embodiments of the present invention. DETAILED DESCRIPTION

[0048] In order to make the purposes and advantages of the embodiments of the present invention easier to understand, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. The detailed description of the embodiments of the present invention in the drawings below does not limit the scope of protection claimed by the present invention, but only represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0049] It should be noted that, if no conflict is constituted, the various technical features involved in the embodiments of the present invention described below can be combined with each other and are all within the scope of protection of the present invention. In addition, although the functional modules are divided in the device or structural diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a different module division than in the device or in an order different from that in the flow chart. In addition, the "first", "second", "third" and other similar expressions used herein do not limit the data and execution order, but are only for the purpose of convenience of explanation and to distinguish between the same items or similar items with basically the same functions and effects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features.

[0050] Unless otherwise defined, the technical and scientific terms used in this specification have the same meanings as those commonly understood by those skilled in the art within the technical field of the present invention. The terms used in this specification are intended solely to describe specific embodiments and are not intended to limit the present invention. It should be understood that the term "and / or" as used in this specification includes any and all combinations of one or more of the relevant listed items.

[0051] See also Figure 1 , Figure 1The following schematically illustrates an application scenario of baud rate detection in some embodiments of the present invention.

[0052] Specifically, if Figure 1 As shown, the control device 100 is communicatively connected to the host computer 200 via the communication interface 150, and the host computer 200 is configured to send a baud rate detection frame to the control device 100. The control device 100 includes a first counter 110, which is connected to the communication interface 150 and is configured to count the target period during which the control device 100 receives the baud rate detection frame. The control device 100 uses the number of system clocks to represent the target period, i.e., the number of system clocks required for the control device 100 to receive the baud rate detection frame. It should be understood that the first counter 110 can be implemented using hardware, software, or a combination of hardware and software, and this embodiment of the present invention does not impose any limitation on this.

[0053] In some embodiments, the host computer 200 can be any suitable type of device or apparatus such as a tablet computer, a desktop computer, a laptop computer, etc., and the control device 100 can be any suitable device or component such as a single-chip microcomputer, a microcontroller, various control chips, for example, the control device 100 is an ASIC chip.

[0054] Pin resources are extremely valuable for ASIC chips. Since serial communication requires relatively few pins, it is often used to communicate between the ASIC chip and the host computer in situations where communication speed requirements are low. Since serial communication lacks a synchronized clock, the ASIC chip must have a baud rate detection function to flexibly meet the host computer's communication requirements at different baud rates. Furthermore, even if the ASIC chip has a pre-agreed baud rate for communication with the host computer, its internal clock may deviate from the set clock before system clock correction is performed, causing serial communication failure. Therefore, baud rate detection is also necessary to match the host computer's communication baud rate.

[0055] In some embodiments, the serial communication principle between the ASIC chip and the host computer is as follows: Figure 2As shown. The ASIC chip 300 includes a core module 310, a digital-to-analog conversion module 320, a UART pin, and a GND pin. The UART pin is the serial communication pin of the ASIC chip, used for communication with the host computer 200. The GND pin is the ground pin of the ASIC chip, used for grounding. The ASIC chip 300 communicates with the host computer 200 via the UART pin, meaning the UART pin serves as a communication interface. The core module 310 includes a UART module 311 and a first counter 312. Baud rate detection frames are transmitted via the UART pin, which converts the baud rate detection frames into UART signals, which are then transmitted to the digital-to-analog conversion module 320. The digital-to-analog conversion module 320 is used to convert the UART signal into a TX signal and an RX signal, where the RX signal and the TX signal are respectively the data receiving signal and the data transmitting signal of the core module 310. The UART module 311 is used to parse and process the data signal (including the TX signal and the RX signal). The first counter 312 is used to count the target period of the UART module 311 receiving the baud rate detection frame, thereby counting the target period of the ASIC chip 300 receiving the baud rate detection frame.

[0056] The inventors have discovered that traditional ASIC chips, due to their low internal clock frequency, have low baud rate detection accuracy when performing baud rate detection, which can easily lead to communication errors and introduce unknown risks. To address the problem of low baud rate detection accuracy in serial communication, an embodiment of the present invention provides a baud rate detection method. This method obtains a first count value of a first counter, which represents a target period for a control device to receive a baud rate detection frame. The control device uses the number of system clocks to represent the target period, and obtains the baud rate of the communication interface based on the first count value. This method can improve the baud rate detection accuracy of the ASIC chip, reduce baud rate detection errors, and minimize or avoid communication errors or failures caused by low baud rate detection accuracy.

[0057] It can be understood that the above content is explained using the control device 100 as an ASIC chip as an example. In embodiments where the control device 100 is any other suitable type of device or component, the control device 100 can be connected to the host computer through any suitable communication interface, thereby receiving the baud rate detection frame sent by the host computer, and counting the target period of the received baud rate detection frame through a counter to detect the baud rate of the communication interface, thereby improving the baud rate detection accuracy, reducing the error of the baud rate detection, and reducing or avoiding communication errors or failures due to low baud rate detection accuracy.

[0058] It should be understood that Figure 1The control device 100 is only schematically shown to be connected to the host computer 200 for communication to detect the baud rate of the communication interface, which does not impose any restrictions on the structure, type, quantity, etc. of the control device and the host computer in other application scenarios or embodiments. For example, in other application scenarios or embodiments, the control device can also be a single-chip microcomputer, a microcontroller, or any other suitable type of device or component. In addition, the control device and the host computer in other application scenarios or embodiments can also be more Figure 1 The control device and host computer shown may include more or fewer components, or have the same Figure 1 The control device and the host computer are shown in different configurations.

[0059] In order to facilitate understanding of the baud rate detection method provided by the embodiment of the present invention, the control device provided by the embodiment of the present invention is first introduced in detail.

[0060] See also Figure 3 , Figure 3 The structural diagram of the control device 400 provided in some embodiments of the present invention is schematically shown.

[0061] like Figure 3 As shown, the control device 400 includes at least one processor 410, a memory 420, a first counter 430 and a second counter 440 that are communicatively connected. The first counter 430 is used to count the target period of the baud rate detection frame received by the control device 400, and the second counter 440 is used to count the number of detection data received by the control device 400. Figure 3 In the example, the bus system 430 is connected to a processor. The various components in the control device 400 are coupled together through the bus system 430, and the bus system 430 is used to realize the connection and communication between the various components. It is easy to understand that the bus system 430 includes not only a data bus, but also a power bus, a control bus, and a status signal bus. However, for the sake of clarity and brevity, Figure 3 In FIG. 4 , various buses are labeled as bus system 430. It can be understood that Figure 3 The structure shown in the embodiment is only for illustration and does not impose any limitation on the structure of the above control device. For example, the above control device may also include Figure 3 The structures shown may have more or fewer components, or may have Figure 3 Different configurations of the structure are shown.

[0062] Specifically, the processor 410 is used to provide computing and control capabilities to control the control device 400 to perform corresponding tasks, such as controlling the above-mentioned control device 400 to perform any baud rate detection method provided in the embodiment of the present invention, or to perform the steps in any possible implementation of any baud rate detection method provided in the embodiment of the present invention. Those skilled in the art will understand that the processor 410 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component.

[0063] The memory 420 is a non-transitory computer-readable storage medium that can be used to store non-transitory software programs, non-transitory computer executable programs, instructions, and modules, for example, programs, instructions, and modules corresponding to the baud rate detection method in the embodiment of the present invention. In some embodiments, the memory 420 may include a program storage area and a data storage area. The program storage area may store an operating system, an application required for at least one function, and the data storage area may store data created according to the use of the processor 410. The processor 410 executes various functional applications and data processing of the control device 400 by running the non-transitory software programs, instructions, and modules stored in the memory 420 to implement any baud rate detection method provided in the embodiment of the present invention, or to perform any step in any possible implementation of any baud rate detection method provided in the embodiment of the present invention. In some embodiments, the memory 420 may include a high-speed random access memory and may also include a non-transitory memory. For example, at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 420 may also include a memory remotely located relative to the processor 410, and these remotely located memories may be connected to the processor 410 via a communication network. It is understandable that examples of the above-mentioned communication network include but are not limited to the Internet, corporate intranet, local area network, mobile communication network and combinations thereof.

[0064] As can be understood from the foregoing, any baud rate detection method provided in the embodiments of the present invention may be implemented by any suitable type of control device having certain computing and control capabilities, for example, the control device 400 described above. In some feasible implementations, any baud rate detection method provided in the embodiments of the present invention may be implemented by a processor invoking computer program instructions stored in a memory.

[0065] The baud rate detection method provided by the embodiment of the present invention will be described in detail below in conjunction with exemplary applications and implementations of the control device provided by the embodiment of the present invention.

[0066] See also Figure 4 , Figure 4 The flowchart of the baud rate detection method provided by some embodiments of the present invention is schematically shown.

[0067] Those skilled in the art will appreciate that the baud rate detection method provided in the embodiment of the present invention can be applied to the above control device (eg, control device 400). Specifically, the baud rate detection method is executed by one or at least two processors of the control device.

[0068] like Figure 4 As shown, the baud rate detection method includes but is not limited to the following steps S100-S200:

[0069] S100: Obtain a first count value of a first counter.

[0070] In this step, the control device is communicatively connected to a host computer via a communication interface, wherein the host computer is configured to send a baud rate detection frame to the control device. The control device includes a first counter configured to count a target period during which the control device receives the baud rate detection frame to obtain a first count value, wherein the first count value represents the target period during which the control device receives the baud rate detection frame. The control device represents the target period using the number of system clocks.

[0071] In some embodiments, the serial communication data carrying the baud rate detection frame is as follows: Figure 5 As shown, the serial communication data includes a baud rate detection frame, an address frame, a read / write control frame, a data frame, and a check frame. The first frame of the serial communication data is the baud rate detection frame, the second frame is the address frame, the third frame is the read / write control frame, the fourth frame is the data frame, and the last frame is the check frame. The address frame is used to represent the address information of the serial communication data, the read / write control frame is used for read / write control of the serial communication data, the data frame represents the actual data transmitted by the serial communication data, and the check frame is used to verify whether the serial communication data is correctly received. After the control device parses the baud rate detection frame to obtain the baud rate for communication with the host computer (i.e., the communication interface), it parses the subsequent address frame, read / write control frame, data frame, and check frame.

[0072] Specifically, after establishing a communication connection with the control device via a communication interface, the host computer sends serial communication data to the control device. The control device receives the serial communication data, parses the baud rate detection frame of the serial communication data, and uses a first counter to count the target period for receiving the baud rate detection frame. That is, the first counter counts the number of system clocks required to receive the baud rate detection frame to obtain a first count value. The first count value represents the target period for receiving the baud rate detection frame by the control device.

[0073] In some embodiments, after the control device receives the baud rate detection frame and the first counter completes counting, the control device obtains a count value from the first counter to obtain a first count value of the first counter.

[0074] Of course, the first counter may also send the count value (ie, the first count value) to the control device after counting is completed, so that the control device obtains the first count value of the first counter.

[0075] In some embodiments, obtaining the first count value of the first counter specifically includes but is not limited to the following steps S110-S130:

[0076] S110: In response to receiving the first bit detection data, controlling the first counter and the second counter to start counting, the first bit detection data being the first bit detection data in the baud rate detection frame.

[0077] In some embodiments, the baud rate detection frame includes multiple bits of detection data, for example, see Figure 6 , Figure 6 The format of a baud rate detection frame in some embodiments of the present invention is shown. The baud rate detection frame includes 8 bits of detection data, which are arranged in the order of 1, 0, 1, 0, 1, 0, 1, 0. The control device also includes a second counter for counting the amount of detection data received by the control device.

[0078] Specifically, when receiving the first bit detection data, the control device controls the first counter and the second counter to start, and controls the first counter and the second counter to start counting. Among them, the first counter is used to count the number of system clocks. The definition of a system clock is as follows Figure 7 As shown, a system clock is defined as the period from one rising edge of the system clock to the next. Therefore, each time a rising edge of the control device's system clock is detected, the first counter increments by one, thereby counting one system clock. The second counter is used to count the amount of detection data received by the control device. Each time it detects that the control device has received a bit of detection data, the second counter increments by one, thereby counting one bit of detection data. It is understood that the first bit of detection data is the first bit of detection data in the baud rate detection frame.

[0079] In some embodiments, in response to receiving the first bit detection data, before controlling the first counter and the second counter to start counting, the baud rate detection method further includes but is not limited to the following steps S101:

[0080] S101: Determine whether the bit width of a first counter meets a preset condition.

[0081] In this step, to ensure that the bit width of the first counter can meet the number of system clocks required to count the received baud rate detection frames, before controlling the first counter to start counting, it is first determined whether the bit width of the first counter meets a preset condition.

[0082] In some embodiments, the control device obtains the bit width of a first counter stored locally, compares the bit width of the first counter with a preset bit width threshold, and if the bit width of the first counter is greater than or equal to the bit width threshold, indicating that the first counter can be used to count the number of system clocks required to receive the baud rate detection frame, the control device determines that the bit width of the first counter meets the preset condition. If the bit width of the first counter is less than the preset bit width threshold, indicating that the first counter cannot be used to count the number of system clocks required to receive the baud rate detection frame, the control device determines that the bit width of the first counter does not meet the preset condition.

[0083] In some embodiments, the control device may obtain the bit width of the first counter from the first counter, or the first counter may send its bit width to the control device, and the control device may obtain the bit width of the first counter.

[0084] In some embodiments, determining whether the bit width of the first counter meets a preset condition specifically includes but is not limited to the following steps S1011-S1013:

[0085] S1011: Obtain the minimum baud rate of the communication interface.

[0086] S1012: Acquire a first frequency of the system clock, and determine a minimum bit width of the first counter based on the first frequency and the minimum baud rate.

[0087] S1013: Obtain the bit width of the first counter. If the bit width of the first counter is greater than or equal to the minimum bit width, determine that the bit width of the first counter meets a preset condition.

[0088] In this step, the control device obtains the minimum baud rate of the communication interface and the first frequency of the system clock from local storage, and calculates the minimum bit width of the first counter based on the first frequency and the minimum baud rate. The minimum bit width of the first counter can be calculated using the following first calculation formula: that is, the first frequency and the minimum baud rate are substituted into the first calculation formula to obtain the minimum bit width of the first counter.

[0089] Among them, the first calculation formula is:

[0090]

[0091] In the above formula, m is the minimum bit width of the first counter, and the solution is Y is the first frequency of the system clock, and X is the minimum baud rate of the communication interface.

[0092] Specifically, the control device obtains the bit width of the first counter stored locally, compares the bit width of the first counter with the minimum bit width, and if the bit width of the first counter is greater than or equal to the minimum bit width, it indicates that the first counter can be used to count the number of system clocks required to receive the baud rate detection frame, and it is determined that the bit width of the first counter meets the preset condition. If the bit width of the first counter is less than the minimum bit width, it indicates that the first counter cannot be used to count the number of system clocks required to receive the baud rate detection frame, and it is determined that the bit width of the first counter does not meet the preset condition.

[0093] In some embodiments, in response to receiving the first bit detection data, the steps specifically include but are not limited to the following steps S111:

[0094] S111: Acquire the level of the communication interface, and based on the level of the communication interface, respond to determine that the control device has received the first bit of detection data.

[0095] Specifically, the control device obtains the level of the communication interface and responds to determine whether the first bit of detection data has been received based on changes in the level of the communication interface. In some embodiments, when the detection data begins to be received, there is a significant change in the level of the communication interface, such as a jump from a low level to a high level, a high level to a low level, or a specific level. The control device determines whether the first bit of detection data of the baud rate detection frame has been received by monitoring the change in the level of the communication interface.

[0096] For example, if the level of the communication interface jumps from the first level in the initialization state to the preset second level, it means that the control device starts to receive the detection data, and then it is determined in response that the control device has received the first bit of detection data.

[0097] In some embodiments, based on the level of the communication interface, responding to determine that the control device has received the first bit of detection data specifically includes but is not limited to the following steps S1111:

[0098] S1111: If the start bit is at a low level and the level of the communication interface changes from a low level to a high level, it is determined that the control device has received the first bit of detection data.

[0099] In this step, the baud rate detection frame also includes a start bit. Figure 6 , Figure 6The format of the baud rate detection frame in some embodiments of the present invention is shown, wherein the baud rate detection frame includes a start bit 0 and 8 bits of detection data, the detection data is located after the start bit 0, and the 8 bits of detection data are arranged in the order of 1, 0, 1, 0, 1, 0, 1, 0.

[0100] In some embodiments, the start bit of the baud rate detection frame can be configured as a low level or a high level, and when receiving the detection data, the level of the communication interface changes. When the level change of the communication interface meets the corresponding level change condition, it is determined that the control device has received the first bit of the detection data.

[0101] In some embodiments, the start bit of the baud rate detection frame is configured to be low level. If the start bit is low level and the level of the communication interface changes from low level to high level, it is determined that the control device has received the first bit of detection data. Figure 6 As shown, the start bit of the baud rate detection frame is configured to be low level. If the level of the communication interface changes from low level to high level, it is determined that the control device has received the first bit of detection data (ie, the first bit of detection data 1).

[0102] Alternatively, in some embodiments, based on the level of the communication interface, in response to determining that the control device has received the first bit of detection data, specifically includes but is not limited to the following steps S1112:

[0103] S1112: If the start bit is at a high level and the level of the communication interface changes from a high level to a low level, it is determined that the control device has received the first bit of detection data.

[0104] In some embodiments, the start bit of the baud rate detection frame is configured to be high level. If the start bit is high level and the level of the communication interface changes from high level to low level, it is determined that the control device has received the first bit of detection data.

[0105] S120: Obtain a second count value of the second counter, and if the second count value is the same as the first number of detection data in the baud rate detection frame, control the second counter to stop counting.

[0106] Specifically, the control device obtains the count value from the second counter to obtain the second count value of the second counter. Alternatively, in some embodiments, the second counter sends its count value to the control device, so that the control device obtains the second count value of the second counter.

[0107] Then the second count value is compared with the first number of detection data in the baud rate detection frame. If the second count value is the same as the first number of detection data in the baud rate detection frame, the control device sends a stop counting instruction to the second counter to control the second counter to stop counting.

[0108] S130: In response to receiving the last bit detection data and the second count value being the same as the first number, control the first counter to stop counting and obtain the first count value of the first counter, where the last bit detection data is the last bit detection data in the baud rate detection frame.

[0109] Specifically, when the last bit detection data is received and the second count value is the same as the first number, the control device sends a stop counting instruction to the first counter, controls the first counter to stop counting, and obtains the first count value of the first counter. It can be understood that the last bit detection data is the last bit detection data in the baud rate detection frame.

[0110] In some embodiments, in response to receiving the final detection data, the steps include but are not limited to the following steps S131:

[0111] S131: If it is detected that the communication interface receives the stop bit, respond to determine that the reception of the last bit detection data is completed.

[0112] In this step, the baud rate detection frame also includes a stop bit. Figure 6 , Figure 6 The format of the baud rate detection frame in some embodiments of the present invention is shown. The baud rate detection frame includes a start bit 0, a stop bit 1, and 8 bits of detection data. The detection data is located after the start bit 0 and before the stop bit 1. The 8 bits of detection data are arranged in the order of 1, 0, 1, 0, 1, 0, 1, 0.

[0113] Specifically, if it is detected that the communication interface receives the stop bit 1, the control device responds to determine that the reception of the last bit detection data is completed. It should be understood that any other appropriate method can also be used to determine whether the reception of the last bit detection data is completed. For example, based on the level of the start bit 0 configuration and the level change corresponding to the 8-bit detection data, it can be determined whether the level change of the communication interface during the reception of the baud rate detection frame meets the expected level change condition. If the level change of the communication interface during the reception of the baud rate detection frame meets the expected level change condition, it is determined that the reception of the last bit detection data is completed. For example, please refer to Figure 6 , configure the start bit 0 to a low level, then the expected level change condition of the communication interface during the reception of the baud rate detection frame is low → high → low → high → low → high → low → high → low → high → low → high. If the level change of the communication interface during the reception of the baud rate detection frame meets the expected level change condition: low → high → low → high → low → high → low → high → low → high, it is determined that the reception of the last bit detection data is completed.

[0114] S200: Obtaining a baud rate of the communication interface based on the first count value.

[0115] In this step, after obtaining the first count value of the first counter, the baud rate of the communication interface is calculated in combination with the frequency of the system clock.

[0116] Specifically, the control device obtains the frequency of the system clock and calculates the baud rate of the communication interface according to the first count value and the frequency of the system clock, that is, divides the frequency of the system clock by the first count value to obtain the baud rate of the communication interface.

[0117] Of course, any other suitable manner or method may be used to calculate the baud rate of the communication interface, and the embodiment of the present invention does not impose any limitation on this. For example, refer to Figure 6 The first count value of the first counter is 32, and the first number (that is, the number of detection data in the baud rate detection frame) is 8. The first count value 32 is divided by the first number 8 to obtain the baud rate 4 of the communication interface, that is, the number of system clocks required to receive each bit of detection data is 4.

[0118] In some embodiments, obtaining the baud rate of the communication interface based on the first count value includes, but is not limited to, the following steps S210-S230:

[0119] S210: Divide the first count value by the first quantity to obtain a first quotient and a first remainder.

[0120] S220: If the first remainder is greater than or equal to the first preset value, add the first quotient and the second preset value to obtain the baud rate of the communication interface.

[0121] S230: If the first remainder is smaller than the first preset value, determine the first quotient value as the baud rate of the communication interface.

[0122] In this step, the first count value is divided by the first quantity (i.e., the number of detection data in the baud rate detection frame) to obtain a first quotient and a first remainder. If the first count value can completely divide the first quantity, the first remainder is 0. The first remainder is compared with a first preset value. If the first remainder is greater than or equal to the first preset value, the first quotient is added to a second preset value to obtain the baud rate of the communication interface. If the first remainder is less than the first preset value, the first quotient is determined as the baud rate of the communication interface. In an embodiment of the present invention, the first preset value is set to 4, and the second preset value is set to 1.

[0123] For example, the first count value is 109 (that is, the number of system clocks required to receive the baud rate detection frame, which is actually the number of system clocks required to receive the detection data in the baud rate detection frame), and the first number is 8. The first count value 109 is divided by the first number 8 to obtain a first quotient value 13 and a first remainder 5. Obviously, the first remainder 5 is greater than the first preset value 4. The first quotient value 13 is added to the second preset value 1 to obtain the baud rate of the communication interface as 14.

[0124] It is understandable that when the baud rate of the communication interface of the control device is represented by the number of system clocks, it can only be expressed as an integer. In the traditional method for calculating the baud rate of the communication interface, the first count value 109 is converted to a binary number, which is 01101101. The binary number 01101101 is shifted right by 3 bits (equivalent to dividing by the first number 8) to obtain the binary number 00001101. The binary number 00001101 is converted to decimal as 13, which means the baud rate of the communication interface is 13. However, the actual baud rate of the communication interface is 109 / 8 = 13.625. Therefore, the error between the calculated baud rate of the communication interface 13 and the actual baud rate of the communication interface 13.625 is 0.625.

[0125] Using the method provided in the above-mentioned embodiment of the present invention, the baud rate of the communication interface is calculated to be 14, and the error between the baud rate 14 of the communication interface and the actual baud rate 13.625 of the communication interface is 0.375. Compared with 0.625, the error is reduced. Therefore, using the method provided in the embodiment of the present invention, the baud rate detection accuracy can be improved, the error of baud rate detection can be reduced, and the occurrence of communication errors or failures due to low baud rate detection accuracy can be reduced or avoided, thereby reducing or avoiding unknown safety risks, ensuring the smooth communication and data transmission between the control device and the host computer, and improving the user experience.

[0126] To sum up, the baud rate detection method provided in an embodiment of the present invention is applied to a control device, the control device is communicatively connected to a host computer through a communication interface, the host computer is used to send a baud rate detection frame to the control device, and the control device includes a first counter. The method includes: obtaining a first count value of the first counter, the first count value representing a target period for the control device to receive the baud rate detection frame, the control device uses the number of system clocks to represent the target period, and obtains the baud rate of the communication interface based on the first count value.

[0127] The embodiment of the present invention obtains the target period of the control device receiving the baud rate detection frame by using the first counter to count, detects the baud rate of the communication interface, improves the baud rate detection accuracy, reduces the baud rate detection error, reduces or avoids the occurrence of communication errors or failures due to low baud rate detection accuracy, reduces or avoids unknown security risks, ensures the smooth transmission of communication data between the control device and the host computer, and improves the user experience.

[0128] As another aspect of an embodiment of the present invention, an embodiment of the present invention further provides a corresponding baud rate detection device. The baud rate detection device can be a software module, which includes a plurality of instructions stored in a memory. A processor can access the memory and call the instructions for execution to complete the baud rate detection method described in each of the above embodiments.

[0129] In some possible implementations, the baud rate detection device can also be constructed by hardware devices. For example, the baud rate detection device can be constructed by one or more chips, and the chips can work in coordination with each other to implement the baud rate detection methods described in the above embodiments. In some embodiments, the baud rate detection device can also be constructed by various logic devices, such as: a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a single-chip microcomputer, a field-programmable gate array (FPGA), an ARM (Acorn RISC Machine) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or any combination of these devices or components.

[0130] See also Figure 8 , Figure 8 The following schematically illustrates a structural diagram of a baud rate detection device 700 provided in some embodiments of the present invention. It is easy to understand that the baud rate detection device 700 can be configured in a control device, the control device is communicatively connected to a host computer via a communication interface, the host computer is configured to send a baud rate detection frame to the control device, and the control device includes a first counter.

[0131] Specifically, if Figure 8 As shown, the baud rate detection device 700 includes a first acquisition module 710 and a second acquisition module 720. The first acquisition module 210 is configured to obtain a first count value of a first counter, wherein the first count value represents a target period for the control device to receive a baud rate detection frame, and the control device uses the number of system clocks to represent the target period. The second acquisition module 220 is configured to obtain the baud rate of the communication interface based on the first count value.

[0132] In some embodiments, the baud rate detection frame includes multiple bits of detection data, and the control device also includes a second counter, which is used to count the number of detection data received by the control device. The first acquisition module 210 is specifically used to: in response to receiving the first bit of detection data, control the first counter and the second counter to start counting, and increase a count value by the second counter each time it is detected that the control device has completed receiving a bit of detection data. Each time a rising edge of the system clock of the control device is detected, the first counter increases a count value, and the first bit of detection data is the first bit of detection data in the baud rate detection frame. The second count value of the second counter is obtained. If the second count value is the same as the first number of detection data in the baud rate detection frame, the second counter is controlled to stop counting. In response to receiving the last bit of detection data and the second count value is the same as the first number, the first counter is controlled to stop counting and the first count value of the first counter is obtained. The last bit of detection data is the last bit of detection data in the baud rate detection frame.

[0133] In some embodiments, the first acquisition module 210 is further specifically configured to: acquire the level of the communication interface, and based on the level of the communication interface, respond to determine that the control device has received the first bit of detection data.

[0134] In some embodiments, the baud rate detection frame also includes a start bit, and the first acquisition module 210 is further specifically used to: if the start bit is a low level and the level of the communication interface changes from a low level to a high level, it is determined that the control device has received the first bit of detection data; or, if the start bit is a high level and the level of the communication interface changes from a high level to a low level, it is determined that the control device has received the first bit of detection data.

[0135] In some embodiments, the baud rate detection frame further includes a stop bit, and the first acquisition module 210 is further specifically configured to: if it is detected that the communication interface receives the stop bit, respond with a determination that the last bit detection data has been received.

[0136] See also Figure 9 In some embodiments, the baud rate detection device 700 further includes a determination module 730. In response to receiving the first bit detection data, before controlling the first counter and the second counter to start counting, the determination module 730 is used to determine whether the bit width of the first counter meets a preset condition.

[0137] In some embodiments, the determination module 730 is specifically used to: obtain the minimum baud rate of the communication interface, obtain the first frequency of the system clock, determine the minimum bit width of the first counter based on the first frequency and the minimum baud rate, obtain the bit width of the first counter, and if the bit width of the first counter is greater than or equal to the minimum bit width, determine that the bit width of the first counter meets the preset conditions.

[0138] In some embodiments, the second acquisition module 720 is specifically used to: divide the first count value by the first quantity to obtain a first quotient and a first remainder; if the first remainder is greater than or equal to the first preset value, add the first quotient to the second preset value to obtain the baud rate of the communication interface; if the first remainder is less than the first preset value, determine that the first quotient is the baud rate of the communication interface.

[0139] It should be noted that, for ease of description and brevity, the baud rate detection device 700 described above can implement the functional modules and beneficial effects corresponding to the baud rate detection method provided in the embodiment of the present invention. For technical details not fully described in the embodiment of the baud rate detection device 700, reference can be made to the baud rate detection method provided in the embodiment of the present invention. The specific operating process of the baud rate detection device 700 described above can also be referred to the specific execution process corresponding to the baud rate detection method provided in the aforementioned embodiment of the present invention, and will not be further described here.

[0140] An embodiment of the present invention provides a computer-readable storage medium, on which computer program instructions executable by a processor are stored. When the computer program instructions are called by the processor, the processor executes any baud rate detection method provided by the embodiment of the present invention, or executes the steps in any possible implementation of any baud rate detection method provided by the embodiment of the present invention.

[0141] In some embodiments, the storage medium may be a flash memory, a hard disk, an optical disk, a register, a magnetic surface storage, a removable disk, a CD-ROM, a random access memory (RAM), a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM or any other form of storage medium known in the art, or various devices including one or any combination of the above storage media.

[0142] In some embodiments, computer program instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0143] As an example, computer program instructions may, but do not necessarily, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, for example, in one or more scripts within a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (for example, files storing one or more modules, subroutines, or code portions).

[0144] As an example, computer program instructions can be deployed to be executed on a computing device (including devices such as smart terminals and servers), or on multiple computing devices located in one location, or on multiple computing devices distributed in multiple locations and interconnected by a communication network. It is easy to understand that all or part of the steps of the method described in the embodiments of the present invention can be directly implemented using electronic hardware or processor-executable computer program instructions, or a combination of the two.

[0145] Those skilled in the art will appreciate that the embodiments provided herein are merely illustrative, and the order in which the steps in the methods of the embodiments are written does not imply a strict order of execution and does not limit the implementation process. The order can be adjusted, merged, and deleted according to actual needs. The modules or submodules, units or subunits in the devices or systems of the embodiments can be merged, divided, and deleted according to actual needs. For example, the division of units is only a logical function division, and there can be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0146] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general hardware platform, and of course can also be implemented by hardware. Those skilled in the art can understand that all or part of the processes in the above embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0147] It should be noted that the above embodiments are intended to illustrate the technical concepts and features of the present invention, and their purpose is to enable people familiar with this technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the scope of protection of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiments can be implemented according to the technical solutions recorded in the embodiments of the present invention, or some of the technical features can be equivalently replaced. It is understandable that these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention, and should be regarded as equal changes and modifications based on the embodiments of the present invention, and should all fall within the scope of the claims of the present invention.

Claims

1. A baud rate detection method, applied to a control device, characterized in that: The control device is communicatively connected to a host computer via a communication interface, the host computer is used to send a baud rate detection frame to the control device, and the control device includes a first counter; The method comprises: Obtaining a first count value of the first counter, wherein the first count value represents a target period for the control device to receive the baud rate detection frame, and the control device uses the number of system clocks to represent the target period; Based on the first count value, a baud rate of the communication interface is obtained.

2. The method according to claim 1, characterized in that The baud rate detection frame includes multiple bits of detection data, and the control device further includes a second counter, which is used to count the number of detection data received by the control device; The obtaining the first count value of the first counter includes: In response to receiving the first bit detection data, controlling the first counter and the second counter to start counting, wherein the second counter increases a count value each time it is detected that the control device has completed receiving a bit of detection data, and the first counter increases a count value each time a rising edge of the system clock of the control device is detected, wherein the first bit detection data is the first bit detection data in the baud rate detection frame; obtaining a second count value of the second counter, and controlling the second counter to stop counting if the second count value is the same as the first amount of detection data in the baud rate detection frame; In response to receiving the last bit detection data and the second count value being the same as the first number, the first counter is controlled to stop counting and the first count value of the first counter is obtained. The last bit detection data is the last bit detection data in the baud rate detection frame.

3. The method according to claim 2, characterized in that The step of responding to receiving the first bit detection data comprises: The level of the communication interface is acquired, and based on the level of the communication interface, a response is made to determine that the control device has received the first bit detection data.

4. The method according to claim 3, characterized in that The baud rate detection frame further includes a start bit, and the step of determining, based on the level of the communication interface, that the control device has received the first bit of detection data comprises: If the start bit is at a low level and the level of the communication interface changes from a low level to a high level, it is determined that the control device has received the first bit detection data; or If the start bit is at a high level and the level of the communication interface changes from a high level to a low level, it is determined that the control device has received the first bit detection data.

5. The method according to claim 2, characterized in that The baud rate detection frame further includes a stop bit, and the step of detecting the last bit of the data in response to receiving the completion bit includes: If it is detected that the communication interface receives the stop bit, the end bit detection data is responded to determine that the reception is completed.

6. The method according to claim 2, characterized in that Before controlling the first counter and the second counter to start counting in response to receiving the first bit detection data, the method further includes: Determine whether the bit width of the first counter meets a preset condition.

7. The method according to claim 6, characterized in that The determining whether the bit width of the first counter meets a preset condition includes: Obtaining the minimum baud rate of the communication interface; Obtaining a first frequency of the system clock, and determining a minimum bit width of the first counter based on the first frequency and the minimum baud rate; The bit width of the first counter is obtained. If the bit width of the first counter is greater than or equal to the minimum bit width, it is determined that the bit width of the first counter meets a preset condition.

8. The method according to any one of claims 2 to 7, characterized in that: The obtaining, based on the first count value, the baud rate of the communication interface, comprises: Dividing the first count value by the first quantity to obtain a first quotient and a first remainder; If the first remainder is greater than or equal to a first preset value, adding the first quotient to a second preset value to obtain the baud rate of the communication interface; If the first remainder is smaller than the first preset value, the first quotient value is determined to be the baud rate of the communication interface.

9. A control device, characterized in that: include: a processor, a memory communicatively connected to the processor, a first counter, and a second counter, wherein the first counter is used to count a target period of the baud rate detection frame received by the control device, and the second counter is used to count the amount of detection data received by the control device; The memory stores computer program instructions executable by the processor, and when the computer program instructions are called by the processor, the processor executes the baud rate detection method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer program instructions executable by a processor. When the computer program instructions are called by the processor, the processor executes the baud rate detection method according to any one of claims 1 to 8.

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