A method of manufacturing a semiconductor chip

Abstract

The application discloses a kind of manufacturing methods of semiconductor chip, it is related to chip manufacturing field, including, selecting wafer to deposit, deposition data is collected in the process of wafer deposition, and input pre-constructed thin film deposition optimization model, obtain the wafer of double-layer structure, after coating the wafer of double-layer structure, definition guide template is carried out surface chemical modification and PS cylinder is embedded in the wafer of double-layer structure, obtain the wafer with PS cylinder pattern, form hard mask on the wafer with PS cylinder pattern by reactive ion etching, while with hard mask as foundation, atomic precision etching is carried out, in the process of atomic precision etching, optical emission spectrum and LSTM are used for monitoring and dynamic adjustment, form the wafer with FinFET fin.The present application analyzes deposition data in real time by thin film deposition optimization model and outputs adjustment instruction, provides uniform hard mask and etching stop layer for subsequent.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip manufacturing, and in particular to a manufacturing method of a semiconductor chip. BACKGROUND

[0002] Semiconductor chip manufacturing technology has made significant progress with the increasing demand for high performance, low power consumption and high integration, especially at the 5-nanometer and below nodes. Early manufacturing relies on planar transistor architecture and optical lithography technology. The introduction of FinFET three-dimensional architecture significantly improves the gate control capability and leakage current suppression effect. Atomic layer deposition and plasma-enhanced chemical vapor deposition have become standard techniques for depositing silicon dioxide and silicon nitride films, enabling nanoscale thickness control. Extreme ultraviolet lithography technology has become the core means of defining sub-10-nanometer patterns, while polystyrene-poly(methyl methacrylate) block copolymer directed self-assembly technology makes up for the lack of resolution of traditional lithography. However, the increasing complexity of process integration and real-time control requirements pose a serious challenge to existing manufacturing technology.

[0003] Despite the significant progress of existing semiconductor manufacturing technology, there is still room for improvement in existing semiconductor manufacturing methods, such as the film deposition process of atomic layer deposition and plasma-enhanced chemical vapor deposition, which often results in film quality variation due to uneven thickness and parameter drift, especially on large-diameter wafers, and the lack of real-time optimization capability for detection affects yield and scalability; in addition, when atomic layer etching FinFET fins, the etching rate difference between the center and the edge of the wafer needs to be manually calibrated, which limits the size consistency and production efficiency. SUMMARY

[0004] In view of the above existing problems, the present application is proposed.

[0005] Therefore, the present application provides a manufacturing method of a semiconductor chip to solve the problems of lack of real-time optimization capability for detection and manual calibration of the etching rate difference between the center and the edge of the wafer.

[0006] To solve the above technical problems, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides a manufacturing method of a semiconductor chip, comprising,

[0008] selecting a wafer for deposition, collecting deposition data during wafer deposition, and inputting a pre-constructed thin film deposition optimization model to obtain a double-layer structure wafer;

[0009] defining a guide template after coating the double-layer structure wafer, then performing surface chemical modification and embedding PS cylinders into the double-layer structure wafer to obtain a wafer with a PS cylinder pattern;

[0010] A hard mask is formed on a wafer with a PS cylinder pattern through reactive ion etching. Atomic-level precision etching is performed based on the hard mask. Optical emission spectroscopy and LSTM are used to monitor and dynamically adjust the atomic-level precision etching process to form a wafer with FinFET fins.

[0011] The wafer of the FinFET fin is made to generate an ultra-shallow PN junction by low-temperature plasma doping method and selective laser annealing, and the gate pattern is defined for the FinFET wafer with the ultra-shallow PN junction, and the FinFET wafer with the gate structure is output;

[0012] The dual damascene process is used to deposit a FinFET wafer with a gate structure to obtain a packaged semiconductor chip.

[0013] As a preferred embodiment of the method for manufacturing the semiconductor chip of the present invention, the step of obtaining the double-layer wafer specifically includes the following steps:

[0014] Depositing a double-layer structure of silicon dioxide and silicon nitride on a high-purity single-crystal silicon wafer using atomic layer deposition and plasma-enhanced chemical vapor deposition, while simultaneously collecting deposition data;

[0015] The deposition data is input into a thin film deposition optimization model based on a deep neural network to optimize the process parameters, ultimately forming a wafer with a double-layer structure of silicon dioxide and silicon nitride on the surface.

[0016] As a preferred embodiment of the method for manufacturing the semiconductor chip of the present invention, the step of obtaining a wafer having a PS cylindrical pattern specifically comprises the following steps:

[0017] On a wafer having a double-layer structure of silicon dioxide and silicon nitride on its surface, a guide template pattern is defined by spin coating an extreme ultraviolet photoresist and using an extreme ultraviolet lithography machine;

[0018] Surface chemical modification was performed using plasma activation and polystyrene monolayer coating, and polystyrene cylindrical patterns were formed by self-assembly of polystyrene-polymethyl methacrylate block copolymers to obtain a wafer with a polystyrene cylindrical pattern on the surface.

[0019] As a preferred embodiment of the method for manufacturing the semiconductor chip of the present invention, the method of forming a hard mask on a wafer having a PS column pattern by reactive ion etching specifically comprises the following steps:

[0020] On a double-layer wafer with a polystyrene cylindrical pattern on its surface, a reactive ion etching device is used with a mixture of carbon tetrafluoride and oxygen gas to transfer the polystyrene cylindrical pattern to the double layer of silicon dioxide and silicon nitride, forming a hard mask pattern composed of silicon dioxide and silicon nitride.

[0021] As a preferred embodiment of the method for manufacturing a semiconductor chip according to the present invention, the method includes the following steps: performing atomic-level precision etching based on a hard mask, and using optical emission spectroscopy and LSTM to monitor and dynamically adjust the atomic-level precision etching process to form a wafer with FinFET fins.

[0022] On a wafer with silicon dioxide and silicon nitride hard mask patterns on the surface, an atomic layer etching device is used to etch the silicon substrate through a self-limiting reaction cycle of chlorine and hydrogen to form FinFET fins;

[0023] The chlorine and hydrogen spectral intensities are monitored through optical emission spectroscopy, and a pre-trained LSTM model is used to analyze the spectral data and dynamically adjust the RF power and gas flow to form a wafer with FinFET fins on the surface.

[0024] As a preferred embodiment of the method for manufacturing the semiconductor chip of the present invention, the method of generating an ultra-shallow PN junction on the wafer of the FinFET fin by low-temperature plasma doping and selective laser annealing specifically comprises the following steps:

[0025] On the wafer with FinFET fins on the surface, a silicon dioxide protective layer is deposited using atomic layer deposition and pre-cleaned, and a mixed gas of diborane and argon is injected with boron ions using a low-temperature plasma doping device to form a doping layer;

[0026] A krypton fluoride excimer laser is used to illuminate the doped layer through a photomask to activate boron atoms into substitutional sites in the silicon lattice, forming an ultra-shallow PN junction.

[0027] As a preferred embodiment of the method for manufacturing the semiconductor chip of the present invention, the method of defining a gate pattern for a FinFET wafer having an ultra-shallow PN junction and outputting a FinFET wafer having a gate structure specifically includes the following steps:

[0028] Depositing hafnium dioxide as a high-k gate dielectric by atomic layer deposition and titanium nitride as a metal gate using physical vapor deposition;

[0029] The gate pattern is defined using an argon fluorine lithography machine and reactive ion etching equipment, ultimately forming a FinFET wafer with a high-k gate dielectric and metal gate structure on the surface.

[0030] As a preferred embodiment of the method for manufacturing the semiconductor chip of the present invention, the step of obtaining the packaged semiconductor chip specifically comprises the following steps:

[0031] Based on the wafer with FinFET fins, ultra-shallow PN junctions, high-k gate dielectrics and metal gate structures on the surface, a dual damascene process is used to deposit silicon dioxide interlayer dielectrics, define interconnect trenches and fill them with copper to form multi-layer low-resistance copper interconnects.

[0032] The chip is connected to the substrate using through-silicon vias (TSVs) through wafer dicing and then encapsulated with epoxy resin to obtain a packaged chip.

[0033] In a second aspect, the present invention provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: when the computer program is executed by the processor, any step of the method for manufacturing a semiconductor chip as described in the first aspect of the present invention is implemented.

[0034] In a third aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, any step of the method for manufacturing a semiconductor chip as described in the first aspect of the present invention is implemented.

[0035] The beneficial effects of the present invention are as follows: by using a thin film deposition optimization model to analyze deposition data in real time and output adjustment instructions, nanometer-level thickness control of a double-layer thin film of silicon dioxide and silicon nitride is achieved, providing a uniform and stable hard mask and etch stop layer for subsequent photolithography and etching, significantly improving the film consistency and manufacturing yield of the wafer, enhancing process scalability, and reducing device performance fluctuations caused by thickness variation; and by combining an LSTM model with OES for real-time monitoring and dynamic adjustment of the balancing center and edge etching rates, production efficiency is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 The present invention is a flow chart of a method for manufacturing a semiconductor chip.

[0038] Figure 2 Schematic diagram of the self-assembly pattern formation process.

[0039] Figure 3 This is the atomic layer etching control flow chart.

[0040] Figure 4 This is the chip packaging flow chart. DETAILED DESCRIPTION

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0043] Secondly, the term "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive of other embodiments.

[0044] Reference Figures 1 to 4 , is an embodiment of the present invention, which provides a method for manufacturing a semiconductor chip, comprising the following steps:

[0045] S1. Select a wafer for deposition, collect deposition data during the wafer deposition process, and input it into a pre-built thin film deposition optimization model to obtain a double-layer structure wafer.

[0046] The specific steps include:

[0047] S1.1. Select high-purity single-crystal silicon wafers. In an ISO Class 5 cleanroom, clean the single-crystal silicon wafers using SC-1 solution (ammonia: hydrogen peroxide: water = 1:1:5, 50°C, 10 minutes) and SC-2 solution (hydrochloric acid: hydrogen peroxide: water = 1:1:6, 60°C, 10 minutes) to remove surface particles, organic matter, and metal ions, resulting in a clean wafer surface. Chemical mechanical polishing (CMP) is used to maintain a surface roughness below 0.3 nm and a surface flatness error below 0.5 nm, providing a flat substrate for subsequent deposition processes. After wafer selection and pretreatment, a clean and flat single-crystal silicon wafer is obtained, serving as the starting substrate for the deposition process.

[0048] S1.2. Thin film deposition on a clean and flat single crystal silicon wafer surface is divided into two stages.

[0049] The first stage: Atomic layer deposition (ALD) equipment is used to deposit a 10nm layer of silicon dioxide as a hard mask layer. The precursors are tetraethoxysilane and ozone. ALD achieves precise deposition through a cyclic reaction. For example, 0.1nm of silicon dioxide is deposited per cycle. After 100 cycles, a 10nm thick silicon dioxide layer is formed with a thickness uniformity error of less than 1%.

[0050] In the second stage, a 5nm layer of silicon nitride is deposited as an etch stop layer using plasma-enhanced chemical vapor deposition (PECVD) equipment, using silane and ammonia as precursors. The deposition process is performed in a cleanroom environment to ensure film quality and consistency.

[0051] It is further explained that atomic layer deposition and plasma enhanced chemical vapor deposition techniques are used to deposit silicon dioxide and silicon nitride respectively, achieving precise control of nanometer-level thickness, and this high-precision deposition provides a stable hard mask and etch stop layer for subsequent lithography and etching processes.

[0052] S1.3. During the atomic layer deposition and plasma enhanced chemical vapor deposition processes, real-time collection of deposition-related deposition data is performed.

[0053] The steps are as follows: Deploy temperature sensors, pressure sensors, and film thickness sensors to collect deposition data. The temperature sensor records the deposition chamber temperature, the pressure sensor monitors the chamber pressure, and the film thickness sensor measures the real-time thickness of silicon dioxide and silicon nitride. The collected deposition data is processed by an edge computing unit to generate time series data including temperature, pressure, and film thickness.

[0054] S1.4. First, build and train a thin film deposition optimization model. The thin film deposition optimization model is based on a deep neural network (DNN) architecture. The thin film deposition optimization model is built using historical deposition data and supervised learning methods to analyze temperature, pressure, and film thickness data to predict and optimize thin film deposition parameters. The training process is as follows:

[0055] 1. Data Collection: A large amount of deposition data was collected from historical atomic layer deposition and plasma-enhanced chemical vapor deposition (PECVD) experiments. This deposition data includes temperature, pressure, film thickness, tetraethoxysilane flow rate, silane flow rate, ammonia flow rate, RF power, and corresponding silicon dioxide and silicon nitride layer thickness deviations. This deposition data covers a wide range of process conditions, ensuring that the pre-trained thin film deposition optimization model is adaptable to different deposition scenarios.

[0056] 2. Clean and format the collected deposition data, remove outliers, and normalize the deposition data to a uniform range (0-1). The deposition data is divided into input features and output labels. Input features include temperature, pressure, film thickness, gas flow rate, etc.; output labels include adjusted process parameters, such as tetraethoxysilane flow rate ±0.1sccm, RF power ±5W, and final thickness deviation. The preprocessed deposition data is organized into a preprocessed dataset and divided into training, validation, and test sets.

[0057] 3. Thin Film Deposition Optimization Model Architecture: The underlying deep neural network utilizes a multi-layer, fully connected neural network architecture consisting of an input layer, hidden layers, and an output layer. The input layer receives the dataset; the hidden layer consists of three layers of neurons, each with 100 neurons, using the ReLU activation function; and the output layer generates adjustment commands, such as changes in tetraethoxysilane flow rate and RF power.

[0058] 4. Pre-train the thin film deposition optimization model using supervised learning. The training objective is to minimize the mean squared error between the predicted and actual parameters. For example, the loss function calculates the error between the predicted tetraethoxysilane flow adjustment and the actual adjustment. The Adam optimizer is used to update the thin film deposition optimization model weights. The validation set is used to monitor the training process and prevent overfitting. Training is terminated when the validation set error falls below 0.01. Finally, the thin film deposition optimization model achieves a prediction error of less than 1% on the test set. This indicates that the thin film deposition optimization model training is complete and is stored in the edge computing unit for real-time deposition control.

[0059] S1.4.1. The trained thin film deposition optimization model analyzes deposition data and optimizes parameters in real time during atomic layer deposition and plasma-enhanced chemical vapor deposition. The overall process is as follows:

[0060] (1) The edge computing unit receives the collected deposition data and inputs the collected deposition data into the trained thin film deposition optimization model. The thin film deposition optimization model forward propagates the input deposition data and analyzes the impact of the current process parameters on the film thickness and uniformity. For example, in atomic layer deposition, the thin film deposition optimization model detects that the film thickness growth rate deviates from the target and calculates the tetraethoxysilane flow adjustment amount; in plasma-enhanced chemical vapor deposition, the thin film deposition optimization model predicts the RF power adjustment amount based on the pressure fluctuation. The predicted RF power adjustment amount is used to adjust the RF power parameters of the plasma-enhanced chemical vapor deposition equipment in real time to optimize the deposition rate and film uniformity of the silicon nitride film.

[0061] (2) The thin film deposition optimization model outputs adjustment instructions and feeds them back to the deposition equipment in real time. The deposition equipment adjusts the process parameters in real time according to the adjustment instructions, and finally obtains a wafer with a silicon dioxide layer and a silicon nitride layer deposited on the surface.

[0062] For example, in atomic layer deposition, the thin film deposition optimization model adjusts the tetraethoxysilane flow rate by ±0.1sccm to ensure 0.1nm of silicon dioxide is deposited per cycle. In plasma-enhanced chemical vapor deposition, the thin film deposition optimization model optimizes the silicon nitride deposition rate and film quality by adjusting the RF power by ±5W.

[0063] It is further explained that the pre-trained thin film deposition optimization model is based on a deep neural network (DNN) architecture. Through historical deposition data and supervised learning training, it can analyze temperature, pressure and film thickness data, predict and optimize deposition parameters, and intelligent optimization significantly improves deposition uniformity.

[0064] S2. After coating the double-layer wafer, a guide template is defined, followed by surface chemical modification and embedding of PS cylinders into the double-layer wafer to obtain a wafer with a PS cylinder pattern.

[0065] The specific steps include:

[0066] S2.1. Using a wafer with deposited silicon dioxide and silicon nitride layers as the starting substrate, a chemically amplified EUV photoresist is applied to the silicon dioxide and silicon nitride double layer using a spin coater to form a uniform layer. The layer is then baked on a hot plate to remove the solvent from the photoresist layer, enhance its stability, and provide a coating suitable for subsequent EUV lithography exposure. After coating, a double-layer wafer covered with EUV photoresist is obtained, which serves as the substrate for the guide template definition.

[0067] S2.2. On a double-layer wafer covered with extreme ultraviolet (EUV) photoresist, an EUV lithography machine is used to perform exposure and define a guide template pattern. Specifically: (1) Each region is exposed using an EUV lithography machine to form a guide template pattern. After exposure, tetramethylammonium hydroxide is used for development to form a photoresist guide template. (2) Oxygen plasma cleaning is used to remove residual photoresist, ensure a clear pattern, and complete the definition of the guide template. After the guide template definition is completed, a double-layer wafer with a photoresist guide template on the surface is obtained, providing a structural foundation for surface chemical modification.

[0068] It is further explained that the guide template pattern is defined on the double-layer structure wafer through extreme ultraviolet lithography technology, achieving nanometer-level pattern accuracy, providing precise structural guidance for the subsequent block copolymer self-assembly, ensuring the formation of the contact hole pattern, and meeting the manufacturing size requirements.

[0069] S2.3. Surface chemical modification is performed on a double-layer structure wafer with a photoresist guide template to enhance the directionality of subsequent self-assembly. Specifically: (1) An oxygen / argon gas mixture is introduced into the plasma chamber, and radio frequency activation is used to activate the surface of the photoresist guide template to form hydroxyl groups, thereby increasing the surface hydrophilicity. (2) A polystyrene (PS) monolayer is coated using a spin coater to form a chemically modified layer. The hydrophobicity of polystyrene is combined with the hydrophilicity of hydroxyl groups to form a hydrophilic hydroxyl surface through plasma activation and spin-coating of a polystyrene monolayer to construct a hydrophilic-hydrophobic contrasting chemically modified layer, providing chemical guidance for the self-assembly of block copolymers. After the surface chemical modification is completed, a guide template wafer with a chemically modified layer is obtained, which prepares the chemical and structural conditions for the embedding of PS cylinders.

[0070] S2.4. A polystyrene-polymethyl methacrylate block copolymer is coated on a guide template wafer with a chemically modified layer to form a uniform polymer layer. Annealing under a nitrogen atmosphere induces phase separation between polystyrene and polymethyl methacrylate, forming a polystyrene (PS) cylindrical structure embedded in the polymethyl methacrylate matrix. After soaking in acetic acid, the polymethyl methacrylate is selectively removed. The high solubility of acetic acid in polymethyl methacrylate and the low solubility of acetic acid in polymethyl methacrylate dissolve the polymethyl methacrylate matrix, retaining the polystyrene cylinders and forming a contact hole pattern. Simultaneously, the thin film deposition optimization model monitors the self-assembled structure in real time using an optical microscope, adjusting the annealing temperature and acetic acid soaking time to ensure that the dimensional error and defect density of the polystyrene cylinders are less than process requirements. After the block copolymer self-assembly is complete, a wafer with a polystyrene (PS) cylinder pattern on its surface is obtained.

[0071] It is further explained that the combination of extreme ultraviolet lithography and polystyrene-polymethyl methacrylate block copolymer self-assembly technology has broken through the resolution limitation of traditional lithography, reduced process costs, and improved manufacturing efficiency and economy.

[0072] S3. A hard mask is formed on the wafer with the PS cylindrical pattern by reactive ion etching. At the same time, atomic-level precision etching is performed based on the hard mask. During the atomic-level precision etching process, optical emission spectroscopy and LSTM are used for monitoring and dynamic adjustment to form a wafer with FinFET fins.

[0073] The specific steps include:

[0074] S3.1. Using a wafer with a polystyrene (PS) cylinder pattern as the starting substrate, the wafer is placed in a plasma etching chamber and reactive ion etching (RIE) is used to transfer the PS cylinder pattern to the underlying silicon dioxide and silicon nitride bilayer. RIE uses a mixture of carbon tetrafluoride and oxygen. The PS cylinder pattern acts as a soft mask, protecting the underlying silicon dioxide and silicon nitride areas. The CF3 removes the unprotected silicon dioxide and silicon nitride, forming protrusions in the protected areas and grooves in the unprotected areas, creating a hard mask pattern corresponding to the PS cylinders. For example, CF3 provides fluorine groups to etch the silicon dioxide, while oxygen assists in removing PS residues. Subsequently, oxygen plasma cleaning is used to completely remove any remaining PS residues. X-ray photoelectron spectroscopy is used to detect any remaining PS residues. The patterned silicon dioxide and silicon nitride hard mask is then exposed, resulting in a wafer with a surface containing both silicon dioxide and silicon nitride hard masks, providing an etch-resistant template for atomically precise etching.

[0075] It is further explained that the polystyrene cylindrical pattern is precisely transferred to the silicon dioxide and silicon nitride double layer through reactive ion etching to form a highly corrosion-resistant hard mask, which provides a reliable template for atomic layer etching, avoids pattern distortion, and improves the dimensional consistency of the FinFET fin structure.

[0076] S3.2. FinFET fins are processed using an atomic layer etching device through a wafer with a silicon dioxide and silicon nitride hard mask on the surface. The atomic layer etching device is equipped with a chlorine and hydrogen gas inlet device and uses a self-limiting reaction cycle to achieve atomic-level precision etching. Each atomic layer etching cycle includes the following steps: (1) Chlorine-based etching: A mixture of chlorine and argon is introduced into the etching chamber of the atomic layer etching device to form a single atomic layer of silicon chloride reaction layer on the exposed silicon substrate surface. (2) Vacuuming: The chamber is evacuated to remove unreacted gases. (3) Hydrogen-based passivation: A mixture of hydrogen and argon is introduced to generate volatile silane and remove silicon chloride. (4) Vacuuming: The chamber is evacuated again to remove reaction byproducts. For example, 0.2nm of silicon is removed in each cycle, and 250 cycles are performed to form a 50nm high FinFET fin. The silicon dioxide and silicon nitride hard masks protect the unetched areas to ensure that the fin pattern is consistent with the polystyrene cylinder pattern. After atomic layer etching is completed, the silicon dioxide and silicon nitride hard masks are removed by soaking in a dilute hydrofluoric acid solution for 30 seconds to expose the FinFET fins on the silicon substrate.

[0077] S3.3.1. Build and train an LSTM model based on historical atomic layer etching data and supervised learning methods to analyze optical emission spectroscopy data, predict etch rate and uniformity, and optimize process parameters. This involves the following steps: data collection, data preprocessing, LSTM model architecture construction, and model training.

[0078] Specifically, data collection involves collecting extensive optical emission spectral data and process parameter data from historical atomic layer etching experiments. The collected data includes chlorine and hydrogen spectral intensities, chlorine gas flow rate, hydrogen gas flow rate, RF power, bias voltage, etch rate, etch rate difference between the wafer center and edge, and sidewall roughness. The collected data covers a wide range of process conditions, such as different gas ratios and pressures, ensuring that the LSTM model can adapt to diverse etching scenarios.

[0079] Data preprocessing involves cleaning and formatting the collected data, removing outliers, and normalizing the data to a range of 0-1. The data is divided into input features and output labels. Input features include time series of chlorine and hydrogen spectral intensities; output labels include adjusted process parameters, such as RF power change, gas flow change, etch rate difference, and sidewall roughness. The preprocessed dataset is divided into training, validation, and test sets.

[0080] The LSTM model architecture is specifically constructed as follows: The LSTM model utilizes a long short-term memory network architecture, suitable for processing time series data. The architecture consists of an input layer, an LSTM hidden layer, and a fully connected output layer. The input layer receives a time series of spectral intensities. The LSTM hidden layer consists of two layers of LSTM units, each with 50 units, using the tanh activation function. The fully connected output layer generates adjustment commands, such as changes in RF power and gas flow, and has two output nodes. The LSTM model is based on an existing deep learning framework.

[0081] The specific process of model training is as follows: using supervised learning methods, the training objective is set to minimize the mean squared error between the predicted and actual parameters. The Adam optimizer is used to update the LSTM model weights. A validation set is used to monitor the training process and prevent overfitting. For example, training is stopped when the validation set error falls below 0.01. Finally, the performance of the LSTM model is verified using a test set. The verification process involves inputting test data (such as a chlorine spectral intensity sequence). The LSTM model predicts the RF power and gas flow adjustments, ensuring that the etch rate difference is less than 1% and the sidewall roughness is less than 0.1 nm. Once verification is passed, the LSTM model training is completed and saved to the edge computing unit for real-time etching control.

[0082] S3.3.2. The trained LSTM model analyzes the optical emission spectrum data in real time during the atomic layer etching process, dynamically adjusts the process parameters, and ensures etching uniformity and fin accuracy. The specific process of the LSTM model execution is as follows: (1) During the atomic layer etching process, the optical emission spectrum is used to monitor the chlorine and hydrogen spectral intensities, and the concentration data of the reactants and by-products in the etching chamber are collected in real time to reflect the chemical reaction dynamics of the chlorine-based etching and hydrogen-based passivation steps. These collected data are then transmitted to the edge computing unit to generate a spectral intensity time series. (2) The edge computing unit receives the optical emission spectrum data and inputs the spectral intensity time series into the LSTM model. The LSTM model processes the input spectral intensity time series through forward propagation, uses the LSTM unit to capture the timing pattern in the sequence, and analyzes the reaction dynamics of the chlorine-based etching and hydrogen-based passivation steps. The LSTM model predicts the current etching rate based on the mapping relationship between spectral intensity and etching rate; for wafer uniformity, the LSTM model compares the spectral intensity difference between the center and edge of the wafer, infers that the edge etching rate is higher than the center, and thus predicts the uniformity deviation. For example, the LSTM model detects that the chlorine spectrum intensity at the edge of the wafer is 5% higher than that at the center, indicating that the etching rate at the edge is higher than that at the center. The LSTM model calculates the adjustment amount based on the intensity difference and outputs adjustment instructions for optimizing the atomic layer etching process, including changes in RF power and gas flow to balance the etching rate. The intensity difference comes from the chlorine and hydrogen spectrum intensity data collected in real time by the optical emission spectroscopy during the atomic layer etching process, specifically the difference in spectral intensity between the center and edge of the wafer. (3) The LSTM model feeds the output adjustment instructions back to the atomic layer etching equipment in real time, and according to the real-time control of the LSTM model, the atomic layer etching is completed until a wafer with FinFET fins is obtained.

[0083] Furthermore, the LSTM model combined with optical emission spectroscopy monitors the chlorine and hydrogen spectral intensities in real time, dynamically adjusting the RF power and gas flow rate to ensure that the etch rate difference between the center and edge of the wafer is less than 1%, and the sidewall roughness is less than 0.1nm. This high uniformity and low roughness significantly improve the electrical performance of the FinFET.

[0084] S4. An ultra-shallow PN junction is generated on the wafer of the FinFET fin by a low-temperature plasma doping method and selective laser annealing, and a gate pattern is defined for the FinFET wafer with the ultra-shallow PN junction, and a FinFET wafer with a gate structure is output.

[0085] The specific steps include:

[0086] S4.1. Place the wafer with FinFET fins in a high-density plasma chamber equipped with a pulse power supply and a doping gas device. The first step is to use atomic layer deposition equipment to deposit a silicon dioxide protective layer to prevent plasma damage to the fin surface. Atomic layer deposition uses tetraethoxysilane and ozone as precursors to form a 2nm thick silicon dioxide layer. Ensure the integrity of the fin structure. The second step is to pre-clean the surface of the FinFET fin and pass a mixed gas of argon and hydrogen for 30 seconds to remove oxides and impurities on the surface of the fin, provide a clean doping surface, and enhance the doping efficiency. The third step is to pass a mixed gas of diborane and argon into the high-density plasma chamber after completing the deposition and pre-cleaning of the silicon dioxide protective layer, and set the pressure, pulsed RF power, bias, and pulse duration. The temperature of the high-density plasma chamber is controlled at 180-200°C by a water-cooled base to ensure a low-temperature environment. Low temperature conditions prevent boron atoms from diffusing deep into the fins, keeping the doping layer shallow. The pulsed power supply in the high-density plasma chamber excites the plasma through pulsed radio frequency, decomposing diborane to produce boron ions. Argon is used as a carrier gas to stabilize the plasma discharge. The pulsed power supply in the high-density plasma chamber applies a bias voltage to drive the boron ions into the surface of the FinFET fins. During the injection process, attention must be paid to the pulse execution time to control the injection depth and ultimately form the doped layer. The fourth step is to use secondary ion mass spectrometry to in-situ monitor the boron concentration on the surface of the FinFET fins, analyze the boron atomic distribution in real time, and confirm that the doping layer uniformity meets the requirements before completing the low-temperature plasma doping, forming an ultra-shallow doped layer on the surface of the FinFET fins.

[0087] It is further explained that the low-temperature plasma doping method forms an ultra-shallow doping layer on the surface of the FinFET fin through pulse control and precise parameter setting of the high-density plasma cavity, providing the electrical basis of low resistivity and high carrier density for FinFET.

[0088] S4.2. After completing the low-temperature plasma doping, a 248nm krypton fluoride excimer laser is used for selective laser annealing, which specifically includes: the first step, setting the krypton fluoride excimer laser pulse width and energy density parameters, and preparing to irradiate the doped area through a photomask. The second step is to irradiate the doped area of ​​the FinFET fin with a krypton fluoride excimer laser through a photomask, with each area receiving 10 pulses to activate boron atoms to enter the substitutional position of the silicon lattice, forming an ultra-shallow PN junction. Selective laser annealing ensures that the temperature of the non-irradiated area is lower than 200°C to prevent thermal diffusion from damaging the doped layer. The third step is to monitor the surface temperature of the FinFET wafer in real time with an infrared thermometer to ensure the annealing temperature of the irradiated area and the low-temperature control accuracy of the non-irradiated area. The fourth step is to soak the FinFET fin wafer in a dilute hydrofluoric acid solution to remove the 2nm silicon dioxide protective layer and expose the surface of the doped fin. The fourth step is to analyze the doping layer of the FinFET fin through secondary ion mass spectrometry. Specifically, the surface of the FinFET fin is scanned with secondary ion mass spectrometry to collect the change of boron signal intensity with depth. The signal intensity is converted into boron concentration through calibration standard samples, and a depth distribution curve is drawn. The depth distribution curve is analyzed to verify the ultra-shallow PN junction depth, boron concentration peak and concentration gradient. The resistivity of the doped layer is measured by combining the four-probe method to verify the depth and resistivity of the ultra-shallow PN junction, confirm that the high conductivity and electrical properties of the doped layer meet the electrical requirements of the FinFET, complete selective laser annealing, and generate an ultra-shallow PN junction in the FinFET fin.

[0089] It is further explained that selective laser annealing activates boron atoms through a 248nm krypton fluoride excimer laser to form an ultra-shallow PN junction with excellent electrical properties, significantly improving the switching performance and current driving capability of the FinFET.

[0090] S4.3. Based on the FinFET wafer with ultra-shallow PN junction, high-k gate dielectric is deposited by atomic layer deposition, metal gate is deposited by physical vapor deposition, and gate pattern is defined by photolithography and reactive ion etching to form a FinFET wafer with high-k and metal gate structure. There are three processes in total: depositing high-k gate dielectric, depositing metal gate and defining gate pattern.

[0091] S4.3.1. The specific process for depositing the high-k gate dielectric is as follows: Atomic layer deposition uses hafnium tetrachloride and water as precursors. The deposition temperature, deposition thickness per cycle, and number of cycles are set to form a hafnium dioxide layer, enhancing gate control capability. The deposition temperature is set to ensure compatibility with the thermal budget of the ultra-shallow PN junction and to prevent boron atomic diffusion. After hafnium dioxide deposition, the surface of the FinFET wafer is uniformly covered with high-k gate dielectric, providing a flat substrate for metal gate deposition.

[0092] Further, the atomic layer deposition of hafnium dioxide as high-k gate dielectric significantly enhances the gate control capability of the FinFET wafer. Hafnium dioxide has a high dielectric constant, which can provide higher capacitance density, and thus improves the switching speed and current driving capability of the FinFET wafer.

[0093] S4.3.2, the specific process of depositing a metal gate is: physical vapor deposition using a high-purity titanium target, nitrogen and argon mixed gas is introduced, the radio frequency power, pressure and deposition time are set, and a titanium nitride layer is formed. For the formation of a 10 nm thick titanium nitride layer, the low work function characteristics are achieved through precise thickness control, thereby achieving the effect of optimizing the threshold voltage of the FinFET. Simply put, titanium nitride is easier to control current, like a sensitive switch button. The threshold voltage of the FinFET is derived from the low work function of the metal gate formed by physical vapor deposition, which is jointly determined by the high-k dielectric and the doped layer of the FinFET fin, and controls the device conduction by adjusting the channel potential. Based on the precise control of the thickness of the titanium nitride, the stoichiometric ratio and the electrical requirements of the FinFET, the low work function reduces the threshold voltage of the FinFET to match the low power consumption and high performance targets. The mixture of nitrogen and argon ensures the stability of the stoichiometric ratio of titanium nitride, and the setting of the radio frequency power and the pressure ensures that the deposition uniformity error is less than 1%. After the titanium nitride deposition is completed, the high-k and metal gate stack is formed on the surface of the FinFET wafer, providing a structural basis for gate pattern definition.

[0094] Further, the physical vapor deposition of titanium nitride as a metal gate provides a low work function, optimizes the threshold voltage of the FinFET, and also optimizes the low power consumption performance of the FinFET wafer, reducing the leakage current.

[0095] S4.3.3, the process of defining the gate pattern is: first, use a 193 nm argon-fluorine photolithography machine to expose photoresist and form a gate pattern; second, use a carbon tetrafluoride and oxygen mixed gas in a reactive ion etching device to transfer the photoresist pattern to the titanium nitride and hafnium dioxide layer, forming a high-k and metal gate structure. For example, carbon tetrafluoride provides fluorine groups to etch titanium nitride, and oxygen assists in removing photoresist residues, and the etching time ensures that the pattern edge roughness is less than 0.1 nm. After the gate pattern definition is completed, a FinFET wafer with a gate structure is obtained.

[0096] Further, the formation of the high-k and metal gate structure significantly improves the overall performance of the FinFET wafer. The hafnium dioxide high-k gate dielectric enhances the gate capacitance, the titanium nitride low work function optimizes the threshold voltage, and the gate pattern ensures the size accuracy, which together realizes high switching speed, low power consumption and strong gate control capability, and also lays a solid foundation for subsequent interconnection and chip integration.

[0097] S5. Use the dual Damascene process to deposit the FinFET wafer with the gate structure to obtain a packaged semiconductor chip.

[0098] The specific steps include:

[0099] S5.1. Use the dual damascene process to deposit copper interconnects. The dual damascene process forms multi-layer copper interconnects on FinFET wafers with high-k and metal gate structures, including interlayer dielectric deposition, interconnect trench definition, copper filling, and planarization. The specific steps are: (1) Use plasma-enhanced chemical vapor deposition equipment to deposit silicon dioxide as an interlayer dielectric: The plasma-enhanced chemical vapor deposition equipment uses silane and oxygen as precursors to form a silicon dioxide layer. For example, the silicon dioxide layer provides a low dielectric constant and reduces the interconnect parasitic capacitance. (2) Use extreme ultraviolet lithography equipment and reactive ion etching equipment to define the interconnect trench: The extreme ultraviolet lithography equipment exposes the photoresist trench pattern, and reactive ion etching uses a mixture of carbon tetrafluoride and oxygen to etch the interconnect trench. For example, the interconnect trench width is controlled at 20±0.2nm, and the trench depth error is ±0.5nm to ensure high-precision patterns. (3) Use electrochemical deposition equipment to fill the interconnection groove with copper: the electrolyte used is copper sulfate, and the deposition time is 60 seconds to form copper interconnects, ensuring that there are no gaps in the interconnection grooves. Then, chemical mechanical polishing equipment is used to remove excess copper, and the above process is repeated to form multi-layer copper interconnects, providing a low resistance and high-density interconnection structure.

[0100] It is further explained that the dual Damascene process forms low-resistance, high-density multi-layer copper interconnects through precise interlayer dielectric deposition, interconnect trench definition and copper filling, enabling the chip to support high-speed signal transmission; and also improves electrical performance, making the chip's electrical consistency and reliability higher.

[0101] S5.2. After copper interconnect deposition is complete, the chip is packaged using a 2.5D packaging method. Specifically, a wafer saw cuts the FinFET wafer into individual chips. Subsequently, the 2.5D packaging equipment connects the chip to the substrate using through-silicon via (TSV) technology. The TSVs are 5μm in diameter and are filled with copper using electrochemical deposition to form high-density vertical interconnects. The packaging process uses epoxy resin as the packaging material, which cures at 150°C to form a robust package structure. For example, after curing, epoxy resin provides high mechanical strength, protecting the chip from external stress. After packaging, the chip and substrate form a reliable electrical and mechanical connection, suitable for high-frequency signal transmission.

[0102] This embodiment also provides a computer device suitable for the case of a semiconductor chip manufacturing method, comprising: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute computer-executable instructions to implement the semiconductor chip manufacturing method proposed in the above embodiment.

[0103] The computer device may be a terminal, comprising a processor, memory, a communication interface, a display, and an input device connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores an operating system and computer programs. The internal memory provides an environment for the operating system and computer programs stored in the non-volatile storage media. The communication interface of the computer device is used to communicate with external terminals via wired or wireless communication. Wireless communication may be achieved via Wi-Fi, a carrier network, NFC (near-field communication), or other technologies. The display of the computer device may be a liquid crystal display or an electronic ink display. The input device may be a touchscreen overlay on the display, buttons, a trackball, or a touchpad on the computer device housing, or an external keyboard, touchpad, or mouse.

[0104] This embodiment also provides a storage medium having a computer program stored thereon, which, when executed by a processor, implements the method for manufacturing a semiconductor chip as proposed in the above embodiment; the storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0105] In summary, the present invention achieves nanoscale thickness control of a double-layer thin film of silicon dioxide and silicon nitride by: analyzing deposition data in real time through a thin film deposition optimization model and outputting adjustment instructions, providing a uniform and stable hard mask and etch stop layer for subsequent photolithography and etching, significantly improving the film consistency and manufacturing yield of the wafer, enhancing process scalability, and reducing device performance fluctuations caused by thickness variation; and improving production efficiency by combining an LSTM model with OES for real-time monitoring and dynamic adjustment of the center and edge etching rates.

[0106] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor chip, characterized in that: include, Select a wafer for deposition, collect deposition data during the wafer deposition process, and input it into a pre-built thin film deposition optimization model to obtain a double-layer structure wafer; After coating the double-layer wafer, a guide template is defined, followed by surface chemical modification and embedding of PS cylinders into the double-layer wafer to obtain a wafer with a PS cylinder pattern. A hard mask is formed on a wafer with a PS cylinder pattern through reactive ion etching. Atomic-level precision etching is performed based on the hard mask. Optical emission spectroscopy and LSTM are used to monitor and dynamically adjust the atomic-level precision etching process to form a wafer with FinFET fins. The wafer of the FinFET fin is made to generate an ultra-shallow PN junction by low-temperature plasma doping method and selective laser annealing, and the gate pattern is defined for the FinFET wafer with the ultra-shallow PN junction, and the FinFET wafer with the gate structure is output; The dual damascene process is used to deposit a FinFET wafer with a gate structure to obtain a packaged semiconductor chip.

2. The method for manufacturing a semiconductor chip according to claim 1, wherein: The method of obtaining a double-layer wafer specifically includes the following steps: Depositing a double-layer structure of silicon dioxide and silicon nitride on a high-purity single-crystal silicon wafer using atomic layer deposition and plasma-enhanced chemical vapor deposition, while simultaneously collecting deposition data; The deposition data is input into a thin film deposition optimization model based on a deep neural network to optimize the process parameters, ultimately forming a wafer with a double-layer structure of silicon dioxide and silicon nitride on the surface.

3. The method for manufacturing a semiconductor chip according to claim 2, wherein: The method of obtaining a wafer having a PS cylindrical pattern specifically comprises the following steps: On a wafer having a double-layer structure of silicon dioxide and silicon nitride on its surface, a guide template pattern is defined by spin coating an extreme ultraviolet photoresist and using an extreme ultraviolet lithography machine; Surface chemical modification was performed using plasma activation and polystyrene monolayer coating, and polystyrene cylindrical patterns were formed by self-assembly of polystyrene-polymethyl methacrylate block copolymers to obtain a wafer with a polystyrene cylindrical pattern on the surface.

4. The method for manufacturing a semiconductor chip according to claim 3, wherein: The process of forming a hard mask on a wafer having a PS column pattern by reactive ion etching specifically includes the following steps: On a double-layer wafer with a polystyrene cylindrical pattern on its surface, a reactive ion etching device is used with a mixture of carbon tetrafluoride and oxygen gas to transfer the polystyrene cylindrical pattern to the double layer of silicon dioxide and silicon nitride, forming a hard mask pattern composed of silicon dioxide and silicon nitride.

5. The method for manufacturing a semiconductor chip according to claim 4, wherein: The process of performing atomic-level precision etching based on a hard mask, and using optical emission spectroscopy and LSTM to monitor and dynamically adjust the atomic-level precision etching process to form a wafer with FinFET fins, specifically includes the following steps: On a wafer with silicon dioxide and silicon nitride hard mask patterns on the surface, an atomic layer etching device is used to etch the silicon substrate through a self-limiting reaction cycle of chlorine and hydrogen to form FinFET fins; The chlorine and hydrogen spectral intensities are monitored through optical emission spectroscopy, and a pre-trained LSTM model is used to analyze the spectral data and dynamically adjust the RF power and gas flow to form a wafer with FinFET fins on the surface.

6. The method for manufacturing a semiconductor chip according to claim 5, wherein: The method of generating an ultra-shallow PN junction on a wafer of a FinFET fin by a low-temperature plasma doping method and selective laser annealing specifically includes the following steps: On the wafer with FinFET fins on the surface, a silicon dioxide protective layer is deposited using atomic layer deposition and pre-cleaned, and a mixed gas of diborane and argon is injected with boron ions using a low-temperature plasma doping device to form a doping layer; A krypton fluoride excimer laser is used to illuminate the doped layer through a photomask to activate boron atoms into substitutional sites in the silicon lattice, forming an ultra-shallow PN junction.

7. The method for manufacturing a semiconductor chip according to claim 6, wherein: The process of defining a gate pattern for a FinFET wafer having an ultra-shallow PN junction and outputting a FinFET wafer having a gate structure specifically includes the following steps: Depositing hafnium dioxide as a high-k gate dielectric by atomic layer deposition and titanium nitride as a metal gate using physical vapor deposition; The gate pattern is defined using an argon fluorine lithography machine and reactive ion etching equipment, ultimately forming a FinFET wafer with a high-k gate dielectric and metal gate structure on the surface.

8. The method for manufacturing a semiconductor chip according to claim 7, wherein: The step of obtaining the packaged semiconductor chip specifically includes the following steps: Based on the wafer with FinFET fins, ultra-shallow PN junctions, high-k gate dielectrics and metal gate structures on the surface, a dual damascene process is used to deposit silicon dioxide interlayer dielectrics, define interconnect trenches and fill them with copper to form multi-layer low-resistance copper interconnects. The chip is connected to the substrate using through-silicon vias (TSVs) through wafer dicing and then encapsulated with epoxy resin to obtain a packaged chip.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method for manufacturing a semiconductor chip according to any one of claims 1 to 8 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for manufacturing a semiconductor chip according to any one of claims 1 to 8 are implemented.

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