Regional activation hybrid gate structure, high electron mobility transistor and manufacturing method

Abstract

The invention relates to the technical field of transistor structures, and provides a region activation mixed gate structure, a high electron mobility transistor and a manufacturing method, and the structure comprises a substrate structure, and a source electrode and a drain electrode which are disposed on the substrate structure. The gate depletion layer is arranged on the substrate structure and between the source electrode and the drain electrode; an activation enhancement region is formed between the activation enhancement layer and the gate depletion layer; the gate lead-out layer is arranged on the activation enhancement area and the area, not covered by the activation enhancement layer, of the gate consumption layer, and the area, making contact with the gate consumption layer, of the gate lead-out layer forms a low-leakage area. An activation enhancement region with high grid leakage is formed through an activation enhancement layer, a path for rapidly releasing trapped charges in a grid consumption layer is provided, and by adjusting the proportion of the activation enhancement region to a low leakage region, the grid performance is guaranteed while the trapped charges are rapidly released, the influence of the trapped charges is reduced, and the threshold voltage drift is improved. The switch performance and stability are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor structures, and in particular to a regional activation hybrid gate structure, a high electron mobility transistor and a manufacturing method thereof. Background Art

[0002] HEMT (High Electron Mobility Transistor) is a field-effect device based on a heterojunction structure. Its core characteristics rely on the two-dimensional electron gas (2DEG) at the heterojunction interface. The two-dimensional electron gas, with its high carrier concentration and mobility characteristics, gives the device excellent high-frequency response, power carrying capacity and low energy consumption performance.

[0003] In the prior art, the gate structure of the enhancement mode HEMT is as follows Figure 5 As shown, due to the formation of Schottky junctions and PN junctions between different materials in the gate structure, the equivalent circuit is shown on the right, including two reverse-series diodes. As a result, when the device is subjected to gate bias or drain port stress voltage, a large amount of trapped charges will exist in the P-GaN (P-type doped gallium nitride) region of the gate structure. The accumulation of such trapped charges significantly affects the concentration distribution of the two-dimensional electron gas, resulting in threshold voltage drift problems, which in turn affects the switching performance and stability of the HEMT. Summary of the Invention

[0004] The present invention provides a region-activated hybrid gate structure, a high electron mobility transistor and a manufacturing method thereof, which are used to solve the defect in the prior art that gate trapped charges cannot be quickly released when a gate stress voltage or a drain stress voltage is applied.

[0005] The present invention provides a region-activated hybrid gate structure, comprising: A base structure, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are arranged on the base structure, and the base structure is used to form a conductive channel; a gate depletion layer, disposed on the base structure, the gate depletion layer being located between the source and the drain, and configured to consume carriers in the conductive channel so that the conductive channel between the source and the drain is normally closed; an activation enhancement layer, disposed on the gate depletion layer, wherein an activation enhancement region is formed between the activation enhancement layer and the gate depletion layer; a gate lead-out layer, disposed on the activation enhancement region and on a region of the gate consumption layer not covered by the activation enhancement layer, wherein the region where the gate lead-out layer contacts the gate consumption layer forms a low leakage region; The activation enhancement layer is used to enhance the activation degree of the gate depletion layer in the activation enhancement region, and the gate leakage current of the activation enhancement region is greater than the gate leakage current of the low leakage region.

[0006] According to the regional activation hybrid gate structure provided by the present invention, there are at least two activation enhancement regions, and the activation enhancement regions are arranged along the length direction of the gate depletion layer.

[0007] According to the zone-activated hybrid gate structure provided by the present invention, there are at least three activation enhancement regions, and the intervals between adjacent activation enhancement regions are equal.

[0008] According to the regional activation hybrid gate structure provided by the present invention, among the multiple equally spaced activation enhancement regions, the activation enhancement regions located at both ends of the gate depletion layer in the length direction are at least partially located outside the region formed by the line connecting the source and the drain ends.

[0009] According to the regional activation hybrid gate structure provided by the present invention, there are two source electrodes, the drain electrode is located between the two source electrodes, the gate depletion layer is annular, the drain electrode is located within the annular gate depletion layer, and the gate depletion layer and the activation enhancement layer are provided between the two source electrodes and the drain.

[0010] According to the regional activation hybrid gate structure provided by the present invention, the activation enhancement layer forms an ohmic contact with the gate depletion layer.

[0011] The present invention also provides a high electron mobility transistor, comprising the above-mentioned regional activation hybrid gate structure, wherein the base structure comprises a substrate layer, a GaN buffer layer and an AlGaN layer stacked sequentially from bottom to top, and a two-dimensional electron gas is formed between the GaN layer and the AlGaN layer as the conductive channel.

[0012] According to the high electron mobility transistor provided by the present invention, the gate depletion layer is a P-type doped Group III-V semiconductor layer.

[0013] According to the high electron mobility transistor provided by the present invention, the activation enhancement layer (500) is made of a conductive material.

[0014] According to the high electron mobility transistor provided by the present invention, the activation enhancement layer is a Ti layer or a TiN layer.

[0015] The present invention also provides a transistor manufacturing method, comprising: Making the base structure; Fabricating a gate depletion layer, a source electrode, a drain electrode, and a passivation layer on the substrate structure; forming an etching opening exposing the gate depletion layer on the passivation layer through a first etching process; According to the target activation enhancement area, an activation enhancement layer is formed in the etched opening; Depositing a protective dielectric on the surface and performing thermal annealing to activate the gate depletion layer; The protective dielectric is removed, and metal is deposited in the etched opening to form a gate lead-out layer.

[0016] According to the transistor manufacturing method provided by the present invention, the manufacturing of the gate depletion layer, the source, the drain and the passivation layer on the substrate structure includes: Define the gate depletion layer pattern and make the gate depletion layer; forming a first passivation layer to cover the base structure and the gate depletion layer; forming a source opening and a drain opening exposing the substrate structure through a second etching process, wherein the gate depletion layer is located between the source opening and the drain opening; By a first metal deposition process, a source electrode is formed in the source electrode opening, and a drain electrode is formed in the drain electrode opening; A second passivation layer is formed to cover the first passivation layer, the source electrode, and the drain electrode.

[0017] The regional activation hybrid gate structure, high electron mobility transistor and manufacturing method provided by the present invention have at least beneficial effects: the base structure forms a conductive channel, the gate depletion layer is located between the source and the drain, so that the conductive channel between the source and the drain is closed under normal conditions, achieving the effect of enhanced control, and applying voltage to the gate can control the opening and closing of the conductive channel between the source and the drain. An activation enhancement layer is provided on the gate depletion layer, and the gate lead-out layer covers the activation enhancement layer and the area of ​​the gate depletion layer not covered by the activation enhancement layer, forming an activation enhancement region in contact with the activation enhancement layer and a low leakage region in contact with the gate lead-out layer on the gate depletion layer. The activation enhancement layer activates more carriers in the activation enhancement region by enhancing the activation layer degree of the gate depletion layer in the activation enhancement region, thereby reducing the resistance of the activation enhancement region, thereby achieving the purpose of making the gate leakage current of the activation enhancement region greater than the gate leakage current of the low leakage region. In this way, by providing an activation enhancement layer on the gate depletion layer between the source and the drain, an activation enhancement region with high gate leakage is formed, which can provide a path for quickly releasing the trapped charges in the gate depletion layer. By adjusting the ratio of the activation enhancement region to the low leakage region, the gate performance can be guaranteed while achieving the purpose of quickly releasing the trapped charges, which is beneficial to reducing the impact of trapped charges and improving threshold voltage drift, thereby improving switching performance and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 It is a top view schematic diagram of one embodiment of the local activation hybrid gate structure provided by the present invention.

[0020] Figure 2 The regional activation hybrid gate structure provided by the present invention is Figure 1 Schematic cross-sectional view at point A in the embodiment.

[0021] Figure 3 The regional activation hybrid gate structure provided by the present invention is Figure 1 Schematic cross-sectional view at point B in the embodiment.

[0022] Figure 4 It is a process diagram of one embodiment of the transistor manufacturing method provided by the present invention.

[0023] Figure 5 Schematic diagram of the gate structure and equivalent circuit of an existing enhancement-mode HEMT.

[0024] Reference numerals: 100: Base structure; 110: Substrate layer; 120: GaN buffer layer; 130: AlGaN layer; 200: Source; 300: Drain; 400: Gate depletion layer; 410: Activation enhancement region; 420: Low leakage region; 500: Activation enhancement layer; 600: Gate lead-out layer; 700: Passivation layer; 800: Protective dielectric. DETAILED DESCRIPTION

[0025] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0026] The following combination Figures 1 to 3 The present invention is described as follows: A base structure 100, a source electrode 200, and a drain electrode 300, wherein the source electrode 200 and the drain electrode 300 are disposed on the base structure 100, and the base structure 100 is used to form a conductive channel; a gate depletion layer 400 disposed on the substrate structure 100 , the gate depletion layer 400 being located between the source 200 and the drain 300 , and configured to consume carriers in the conductive channel so that the conductive channel between the source 200 and the drain 300 is normally closed; An activation enhancement layer 500 is disposed on the gate depletion layer 400 to form an activation enhancement region 410; a gate lead-out layer 600 disposed on the activation enhancement region 410 and on a region of the gate consumption layer not covered by the activation enhancement layer 500 , wherein the region where the gate lead-out layer 600 contacts the gate consumption layer forms a low leakage region 420 ; The activation enhancement layer 500 includes doping-activated carriers, and the gate leakage current of the activation enhancement region 410 is greater than the gate leakage current of the low leakage region 420 .

[0027] The substrate structure 100 forms a conductive channel, and the gate depletion layer 400 is located between the source 200 and the drain 300. This makes the conductive channel between the source 200 and the drain 300 closed under normal conditions, achieving an enhanced control effect. Applying a voltage to the gate can control the opening and closing of the conductive channel between the source 200 and the drain 300. An activation enhancement layer 500 is provided on the gate depletion layer 400. A gate lead-out layer 600 covers the activation enhancement layer 500 and the area of ​​the gate depletion layer 400 not covered by the activation enhancement layer 500. An activation enhancement region 410 in contact with the activation enhancement layer 500 and a low leakage region 420 in contact with the gate lead-out layer 600 are formed on the gate depletion layer 400. The activation enhancement layer 500 enhances the activation layer degree of the gate depletion layer 400 in the activation enhancement region 410, thereby activating more carriers in the activation enhancement region 410 and reducing the resistance of the activation enhancement region 410, thereby achieving the purpose of making the gate leakage current of the activation enhancement region 410 greater than the gate leakage current of the low leakage region 420.

[0028] In this way, by providing an activation enhancement layer 500 on the gate depletion layer 400 between the source 200 and the drain 300, an activation enhancement region 410 with high gate leakage is formed, which can provide a path for quickly releasing the trapped charges in the gate depletion layer. By adjusting the ratio of the activation enhancement region 410 to the low leakage region 420, the gate performance can be guaranteed while achieving the purpose of quickly releasing the trapped charges, which is beneficial to reducing the impact of the trapped charges and improving the threshold voltage drift, thereby improving the switching performance and stability.

[0029] To consume carriers in the conductive channel, the gate depletion layer 400 is p-type doped. This doped gate depletion layer requires activation to release hydrogen ions from the p-type dopant, forming holes that consume electrons in the conductive channel. During activation, the activation enhancement layer 500 provides a channel for hydrogen ion release, facilitating the release of hydrogen ions from the p-type dopant in the gate depletion layer 400 and enhancing the activation level of the gate depletion layer 400. This results in the gate depletion layer 400 having both an activation enhancement region 410 with high gate leakage and a low leakage region 420 with low gate leakage.

[0030] In some embodiments of the present invention, gate depletion layer 400 is a GaN (gallium nitride) layer doped with Mg (magnesium). Mg is highly active in activation-enhanced region 410 and less active in low-leakage region 420. Gate depletion layer 400 can also be implemented with dopants other than Mg.

[0031] refer to Figure 1 In some embodiments of the region-activated hybrid gate structure of the present invention, there are at least two activation enhancement regions 410 , and the activation enhancement regions 410 are arranged along the length direction of the gate depletion layer 400 .

[0032] At least two activation enhancement layers 500 are provided along the length of the gate depletion layer 400 to form at least two corresponding activation enhancement regions 410. Providing multiple activation enhancement regions 410 helps shorten the path length for releasing trapped charges from the gate depletion layer 400. For different portions of the gate depletion layer 400 along the length, the activation enhancement region 410 with the closest path can be selected to quickly release trapped charges, thus preventing the path length of trapped charges released from certain regions of the gate depletion layer 400 from being excessively long. This helps improve the release efficiency of trapped charges and further reduces the impact of trapped charges.

[0033] refer to Figure 1 In some embodiments of the region-activated hybrid gate structure of the present invention, there are at least three activation enhancement regions 410 , and the intervals between adjacent activation enhancement regions 410 are equal.

[0034] The intervals between the activation enhancement regions 410 are equal, that is, the activation enhancement layers 500 are arranged at equal intervals, so that the influence of the activation enhancement layers 500 on the gate consumption layer is more balanced, avoiding excessive concentration of the activation enhancement regions 410 or the low leakage regions 420, and preventing the occurrence of local excessive gate leakage current, which is conducive to making the gate performance more balanced and stable.

[0035] In some embodiments of the present invention, the lengths of the activation enhancement regions 410 are equal. By making the lengths of the activation enhancement regions 410 equal, the influence of the activation enhancement regions 410 is made consistent, making the influence of the activation enhancement regions 410 on the gate depletion layer more balanced, thereby further facilitating more balanced and stable gate performance.

[0036] refer to Figure 1 In some embodiments of the regional activation hybrid gate structure of the present invention, among the multiple equally spaced activation enhancement regions 410, the activation enhancement regions 410 located at both ends of the gate depletion layer 400 in the length direction are at least partially located outside the region formed by the line connecting the ends of the source 200 and the drain 300.

[0037] There are multiple activation enhancement regions 410 arranged at equal distances, and the activation enhancement regions 410 at both ends are located outside the area formed by the line connecting the source and the drain 300 ends, which means that the overall length of the activation enhancement regions 410 arranged at equal distances is greater than the length of the source 200 and the drain 300. When the gate controls the opening and closing of the conductive channel between the source 200 and the drain 300, the activation enhancement regions 410 arranged at equal distances uniformly affect the conductive performance of the entire source 200 and the drain 300, which is beneficial to improving stability and reliability.

[0038] It can be understood that the area formed by connecting the ends of the source 200 and the drain 300, such as Figure 1 As shown, the area formed by the line connecting the upper end of the source 200 and the upper end of the drain 300 and the line connecting the lower end of the source 200 and the lower end of the drain 300. Figure 1 In the figure, the upper end of the first activation enhancement region 410 from top to bottom protrudes from the area formed by the line connecting the ends of the source 200 and the drain 300, and the lower end of the last activation enhancement region from top to bottom protrudes from the area formed by the line connecting the ends of the source 200 and the drain 300.

[0039] refer to Figure 1 In some embodiments of the regional activation hybrid gate structure of the present invention, there are two source electrodes 200, the drain electrode 300 is located between the two source electrodes 200, the gate depletion layer 400 is annular, the drain electrode 300 is located in the annular gate depletion layer 400, and the gate depletion layer 400 and the activation enhancement region 410 are provided between the two source electrodes 200 and the drain electrode 300.

[0040] By providing the source 200 on both sides of the drain 300, and providing the gate depletion layer 400 and the activation enhancement region 410 between the two source electrodes 200 and the drain 300, a conductive channel can be formed on both sides of the drain 300 when a voltage is applied to the gate, which is conducive to increasing the maximum current and maximum power consumption, thereby improving the performance of the transistor.

[0041] In some embodiments of the present invention, multiple drains 300 and sources 200 may be provided, and the drains 300 and sources 200 are arranged alternately, and a gate depletion layer 400 and an activation enhancement region 410 are provided between each group of drains 300 and sources 200. This structure can further increase the maximum current and maximum power consumption.

[0042] In some embodiments of the area-activated hybrid gate structure of the present invention, the activation enhancement layer 500 forms an ohmic contact with the gate depletion layer 400 .

[0043] The activation enhancement layer 500 can form an ohmic contact or an incomplete ohmic contact with the gate depletion layer 400, so that no equivalent diode is formed between the activation enhancement layer 500 and the gate depletion layer 400, so that trapped charges in the gate depletion layer 400 can be released more easily through the activation enhancement layer 500, which is conducive to further improving the efficiency of quickly releasing trapped charges and further reducing the impact of trapped charges. In this way, the activation enhancement layer 500, on the basis of enhancing the activation level of the gate depletion layer 400, forms an ohmic contact with the gate depletion layer 400, both of which help to quickly release trapped charges, further reduce the impact of trapped charges and improve threshold voltage drift, thereby improving switching performance and stability.

[0044] A Schottky contact is formed between the gate lead-out layer 600 and the gate depletion layer 400, exhibiting low capacitance characteristics. This shortens switching time, improves switching dynamics, reduces gate leakage current, and provides a large voltage swing for easier control. By adjusting the ratio of the activation-enhanced region 410 to the low-leakage region 420, the effects of the activation-enhanced region 410 and the low-leakage region 420 can be balanced. The activation-enhanced region 410 can reduce the impact of trapped charge and improve threshold voltage drift, enhancing switching performance and stability. The low-leakage region 420 also forms a Schottky contact, shortening switching time, improving switching dynamics, reducing gate leakage current, and facilitating control.

[0045] The high electron mobility transistor provided by the present invention is described below. The high electron mobility transistor described below and the area-activated hybrid gate structure described above can be referred to in correspondence with each other.

[0046] refer to Figure 2 and Figure 3 The present invention also provides a high electron mobility transistor, including the above-mentioned regional activation hybrid gate structure, wherein the base structure 100 includes a substrate layer 110, a GaN buffer layer 120 and an AlGaN layer 130 stacked in sequence from bottom to top, and a two-dimensional electron gas is formed between the GaN layer and the AlGaN layer 130 as the conductive channel.

[0047] A GaN (gallium nitride) buffer layer is epitaxially grown on the substrate layer 110 , and an AlGaN (aluminum gallium nitride) layer is epitaxially grown on the GaN buffer layer 120 . The GaN layer and the AlGaN layer 130 form a heterojunction, and a 2DEG (two-dimensional electron gas) is formed at the interface between the two as a conductive channel.

[0048] The gate depletion layer 400 is located between the source 200 and the drain 300, so that the conductive channel between the source 200 and the drain 300 is normally closed, achieving an enhanced control effect. An activation enhancement layer 500 is provided on the gate depletion layer 400, and a gate lead-out layer 600 covers the activation enhancement layer 500 and the area of ​​the gate depletion layer 400 not covered by the activation enhancement layer 500. An activation enhancement region 410 in contact with the activation enhancement layer 500 and a low leakage region 420 in contact with the gate lead-out layer 600 are formed on the gate depletion layer 400.

[0049] The activation enhancement layer 500 enhances the activation layer degree of the gate depletion layer 400 in the activation enhancement region 410, thereby activating more carriers in the activation enhancement region 410 and reducing the resistance of the activation enhancement region 410, thereby achieving the purpose of making the gate leakage current of the activation enhancement region 410 greater than the gate leakage current of the low leakage region 420.

[0050] Thus, in a HEMT, by providing an activation enhancement layer 500 on the gate depletion layer 400 between the source 200 and the drain 300, an activation enhancement region 410 with high gate leakage is formed. This provides a path for rapidly releasing trapped charge within the gate depletion layer. By adjusting the ratio of the activation enhancement region 410 to the low leakage region 420, gate performance can be maintained while achieving rapid release of trapped charge, thereby reducing the impact of trapped charge, improving threshold voltage drift, and enhancing switching performance and stability.

[0051] refer to Figure 2 and Figure 3 In some embodiments of the high electron mobility transistor of the present invention, the gate depletion layer 400 is a P-type doped Group III-V semiconductor layer.

[0052] The gate depletion layer 400 is made of a P-type doped III-V semiconductor, and may be specifically implemented as a P-GaN (P-doped gallium nitride) layer, a P-GaN and P-AlGaN (P-doped aluminum gallium nitride) composite layer, or the like.

[0053] The P-type doped III-V semiconductor layer consumes electrons of the 2DEG to achieve the purpose of normal shutdown, and the P-type doped III-V semiconductor layer has the advantages of high voltage resistance and strong reliability.

[0054] refer to Figure 2 and Figure 3In some embodiments of the high electron mobility transistor of the present invention, the activation enhancement layer 500 is made of a conductive material.

[0055] The activation enhancement layer 500 is made of a conductive material to provide an escape channel by utilizing the characteristics of the conductive material, so that hydrogen ions in the gate depletion layer 400 can leave the gate depletion layer 400 through the escape channel during thermal annealing, thereby achieving the effect of enhancing the activation level.

[0056] refer to Figure 2 and Figure 3 In some embodiments of the high electron mobility transistor of the present invention, the activation enhancement layer 500 is a Ti layer or a TiN layer.

[0057] The Ti (titanium) layer or the TiN (titanium nitride) layer can provide a channel to allow hydrogen ions of the dopant to leave the gate depletion layer 400 during the annealing process, thereby achieving an enhanced activation effect.

[0058] In some embodiments of the present invention, the activation enhancement layer 500 may be made of, in addition to Ti or TiN, other metals or metal compound materials that can allow hydrogen ions to leave the gate depletion layer 400, such as nickel.

[0059] In some embodiments of the present invention, the gate lead-out layer 600 may be implemented using TiN (titanium nitride). It should be emphasized that although the activation enhancement layer 500 and the gate lead-out layer 600 can both be implemented using TiN, the activation enhancement layer 500 participates in the annealing activation process. That is, during the annealing activation process, the gate lead-out layer 600 has not yet been formed. The activation enhancement layer 500 enhances the activation effect of the gate depletion layer 400, forming an activation-enhanced region. Regions of the gate depletion layer 400 not covered by the activation enhancement layer 500 exhibit a relatively low activation level, forming low-leakage regions. Fabricating the gate lead-out layer 600 after the annealing activation process does not affect the activation level of the low-leakage region. Therefore, the activation enhancement layer 500 and the gate lead-out layer 600 can be made of the same material, such as TiN. It is understandable that the activation enhancement layer 500 and the gate lead-out layer 600 can also be made of different materials. For example, the activation enhancement layer 500 is made of Ti. While achieving enhanced activation, Ti can form an ohmic contact with the gate depletion layer 400, while the gate lead-out layer 600 is made of TiN. TiN forms a Schottky contact with the gate depletion layer 400.

[0060] The transistor manufacturing method provided by the present invention is described below. The transistor manufacturing method described below and the area-activated hybrid gate structure and high electron mobility transistor described above can be referred to each other.

[0061] refer to Figure 4 The present invention also provides a transistor manufacturing method, comprising: manufacturing a base structure 100; A gate depletion layer 400 , a source electrode 200 , a drain electrode 300 and a passivation layer 700 are fabricated on the substrate structure 100 ; By a first etching process, an etching opening is formed on the passivation layer 700 to expose the gate depletion layer 400 ; According to the target activation enhancement region 410, an activation enhancement layer 500 is formed in the etched opening; Depositing a protective dielectric 800 on the surface and performing a thermal annealing process to activate the gate depletion layer 400; The protective dielectric 800 is removed, and metal is deposited in the etched opening to form a gate lead-out layer 600 .

[0062] After fabricating the base structure 100, gate depletion layer 400, source 200, drain 300, and passivation layer 700, an etching opening is formed on the passivation layer 700 and an activation enhancement layer 500 is fabricated in the target activation enhancement region 410. A protective dielectric 800 is deposited on the surface and then thermal annealing is performed. This not only protects the passivation layer 700, base structure 100, gate depletion layer 400, and activation enhancement layer 500 from high-temperature damage, but also ensures that the activation enhancement layer 500 directional guides the escape of hydrogen ions from the gate depletion layer 400, thereby activating the gate depletion layer 400. The thermal annealing provides a directional escape channel for hydrogen ions in the gate depletion layer 400, such as a P-type Mg-doped GaN layer. The activation enhancement layer 500 accelerates the release of hydrogen ions during the annealing process, forming an activation enhancement region 410 with high gate leakage current.

[0063] The activation-enhanced region 410 provides a path for rapidly releasing trapped charge within the gate depletion layer. By adjusting the ratio of the activation-enhanced region 410 to the low-leakage region 420, this rapid release of trapped charge is achieved, mitigating the impact of trapped charge and improving threshold voltage shift. This, in turn, preserves the gate control capability of the low-leakage region 420, enhancing switching performance and stability. By adjusting the ratio of the activation-enhanced region 410 to the low-leakage region 420, rapid charge release can be balanced with overall gate leakage performance, optimizing device reliability.

[0064] It should be emphasized that before the thermal annealing treatment, the activation enhancement layer 500 has been fabricated on the gate depletion layer 400 and participates in the thermal annealing treatment to achieve the effect of providing an escape channel for the hydrogen ions in the gate depletion layer 400, thereby achieving the goal of enhancing the activation level of the gate depletion layer 400 in the activation enhancement region 410.

[0065] It is understandable that after the gate lead-out layer is formed, other steps may be further included, such as etching and forming a source lead-out layer and a drain lead-out layer.

[0066] In some embodiments of the transistor manufacturing method of the present invention, the step of manufacturing the gate depletion layer 400, the source 200, the drain 300, and the passivation layer 700 on the substrate structure 100 includes: Defining a gate depletion layer 400 pattern and manufacturing the gate depletion layer 400; Fabricating a first passivation layer to cover the substrate structure 100 and the gate depletion layer 400; Through a second etching process, a source 200 opening and a drain 300 opening exposing the substrate structure 100 are formed, and the gate depletion layer 400 is located between the source 200 opening and the drain 300 opening; Through a first metal deposition process, the source electrode 200 is opened to form the source electrode 200 , and the drain electrode 300 is opened to form the drain electrode 300 ; A second passivation layer is formed to cover the first passivation layer, the source electrode 200 and the drain electrode 300 .

[0067] By defining the gate depletion layer 400 pattern and fabricating it on the substrate structure 100, the first passivation layer covers the substrate and the gate depletion layer 400 to prevent subsequent etching and metal deposition processes from damaging or contaminating the substrate structure 100. The source 200 opening and the drain 300 opening are formed by a second etching process. The source 200 and the drain 300 formed in the opening by the first metal deposition process form a low-resistance ohmic contact, thereby reducing conduction loss. The gate depletion layer 400 is located between the source 200 and the drain 300 openings, effectively controlling the conductive channel between the gate and the drain 300. After the source 200 and the drain 300 are fabricated, the second passivation layer covers the entirety, further isolating the source 200 and the drain 300, thereby improving the long-term stability of the device. The first passivation layer and the second passivation layer form the above-mentioned passivation layer 700. The layered passivation takes into account the compatibility between the process steps, avoiding excessive thickness of a single passivation, which may lead to interface stress or reduced etching accuracy.

[0068] It is understood that the first passivation layer and the second passivation layer formed form the passivation layer 700 in the above-mentioned hybrid gate structure. In some embodiments of the present invention, the first passivation layer and the second passivation layer can be formed using the same material, such as silicon oxide, silicon nitride, etc. In some embodiments of the present invention, the first passivation layer and the second passivation layer can also be formed using different materials, such as silicon oxide for the first passivation layer and silicon nitride for the second passivation layer.

[0069] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0070] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A region-activated hybrid gate structure, characterized in that: include: A base structure (100), a source electrode (200), and a drain electrode (300), wherein the source electrode (200) and the drain electrode (300) are arranged on the base structure (100), and the base structure (100) is used to form a conductive channel; A gate depletion layer (400) is provided on the base structure (100), the gate depletion layer (400) is located between the source (200) and the drain (300), and the gate depletion layer (400) is used to consume carriers in the conductive channel so that the conductive channel between the source (200) and the drain (300) is normally closed; An activation enhancement layer (500) is provided on the gate depletion layer (400), and an activation enhancement region (410) is formed between the activation enhancement layer (500) and the gate depletion layer (400); A gate lead-out layer (600) is provided on the activation enhancement region (410) and on a region of the gate consumption layer not covered by the activation enhancement layer (500), wherein the region where the gate lead-out layer (600) contacts the gate consumption layer forms a low leakage region (420); The activation enhancement layer (500) is used to enhance the activation degree of the gate depletion layer (400) in the activation enhancement region (410), and the gate leakage current of the activation enhancement region (410) is greater than the gate leakage current of the low leakage region (420).

2. The local activation hybrid gate structure according to claim 1, wherein: There are at least two activation enhancement regions (410), and the activation enhancement regions (410) are arranged along the length direction of the gate depletion layer (400).

3. The local activation hybrid gate structure according to claim 2, wherein: There are at least three activation enhancement areas (410), and the intervals between adjacent activation enhancement areas (410) are equal.

4. The local activation hybrid gate structure according to claim 3, wherein: Among the plurality of equally spaced activation enhancement regions (410), the activation enhancement regions (410) located at both ends of the gate depletion layer (400) in the length direction are at least partially located outside a region formed by a line connecting the ends of the source (200) and the drain (300).

5. The local activation hybrid gate structure according to any one of claims 1 to 4, characterized in that: There are two source electrodes (200), the drain electrode (300) is located between the two source electrodes (200), the gate depletion layer (400) is annular, the drain electrode (300) is located within the annular gate depletion layer (400), and the gate depletion layer (400) and the activation enhancement layer (500) are both provided between the two source electrodes (200) and the drain electrode (300).

6. The local activation hybrid gate structure according to claim 1, wherein: The activation enhancement layer (500) forms an ohmic contact with the gate depletion layer (400).

7. A high electron mobility transistor, characterized in that The invention comprises a regional activation hybrid gate structure according to any one of claims 1 to 6, wherein the base structure (100) comprises a substrate layer (110), a GaN buffer layer (120) and an AlGaN layer (130) stacked in sequence from bottom to top, and a two-dimensional electron gas is formed between the GaN layer and the AlGaN layer (130) as the conductive channel.

8. The high electron mobility transistor according to claim 7, wherein: The gate depletion layer (400) is a P-type doped III-V group semiconductor layer.

9. The high electron mobility transistor according to claim 7, wherein: The activation enhancement layer (500) is made of a conductive material.

10. The high electron mobility transistor according to claim 9, wherein The activation enhancement layer (500) is a Ti layer or a TiN layer.

11. A method for manufacturing a transistor, characterized in that: include: making a base structure (100); Fabricating a gate depletion layer (400), a source electrode (200), a drain electrode (300), and a passivation layer (700) on the substrate structure (100); forming an etching opening exposing the gate depletion layer (400) on the passivation layer (700) through a first etching process; According to the target activation enhancement region (410), an activation enhancement layer (500) is formed in the etched opening; Depositing a protective medium (800) on the surface, and performing a thermal annealing process to activate the gate depletion layer (400); The protective medium (800) is removed, and metal is deposited in the etched opening to produce a gate lead-out layer (600).

12. The transistor manufacturing method according to claim 11, wherein: The method of manufacturing a gate depletion layer (400), a source electrode (200), a drain electrode (300), and a passivation layer (700) on a substrate structure (100) comprises: Defining a gate depletion layer (400) pattern and making the gate depletion layer (400); Making a first passivation layer to cover the base structure (100) and the gate depletion layer (400); A source (200) opening and a drain (300) opening exposing the substrate structure (100) are formed through a second etching process, wherein the gate depletion layer (400) is located between the source (200) opening and the drain (300) opening; Through a first metal deposition process, a source electrode (200) is formed at the source electrode (200) opening, and a drain electrode (300) is formed at the drain electrode (300) opening; A second passivation layer is produced to cover the first passivation layer, the source electrode (200) and the drain electrode (300).

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