Low-leakage Schottky diode and preparation method thereof

Abstract

The invention relates to the technical field of diode preparation, and particularly discloses a low-leakage Schottky diode and a preparation method thereof. The first N type GaN layer is arranged on the substrate; the first N-type GaN layer comprises a plane layer and a boss structure arranged on the plane layer; the N-type buried layer is arranged on the first N-type GaN layer; the second N-type GaN layer is arranged on the boss structure; the JTE region is arranged on the partial upper surface of the second N-type GaN layer, the side wall of the second N-type GaN layer, the side wall of the boss structure and the partial upper surface of the plane layer; the JTE region is a P-type GaN layer, is formed by Mg ion injection activation, and is not in contact with the Schottky electrode, the front ohmic electrode and the back ohmic electrode. The Mg-JTE terminal is adopted, a metal P-type terminal layer is not used, and the shielding effect, electric field reflection and distortion and high-frequency stray capacitance interference or inductance interference of metal under high frequency are eliminated from the source.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of diode preparation, and particularly relates to a low-leakage Schottky diode and a preparation method thereof. BACKGROUND

[0002] The Schottky diode is a metal-semiconductor junction diode, also known as a hot carrier diode, a low-voltage diode or a Schottky barrier diode. The Schottky diode is formed by a junction of a semiconductor and a metal. The Schottky diode provides fast switching action and has a low forward voltage drop; in a PN junction diode, a p-type and an n-type are connected together to form a PN junction, while in the Schottky diode, a metal such as platinum or aluminum is used instead of a p-type semiconductor; compared with the PN junction diode, the maximum feature of the Schottky diode is a small forward voltage drop and a short reverse recovery time, in addition, the Schottky diode has a low turn-on voltage, a small charge storage effect, and is extremely suitable for high-frequency operation, but the high-frequency operation itself brings some changes in environmental parameters, such as temperature and field effect caused by high frequency, the Schottky diode is highly sensitive to environmental parameters, therefore, it is easy to produce special problems in the high-frequency operation scene, therefore, how to improve the stability of the Schottky diode is a technical problem to be solved by the technical scheme of the present application. SUMMARY

[0003] The present application aims to provide a low-leakage Schottky diode and a preparation method thereof to solve the problems in the background.

[0004] To achieve the above object, the present application provides the following technical scheme. A low-leakage Schottky diode and a preparation method thereof, comprising.

[0005] a substrate; a first N-type GaN layer arranged on the substrate; the first N-type GaN layer comprises a planar layer and a boss structure arranged on the planar layer; an N-type buried layer arranged on the first N-type GaN layer; the N-type buried layer is partially arranged below the boss structure; a second N-type GaN layer arranged on the boss structure; a JTE region arranged on a part of an upper surface of the second N-type GaN layer, a sidewall of the second N-type GaN layer, a sidewall of the boss structure and a part of an upper surface of the planar layer; the JTE region is a P-type GaN layer formed by Mg ion implantation and activation, and does not contact the Schottky electrode, the front ohmic electrode and the back ohmic electrode; a Schottky electrode arranged on a remaining upper surface of the second N-type GaN layer; the Schottky electrode comprises a first contact layer and a first metal layer; a front ohmic electrode arranged on a remaining upper surface of the planar layer; the front ohmic electrode comprises a second contact layer and a second metal layer; A back ohmic electrode is disposed on the back side of the substrate; A composite passivation layer deposited at the Schottky edge and above the JTE.

[0006] As a further aspect of the present invention: the substrate is an Al2O3 substrate with a thickness of 430μm-650μm and a surface roughness not exceeding 0.5nm; the planar layer has a thickness of 2.0μm-2.5μm, and the doped ions are Si with a doping concentration of 1×10⁻⁶. 19 cm -3 -5×10 19 cm -3 The boss height is 0.6μm-0.8μm; the doping type is consistent with the planar layer, and the concentration is not less than 1×10⁻⁶. 19 cm -3 The thickness of the N-type buried layer is 0.15 μm-0.3 μm, and the doping ion is Si with a doping concentration of 5 × 10⁻⁶. 18 cm -3 -1×10 19 cm -3 The thickness of the second N-type GaN layer is 4.5 μm-5.0 μm; the dopant ion is Si, and the doping concentration is 1×10⁻⁶. 16 cm -3 -5×10 17 cm -3 The back ohmic electrode is made of a Ti, Ni, and Au composite layer with thicknesses of 20 nm, 50 nm, and 200 nm, respectively, and its contact resistance after annealing does not exceed 1 × 10⁻⁶. -5 Ω·cm 2 .

[0007] As a further aspect of the present invention: the equivalent doping concentration of Mg after activation is 1×10⁻⁶. 19 cm -3 -5×10 19 cm -3 The lateral width of the JTE region is 35μm-45μm.

[0008] As a further aspect of the present invention: the first contact layer is made of Ni with a thickness of 80nm-100nm; the first metal layer is made of Au with a thickness of 500nm-800nm; the Schottky electrode contact interface barrier height is not less than 1.05eV; the second contact layer is a Ti, Al, and Ni composite layer with thicknesses of 20nm, 120nm, and 40nm, respectively; the second metal layer is made of Al with a thickness of 800nm; and the specific contact resistance after annealing does not exceed 5×10⁻⁶. -6 Ω·cm 2 .

[0009] As a further scheme of the present application: the gap between the JTE region and the Schottky electrode is 6-8 μm; the gap between the JTE region and the front ohmic electrode is 6-8 μm.

[0010] As a further scheme of the present application: the composite passivation layer comprises a bottom layer and an upper layer, the dielectric constant equivalent value of the composite passivation layer is not more than 6.5, and the interface state density is not more than 5×10 11 cm -2 ·eV -1 ; the passivation layer does not cover the Schottky contact central region, but covers only the edge within a range of 5-10 μm.

[0011] The present application also provides a preparation method of the low-leakage Schottky diode. The first N-type GaN layer, the N-type buried layer and the second N-type GaN layer are sequentially epitaxially grown on the substrate; the first N-type GaN layer is grown by MOCVD, at a temperature of 1050℃, a pressure of 150 Torr, a V / III ratio of 3000, a growth rate of 1 μm / h, and with SiH4 as the doping source for controlling the concentration; the N-type buried layer is grown at a temperature of 1050℃, a pressure of 150 Torr, a V / III ratio of 3000, a growth rate of 1 μm / h, and with SiH4 as the doping source for controlling the concentration; the second N-type GaN layer is grown by MOCVD, at a temperature of 1040℃, a pressure of 120 Torr, a V / III ratio of 3500, and with SiH4 as the doping source but at a flow rate less than that in the growth of the first N-type GaN layer, and at a concentration range of 1×10 16 -5×10 17 cm -3 ; SiH4 is used as the doping source for controlling the concentration, and the control target is the Si concentration; The first N-type GaN layer and the second N-type GaN layer are etched by ICP-RIE dry etching; the etching gas comprises Cl2, BCl3 and Ar, at flow rates of 15 sccm, 5 sccm and 10 sccm respectively, at an RF power of 120 W, an ICP power of 600 W, and a rate of 300-450 nm / min, to form a convex height of 0.6-0.8 μm and a sidewall angle of 88-90° straight wall; Mg ion implantation is performed by using SiO2 hard mask as a mask plate to cover the area outside the JTE region; the implantation energy is 150 keV, and the dose is 1.5×10 14 cm -2 and 5×10 13 cm -2 ; a 2-window lateral gradual change design is adopted, and the edge window is expanded outward by 35-45 μm; High-temperature annealing activates Mg ions and N-type buried layer; annealing parameters: temperature is 1250 DEG C, time is 30 min, pressure is normal pressure, protective gas is nitrogen, flow is 5L / min, heating rate is 25 DEG C / min, cooling rate is 15 DEG C / min; HF wet method is used to remove SiO2 hard mask, and electron beam evaporation is used to deposit electrode; removal parameters are that the concentration of HF solution is 5%, and immersion time is 60s; TiN, Ni and Au are deposited in sequence to form contact, and then annealing is carried out to form stable contact layer; annealing parameters are that temperature is 400 DEG C, annealing time is 30s, protective gas is nitrogen, and flow is 5L / min; wherein, the thickness of TiN is 10nm, the thickness of Ni is 80nm-100nm, and the thickness of Au is 500nm-800nm; Ti, Al and Ni are evaporated, and then Al is covered to form low-resistance ohmic contact by annealing; annealing parameters are that temperature is 500 DEG C, annealing time is 30s, protective gas is nitrogen, and flow is 5L / min; Ti, Ni and Au are evaporated to form Schottky diode by annealing.

[0012] As a further scheme of the application, the preparation method further comprises: The device edge adopts single ICP dry method to form a bevel angle terminal, and the angle is 30 DEG -40 DEG, and the etching depth penetrates the second N-type GaN layer to the convex wall.

[0013] Compared with the prior art, the application has the beneficial effects that: the first N-type GaN layer, the N-type buried layer and the second N-type GaN layer are completed by one-time epitaxy in the application, which are respectively used as a plane layer, a buried layer and a drift layer, and a clear energy band gradient is formed by three layers of doping, so that the depletion expansion under reverse bias is stably controlled in the drift layer, the main barrier is greatly reduced due to the fluctuation of junction temperature, in addition, the hot carriers under reverse high temperature preferentially pump laterally to the buried depletion zone, rather than penetrating the main Ni / Au Schottky interface, the Jolthot is quickly bypassed during high-frequency surge, and the local hotspot temperature is prevented from exceeding the critical melting of Ni / Au, the positive feedback link of high-temperature TE leakage index rising and self-heating can be broken, and the leakage growth under high frequency / high temperature is limited to below 2 orders of magnitude.

[0014] The application adopts Mg-JTE terminal, and does not use metal P-type terminal layer, so that the shielding effect (affecting barrier uniformity), electric field reflection and distortion (causing edge breakdown in advance) and high-frequency parasitic capacitance / inductance interference (causing signal reflection and unstable switching) of metal under high frequency are eliminated from the root.

[0015] The present invention employs a selective composite passivation layer that covers only the Schottky edge region, forming a "local interface defect freezing and surface electric field buffer layer", which can make the interface state density sufficiently small, thereby suppressing surface state-assisted conductivity.

[0016] This invention uses TiN and Ni to form an ultrathin NiSi composite barrier after annealing, forming a thermally stable, uniform barrier with low interface defects, no cracking, and no high-frequency shielding interference MS junction. This ensures minimal barrier height drift under high-frequency or high-temperature conditions, stable interface band structure, and no triggering of tunneling or TFE field emission leakage current. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention.

[0018] Figure 1 This is a schematic diagram of a low-leakage Schottky diode.

[0019] Figure 2 This is the first sub-flowchart of the method for fabricating a low-leakage Schottky diode.

[0020] Figure 3 This is the second sub-flowchart of the method for fabricating a low-leakage Schottky diode.

[0021] In the figure: 1-substrate, 2-first N-type GaN layer, 3-boob structure, 4-second N-type GaN layer, 5-Schottky electrode, 6-front ohmic electrode. Detailed Implementation

[0022] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0023] Example 1 like Figure 1 As shown, the technical solution of the present invention provides a low leakage Schottky diode, specifically comprising: Substrate 1; A first N-type GaN layer 2 is disposed on the substrate 1; the first N-type GaN layer includes a planar layer and a boss structure 3 disposed on the planar layer; The first N-type GaN layer 2 is an N-type buried layer; the N-type buried layer portion is located below the boss structure 3; A second N-type GaN layer 4 is disposed on the boss structure 3; The substrate 1 is an Al2O3 substrate 1 with a thickness of 430 μm, a surface roughness of not more than 0.5 nm, the planar layer has a thickness of 2.0 μm, the doping ion is Si, and the doping concentration is 1×10 19 cm -3 -3; the height of the mesa is 0.6 μm; the doping type is consistent with that of the planar layer, and the concentration is not less than 1×10 19 cm -3 -3; the N-type buried layer has a thickness of 0.15 μm, the doping ion is Si, and the doping concentration is 5×10 18 cm -3 -3; the second N-type GaN layer 4 has a thickness of 4.5 μm; the doping ion is Si, and the doping concentration is 1×10 16 cm -3 -3; the back ohmic electrode is made of a Ti, Ni and Au composite layer with thicknesses of 20 nm, 50 nm and 200 nm respectively, and the contact resistance after annealing is not more than 1×10 -5 Ω·cm 2 .

[0024] A JTE region is arranged on part of the upper surface of the second N-type GaN layer, the sidewall of the second N-type GaN layer, the sidewall of the mesa structure 3 and part of the upper surface of the planar layer; the JTE region is a P-type GaN layer formed by Mg ion implantation and activation, and does not contact the Schottky electrode 5, the front ohmic electrode 6 and the back ohmic electrode; A Schottky electrode 5 is arranged on the remaining upper surface of the second N-type GaN layer 4, and the Schottky electrode 5 comprises a first contact layer and a first metal layer; A front ohmic electrode 6 is arranged on the remaining upper surface of the planar layer, and the front ohmic electrode 6 comprises a second contact layer and a second metal layer; The material of the first contact layer is Ni, and the thickness is 80 nm; the material of the first metal layer is Au, and the thickness is 500 nm; the height of the Schottky electrode contact interface barrier is not less than 1.05 eV; the material of the second contact layer is a Ti, Al and Ni composite layer with thicknesses of 20 nm, 120 nm and 40 nm respectively; the material of the second metal layer is Al, and the thickness is 800 nm; the specific contact resistance after annealing is not more than 5×10 -6 Ω·cm 2 .

[0025] A back ohmic electrode is arranged on the back of the substrate 1; A composite passivation layer is deposited above the Schottky edge and the JTE.

[0026] The composite passivation layer comprises a bottom layer and an upper layer, and the equivalent value of the dielectric constant of the composite passivation layer is not more than 6.5, and the interface state density is not more than 5×10 11 cm -2·eV -1 ; the passivation layer does not cover the center area of the Schottky contact, but only covers the edge in the range of 5-10 μm.

[0027] As shown in Figure 2 and Figure 3 , the present application also provides a preparation method of the low-leakage Schottky diode, which comprises the following steps: Step S1: sequentially epitaxially growing a first N-type GaN layer 2, an N-type buried layer and a second N-type GaN layer 4 on a substrate 1; Wherein, the first N-type GaN layer 2 is grown by MOCVD, the temperature is 1050℃, the pressure is 150 Torr, the V / III ratio is 3000, the growth rate is 1 μm / h, and SiH4 is used as the doping source to control the concentration; the temperature of the N-type buried layer is 1050℃, the pressure is 150 Torr, the V / III ratio is 3000, the growth rate is 1 μm / h, and SiH4 is used as the doping source to control the concentration; the second N-type GaN layer 4 is grown by MOCVD, the temperature is 1040℃, the pressure is 120 Torr, the V / III ratio is 3500, the doping source is also SiH4 but the flow rate is less than that of the first N-type GaN layer 2, and the concentration range is 1×10 16 ; SiH4 is used as the doping source to control the concentration, and the control target is the concentration of Si; Step S2: etching the first N-type GaN layer 2 and the second N-type GaN layer 4 by ICP-RIE dry etching; Wherein, the etching gas comprises Cl2, BCl3 and Ar, the flow rates are 15 sccm, 5 sccm and 10 sccm respectively, the RF power is 120 W, the ICP power is 600 W, the rate is 300 nm / min, the height of the convex platform is 0.6 μm, and the sidewall inclination angle is 90° straight wall; Step S3: using SiO2 hard mask as a mask plate to cover the area outside the JTE region, and performing Mg ion implantation; Wherein, the implantation energy in the Mg ion implantation process is 150 keV, the dose is 1.5×10 14 cm -2 and 5×10 13 cm -2 , a 2-window lateral gradual change design is adopted, and the edge window expands outward by 35-45 μm; Step S4: high-temperature annealing to activate the Mg ions and the N-type buried layer; the annealing parameters are: the temperature is 1250℃, the time is 30 min, the pressure is normal pressure, the protective gas is nitrogen, the flow rate is 5 L / min, the heating rate is 25℃ / min, and the cooling rate is 15℃ / min; Step S5: remove the SiO2 hard mask by HF wet method, and deposit the electrode by electron beam evaporation; the removal parameters are that the concentration of the HF solution is 5%, and the soaking time is 60s; Step S6: deposit TiN, Ni and Au in sequence to form a contact, and then perform annealing to form a stable contact layer; the annealing parameters are that the temperature is 400℃, the annealing time is 30s, the protective gas is nitrogen, and the flow rate is 5L / min; wherein the thickness of the TiN is 10nm, the thickness of the Ni is 80nm, and the thickness of the Au is 500nm; Step S7: evaporate Ti, Al and Ni, and then cover Al to perform annealing to form a low-resistance ohmic contact; the annealing parameters are that the temperature is 500℃, the annealing time is 30s, the protective gas is nitrogen, and the flow rate is 5L / min; Step S8: evaporate Ti, Ni and Au to perform annealing to form a Schottky diode.

[0028] Regarding the diode prepared by the above preparation method, the core process includes an N-type buried layer, a non-contact JTE region, a composite passivation layer, a TiN and a NiSi ultra-thin composite barrier, and the specific description is as follows: The N-type buried layer can form a local high-doped region (non-continuous metal layer) by epitaxy, without introducing metal shielding interference, and the working principle is that under reverse bias, there is a lateral electric field and a depletion region expansion at the edge of the main junction, the buried layer serves as a local high-electron-concentration layer to establish a low-resistance current bypass in advance, guide the edge leakage current and the carrier under reverse bias to the center, and suppress the edge local barrier reduction and tunneling triggering. In addition, at high temperature (150℃), the Ni / Au barrier height decreases with temperature, resulting in an increase in TE current, but the buried layer provides a lower energy band rise channel, and the reverse current preferentially expands laterally in the buried layer region rather than directly penetrating the main Schottky interface, thereby breaking the positive feedback link of "heat, leakage, and more heat", and improving the junction temperature stability. On this basis, for a surge current, the IFSM1A (package level) corresponds to a chip internal instantaneous current density of 10 2 -10 3 A / cm 2 , the buried layer can instantaneously increase the conductance (electron concentration 5×10 18 -1×10 19 cm -3 ) during the surge period, realize rapid current sinking, and avoid melting of the main Ni / Au layer due to Joule heat.

[0029] The composite passivation layer is only deposited in the Schottky edge region, and the center region of the main junction is not covered with the passivation layer, so as to avoid increasing the junction capacitance, and the principle is that ALD-Al2O3 is deposited at a low temperature of 350℃, which can reduce the interface state density to 10 11 cm -2 ·eV -1The Al2O3 has high dielectric constant and high energy band offset, can reduce the peak value of the surface electric field of GaN, delay the early breakdown, and at high temperature, the Al2O3 as an interface thermal passivation layer can reduce the thermal activation contribution of the interface traps, so that the high-temperature Ir growth is limited within 2 orders of magnitude.

[0030] For the TiN and NiSi ultra-thin composite barrier, TiN is used as a thermal stable transition layer, and after Ni annealing, a NiSi composite Schottky barrier is formed. The working principle is that the effective work function of the NiSi / TiN composite contact is higher than that of pure Ni, so that the barrier height can be stably ≥1.05eV, meeting the high-temperature TE leakage suppression requirement. TiN is used as a diffusion control layer to inhibit the agglomeration and interface diffusion of Ni at high temperature, so that the barrier height deviation does not exceed 0.05eV, and the local tunneling path is improved. TiN has high-temperature chemical stability and low diffusion coefficient, so that the barrier layer is not unstable and does not break and form deep diffusion in 1250℃ annealing.

[0031] Embodiment 2 Different from embodiment 1, the substrate 1 is an Al2O3 substrate 1 with a thickness of 650μm; the surface roughness is not more than 0.5nm; the planar layer has a thickness of 2.5μm, and the doping ion is Si with a doping concentration of 5×10 19 cm -3 -1; the bump height is 0.8μm; the doping type is consistent with that of the planar layer, and the concentration is not less than 1×10 19 cm -3 -1; the N-type buried layer has a thickness of 0.3μm, and the doping ion is Si with a doping concentration of 1×10 19 cm -3 -1; the second N-type GaN layer 4 has a thickness of 5.0μm; the doping ion is Si with a doping concentration of 5×10 17 cm -3 -1; the back surface ohmic electrode is a Ti, Ni and Au composite layer with thicknesses of 20nm, 50nm and 200nm respectively, and the contact resistance after annealing is not more than 1×10⁻ 5 Ω·cm²; The first contact layer is Ni with a thickness of 100nm; the first metal layer is Au with a thickness of 500nm-800nm; the Schottky electrode contact interface barrier height is not less than 1.05eV; the second contact layer is a Ti, Al and Ni composite layer with thicknesses of 20nm, 120nm and 40nm respectively; the second metal layer is Al with a thickness of 800nm; and the specific contact resistance after annealing is not more than 5×10 -6 Ω·cm².

[0032] The gap between the JTE region and the Schottky electrode 5 is 8 μm; the gap between the JTE region and the front ohmic electrode 6 is 8 μm.

[0033] Embodiment 3 Different from Embodiment 1, the equivalent doping concentration after Mg activation is 1×10 18 cm -3 The lateral width of the JTE region is 35 μm; the gap between the JTE region and the Schottky electrode 5 is 6 μm; the gap between the JTE region and the front ohmic electrode 6 is 6 μm.

[0034] The non-contact JTE region is kept 6-8 μm apart from all electrodes, so that the electric field interference caused by metal can be avoided. The working principle is that a P-type region with an equivalent doping concentration of 1×10 18 cm 6 is formed after Mg activation. Under reverse bias, a lateral expansion depletion region is formed with the N- drift layer, so that the vertical breakdown is delayed, the edge of the depletion layer is smooth and continuous, the electric field concentration is avoided, the terminal is not in contact with the electrode, so that the Schottky interface barrier is only determined by the central Ni / Au / TiN, and the edge hot carriers are captured by the JTE depletion region, so that the edge hot carrier injection into the metal-semiconductor interface is reduced, and the barrier consistency is improved.

[0035] Embodiment 4 Different from Embodiment 1, the preparation method further comprises: The device edge adopts single ICP dry method bevel etching to form a bevel terminal, the angle is 40°, and the etching depth penetrates through the second N-type GaN layer 4 to the side wall of the convex.

[0036] As a preferred embodiment of the technical scheme of the application, through the 30°-40° bevel, the electric field can be converted from the vertical direction to the lateral direction, the terminal electric field peak value is reduced to 2×10 6 V / cm (much lower than the peak value of 3-5×10 6 V / cm of the straight wall structure), the early breakdown is inhibited, and the reverse breakdown voltage reliability is improved.

[0037] In addition, it is worth mentioning that in the technical scheme of the application, the N-type buried layer and the JTE region are processed by one-time annealing process. The one-time annealing can realize the Mg activation process at the same time, so as to form a P-JTE terminal, so that the damage repair and activation of the N-type buried layer can be realized, and the Schottky interface defect annealing repair can also be realized.

[0038] The above only describes the preferred embodiments of the application and is not used to limit the application. Any modification, equivalent replacement and improvement made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A low-leakage Schottky diode, characterized in that, The diode includes: Substrate; A first N-type GaN layer is disposed on the substrate; the first N-type GaN layer includes a planar layer and a boss structure disposed on the planar layer; An N-type buried layer is disposed on the first N-type GaN layer; the N-type buried layer is partially positioned below the boss structure; A second N-type GaN layer is disposed on the boss structure; JTE regions are disposed on a portion of the upper surface of the second N-type GaN layer, the sidewall of the second N-type GaN layer, the sidewall of the boss structure, and a portion of the upper surface of the planar layer; the JTE regions are P-type GaN layers, formed by Mg ion implantation activation, and do not contact the Schottky electrode, the front ohmic electrode, or the back ohmic electrode. A Schottky electrode is disposed on the remaining upper surface of the second N-type GaN layer, the Schottky electrode comprising a first contact layer and a first metal layer; A front ohmic electrode is disposed on the remaining upper surface of the planar layer, the front ohmic electrode comprising a second contact layer and a second metal layer; A back ohmic electrode is disposed on the back side of the substrate; A composite passivation layer deposited at the Schottky edge and above the JTE.

2. The low leakage current Schottky diode according to claim 1, characterized in that, The substrate is an Al2O3 substrate with a thickness of 430μm-650μm and a surface roughness not exceeding 0.5nm; the planar layer has a thickness of 2.0μm-2.5μm, and is doped with Si ions at a doping concentration of 1×10⁻⁶. 19 cm -3 -5×10 19 cm -3 The boss height is 0.6μm-0.8μm; the doping type is consistent with the planar layer, and the concentration is not less than 1×10⁻⁶. 19 cm -3 The thickness of the N-type buried layer is 0.15 μm-0.3 μm, and the doping ion is Si with a doping concentration of 5 × 10⁻⁶. 18 cm -3 -1×10 19 cm -3 The thickness of the second N-type GaN layer is 4.5 μm-5.0 μm; the dopant ion is Si, and the doping concentration is 1×10⁻⁶. 16 cm -3 -5×10 17 cm -3 The back ohmic electrode is made of a Ti, Ni, and Au composite layer with thicknesses of 20 nm, 50 nm, and 200 nm, respectively, and its contact resistance after annealing does not exceed 1 × 10⁻⁻⁻⁶. 5 Ω·cm².

3. The low leakage current Schottky diode according to claim 1, characterized in that, The equivalent doping concentration of Mg after activation is 1×10¹ 8 cm -3 -5×10¹ 8 cm -3 The lateral width of the JTE region is 35μm-45μm.

4. The low leakage current Schottky diode according to claim 1, characterized in that, The first contact layer is made of Ni with a thickness of 80nm-100nm; the first metal layer is made of Au with a thickness of 500nm-800nm; the Schottky electrode contact interface barrier height is not less than 1.05eV; the second contact layer is a composite layer of Ti, Al, and Ni with thicknesses of 20nm, 120nm, and 40nm, respectively; the second metal layer is made of Al with a thickness of 800nm; the specific contact resistance after annealing does not exceed 5×10⁻⁶. -6 Ω·cm².

5. The low leakage current Schottky diode according to claim 1, characterized in that, The gap between the JTE region and the Schottky electrode is 6μm-8μm; the gap between the JTE region and the front ohmic electrode is 6μm-8μm.

6. The low leakage current Schottky diode according to claim 1, characterized in that, The composite passivation layer comprises a bottom layer and a top layer. The equivalent dielectric constant of the composite passivation layer does not exceed 6.5, and the interface state density does not exceed 5 × 10⁻⁶. 11 cm -2 ·eV -1 The passivation layer does not cover the central region of the Schottky contact, but only covers the edge range of 5μm-10μm.

7. A method for fabricating a low-leakage Schottky diode as described in any one of claims 1 to 6, characterized in that, The preparation method includes: A first N-type GaN layer, an N-type buried layer, and a second N-type GaN layer were sequentially epitaxially grown on a substrate. The first N-type GaN layer was grown using MOCVD at a temperature of 1050℃, a pressure of 150 Torr, a V / III ratio of 3000, and a growth rate of 1 μm / h, with SiH4 introduced as the dopant source to control the concentration. The N-type buried layer was grown at the same temperature of 1050℃, a pressure of 150 Torr, a V / III ratio of 3000, and a growth rate of 1 μm / h, with SiH4 introduced as the dopant source to control the concentration. The second N-type GaN layer was grown using MOCVD at a temperature of 1040℃, a pressure of 120 Torr, a V / III ratio of 3500, with SiH4 as the dopant source but at a lower flow rate than that used in the first N-type GaN layer, and a concentration range of 1 × 10⁻⁶. 16 -5×10 17 cm -3 SiH4 is used as a doping source to control the concentration, and the target of control is the concentration of Si. The first and second N-type GaN layers were etched using ICP-RIE dry etching. The etching gases included Cl2, BCl3, and Ar, with flow rates of 15 sccm, 5 sccm, and 10 sccm, respectively. The RF power was 120 W, the ICP power was 600 W, and the etching rate was 300-450 nm / min. The resulting bosses had a height of 0.6 μm-0.8 μm and a sidewall tilt angle of 88°-90°. A SiO2 hard mask was used as the template to cover the area outside the JTE region for Mg ion implantation; the implantation energy was 150 keV and the dose was 1.5 × 10⁻⁶. 14 cm -2 and 5×10 13 cm -2 It adopts a two-window horizontal gradient design, with the edge windows extending outward by 35μm-45μm; High-temperature annealing activates Mg ions and N-type buried layers; annealing parameters: temperature 1250℃, time 30min, pressure atmospheric pressure, protective gas nitrogen with a flow rate of 5L / min, heating rate 25℃ / min, cooling rate 15℃ / min. The SiO2 hard mask was removed using the HF wet method, and the electrode was deposited by electron beam evaporation. The removal parameters were: HF solution concentration of 5% and immersion time of 60s. TiN, Ni, and Au were deposited sequentially to form a contact layer, followed by annealing to form a stable contact layer. The annealing parameters were: temperature 400℃, annealing time 30s, protective gas nitrogen with a flow rate of 5L / min. The thickness of TiN was 10nm, the thickness of Ni was 80nm-100nm, and the thickness of Au was 500nm-800nm. Ti, Al and Ni are evaporated, then Al is covered and annealed to form a low-resistance ohmic contact. The annealing parameters are: temperature 500℃, annealing time: 30s, protective gas is nitrogen, flow rate is 5L / min. Evaporation of Ti, Ni, and Au followed by annealing yields a Schottky diode.

8. The method for fabricating a low-leakage Schottky diode according to claim 7, characterized in that, The preparation method further includes: The device edge is formed by single ICP dry etching at an angle of 30°-40°, and the etching depth penetrates the second N-type GaN layer to the sidewall of the boss.

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