Programming pulse modification

Abstract

Aspects of the present disclosure configure a system component, such as a memory subsystem controller, to modify pulses used to program the memory component. The controller receives a request to program data in individual memory components of a set of memory components. The controller calculates a plurality of memory reliability criteria associated with the individual memory components, and compares the plurality of memory reliability criteria to one or more thresholds. The controller selects a programming pulse to program the data to the individual memory components based on a result of comparing the plurality of memory reliability criteria to the one or more thresholds.

Description

[0001] Priority application

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 440,633, filed on January 23, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly to managing programming pulses when writing data in a memory subsystem. Background Art

[0004] The memory subsystem may be a storage system, such as a solid-state drive (SSD), and may include one or more memory components that store data. Memory components may, for example, be non-volatile memory components and volatile memory components. Generally speaking, a host system may utilize the memory subsystem to store data in the memory components and retrieve data from the memory components. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments of the present disclosure.

[0006] Figure 1 is a block diagram illustrating an example computing environment including a memory subsystem according to some embodiments of the present disclosure.

[0007] Figure 2 A block diagram of an example programming pulse selection module according to some embodiments of the present disclosure.

[0008] Figure 3 A list of different read levels, check fail bit (CFBit) count values, and check fail byte (CFByte) count values ​​for associated valley centers (CoV) according to some embodiments of the present disclosure is presented.

[0009] Figure 4 An example programming pulse selection lookup table is presented according to some embodiments of the present disclosure.

[0010] Figure 5 and 6 Flowchart of an example method for performing dynamic programming pulse selection according to some embodiments of the present disclosure.

[0011] Figure 7 The block diagram is a pictorial representation of a machine in the form of a computer system within which a set of instructions may be executed, causing the machine to perform any one or more of the methodologies discussed herein, in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] Aspects of the present disclosure configure a system component, such as a memory subsystem controller, to write or program data to one or more memory components using different programming pulses (e.g., programming pulses having different voltage levels) based on a combination of multiple criteria. Data can be written to the memory components at different levels, each associated with a different programming voltage. The speed at which data is written to the memory can vary based on the strength of the programming pulses used to program the data. Over time, certain memory components experience different read errors and different reliability metrics. To ensure that data is written to the memory quickly and consistently with a certain reliability level, the disclosed controller varies the value or strength of the programming pulses based on a combination of criteria. Specifically, the controller can determine any combination of the program-erase cycle (PEC) count, the read bit error rate (RBER) value, the number of disabled cells generated after initial programming, and / or one or more check-failed cell count values ​​associated with an individual memory component and use this combination as the basis for selecting the strength of the programming pulses used to store data to the individual memory components. In this way, the speed at which data is written to the memory subsystem can be optimized to reduce errors (read or write errors), thereby improving the overall functionality of the memory subsystem.

[0013] The memory subsystem may be a memory device, a memory module, or a combination of a memory device and a memory module. Figure 1 Examples of storage devices and memory modules are described. Typically, a host system may utilize a memory subsystem that includes one or more memory components, such as a memory device that stores data. The host system may send access requests (e.g., write commands, read commands, sequential write commands, sequential read commands) to the memory subsystem to store data in the memory subsystem and read data from the memory subsystem. Data specified by the host is hereinafter referred to as "host data" or "user data."

[0014] The memory subsystem may initiate media management operations, such as write operations, on host data stored on the memory device. For example, the memory subsystem's firmware may rewrite previously written host data from a location on the memory device to a new location as part of a garbage collection management operation. Data that is rewritten, such as by firmware, is hereinafter referred to as "garbage-collected data."

[0015] "User data" may include host data and garbage collection data. "System data," hereinafter, refers to data generated and / or maintained by the memory subsystem for performing operations in response to host requests and for media management. Examples of system data include, but are not limited to, system tables (e.g., logical-to-physical address mapping tables), data from logs, scratch pad data, and the like.

[0016] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die may include one or more planes. Each logical block address (LBA) of the memory device includes a group of pages. Each page includes a group of memory cells that store data bits. The memory device may be a raw memory device (e.g., NAND), which is managed externally, for example, by an external controller. The memory device may also be a managed memory device (e.g., managed NAND), which is a raw memory device combined with a local embedded controller for memory management within the same memory device package.

[0017] Conventional memory subsystems program data in memory cells by applying one or more programming pulses. Depending on the intensity or voltage level of the programming pulses, the data can be programmed faster. That is, stronger programming pulses can result in faster data programming and storage of data in memory cells. However, if the programming pulses are too strong or the applied voltage level is too high, the data programmed in a given cell at a given level can cause some charge to be shifted to adjacent levels. This leads to the introduction of read errors or programming errors. This is particularly true when the reliability or age of the memory cell degrades. For example, a memory cell with a program-erase cycle exceeding a certain threshold may have poor performance and reliability, which means that applying a pulse that is too strong can cause charge to be shifted to adjacent cells. Strong programming pulses also typically cause more stress on the cell, which degrades reliability.

[0018] In some cases, data may be stored and represented at different read levels within a memory subsystem. Specifically, in a triple-level cell (TLC) memory device, data may be stored at one of eight different read levels within the memory subsystem. The charge stored at each read level can be read and interpreted as a set of three bits. Ideally, data is read by applying a read level within a valley center (CoV), which defines the range of voltage levels that can be applied to accurately read data from each of the eight different read levels. In some cases, the charge stored at one of the read levels may be lost or shifted back and forth due to applying a programming pulse that is too strong or too weak. This leads to inaccuracies when reading at a predetermined read level, or even within a previously calculated CoV. These operations can result in abnormal firmware or controller behavior and abnormal memory component behavior. Furthermore, operating these conventional memory systems is inefficient because data may need to be programmed and / or read multiple times.

[0019] Typical memory systems employ lookup tables that map different PEC counts to different programming pulse values. By using a lookup table, different programming pulse values ​​can be applied to the storage of data based on the age or PEC count of the memory component into which the data is being stored. This can address some of the issues that arise and dynamically adjust the speed at which data is stored based on the PEC count of the memory system. While these approaches generally work well, there are several other factors that can affect the overall performance and speed of a memory system. Namely, relying on a single criterion (e.g., PEC count) to control the speed at which data is programmed can result in erratic behavior and potentially cause data to be stored slower than necessary. This is because, while the PEC count may be higher, the reliability of the memory cell may still be higher, and the memory cell may be able to tolerate larger-than-expected programming pulses. Consequently, lookup table-based approaches can result in poor write latency.

[0020] Aspects of the present disclosure address the above and other deficiencies by configuring a system component, such as a memory subsystem controller of a memory subsystem, to dynamically select the value of a programming pulse used to program data into a memory component. The programming pulse is selected based on multiple criteria, such as a PEC count, a disabled cell count, a number of disabled cells after the first programming cycle, which may be a good indicator of programming speed, a read bit error rate (RBER), a CFBit / CFByte count value, and / or any other condition, criterion, or factor indicative of and representative of the reliability of the memory component. Specifically, the disclosed controller receives a request to program data in an individual memory component of a group of memory components. The controller calculates multiple memory reliability criteria associated with the individual memory component and compares the multiple memory reliability criteria to one or more threshold values. The controller selects a programming pulse to program data into the individual memory component based on the results of comparing the multiple memory reliability criteria to the one or more threshold values.

[0021] In some examples, the plurality of memory reliability criteria include an average program erase count (PEC) value and at least one additional metric. In some examples, the at least one additional metric includes an RBER value. In some examples, the at least one additional metric includes a number of disabled cells generated after initial programming of an individual memory component. In some examples, disabled cells represent cells that have been improperly programmed, and the number of disabled cells is determined during a verify phase of a memory programming operation. In some examples, the at least one additional metric includes one or more check fail cell count values, including at least one of one or more check fail bit (CFBit) count values ​​or one or more check fail byte (CFByte) count values. As referred to herein, a CFByte count value corresponds to eight or more CFBit count values.

[0022] In some examples, the controller calculates one or more check fail cell count values ​​corresponding to individual read levels of individual memory components and compares the one or more check fail cell count values ​​with a threshold value of the one or more threshold values.

[0023] In some examples, the controller selects a first value for the programming pulse in response to determining that the one or more fail check cell count values ​​fail to exceed a threshold. The controller selects a second value for the programming pulse in response to determining that the one or more fail check cell count values ​​exceed a threshold.

[0024] In some examples, the controller retrieves a PEC count value corresponding to an individual memory component and compares the PEC count value corresponding to the individual memory component to an additional threshold value of the one or more threshold values. The controller selects a value for the programming pulse based on a first result of comparing the one or more check fail cell count values ​​to the threshold value and a second result of comparing the PEC count value corresponding to the individual memory component to the additional threshold value.

[0025] In some examples, the controller accesses a predetermined check fail cell count value associated with each read level. The controller calculates a threshold value as a function of the predetermined check fail cell count value. In some examples, the programming pulse includes a trimset voltage value.

[0026] In some examples, the controller stores a lookup table that maps a plurality of programming pulse values ​​to corresponding combinations of the plurality of memory reliability criteria. In some examples, the plurality of memory reliability criteria includes a number of disabled cells generated after initial programming of the individual memory components and one or more check failed cell count values.

[0027] In some examples, the controller calculates the one or more failed check cell count values ​​corresponding to the individual read levels of the individual memory components and compares the one or more failed check cell count values ​​with a threshold value among the one or more threshold values. The controller calculates the number of disabled cells corresponding to the individual memory components and compares the number of disabled cells with an additional threshold value among the one or more threshold values.

[0028] In some examples, the controller selects a value for the programming pulse based on a first result of comparing the one or more fail check cell count values ​​to a threshold value and a second result of comparing the number of disabled cells to an additional threshold value. In some examples, the controller selects a value for the programming pulse based on comparing the number of disabled cells associated with a respective memory component and the one or more fail check cell count values ​​associated with a respective read level of the respective memory component.

[0029] Although various embodiments are described herein as being implemented with respect to a memory subsystem (e.g., a memory subsystem's controller, memory components, a media controller, or a combination thereof), some or all of portions of the embodiments may be implemented with respect to a host system (e.g., a software application, an operating system of the host system), or implemented solely by a media controller instead of or in addition to a memory subsystem controller.

[0030] Figure 1 An example computing environment 100 including a memory subsystem 110 is shown, according to some examples of the present disclosure. Memory subsystem 110 may include media, such as memory components 112A through 112N (hereinafter also referred to as "memory devices"). Memory components 112A through 112N may be volatile memory devices, non-volatile memory devices, or a combination of such devices. In some embodiments, memory subsystem 110 is a storage system. Memory subsystem 110 may be a storage device, a memory module, or a hybrid of storage devices and memory modules. Examples of storage devices include SSDs, flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0031] The computing environment 100 may include a host system 120 coupled to a memory system. The memory system may include one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., with no intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0032] Host system 120 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes memory and processing devices. Host system 120 may include or be coupled to memory subsystem 110 so that host system 120 can read data from or write data to memory subsystem 110. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a USB interface, a Fibre Channel interface, a Serial Attached SCSI (SAS) interface, and the like. The physical host interface may be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may additionally access memory components 112A-112N using an NVM Express (NVMe) interface. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 .

[0033] Memory components 112A-112N may include any combination of different types of nonvolatile memory components and / or volatile memory components. An example of a nonvolatile memory component includes NAND-type flash memory. Each of memory components 112A-112N may include one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., TLC or quad-level cells (QLC)). In some embodiments, a particular memory component 112 may include both SLC and MLC portions of memory cells. Each of the memory cells may store one or more bits of data (e.g., a page and / or block) for use by the host system 120.

[0034] Although non-volatile memory components such as NAND-type flash memory are described, memory components 112A-112N can be based on any other type of memory, such as volatile memory. In some embodiments, memory components 112A-112N can be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), or non-NOR flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory cells can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without previously erasing the non-volatile memory cells. Furthermore, the memory cells of memory components 112A-112N may be grouped into memory pages or LBAs, which may refer to units of memory component 112 for storing data. In some examples, the memory cells of memory components 112A-112N may be grouped into a set of different zones of equal or unequal size for storing data for corresponding applications. In such cases, each application may store data in an associated zone in the set of different zones.

[0035] The memory subsystem controller 115 can communicate with the memory components 112A-112N to perform operations such as reading, writing, or erasing data, and other such operations, at the memory components 112A-112N. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor. The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. In some embodiments, the local memory 119 may include memory registers that store memory pointers, fetched data, and the like. Local memory 119 may also include ROM for storing microcode. Figure 1The example memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or a processor 117 or controller separate from the memory subsystem 110).

[0036] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120 and convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A to 112N. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and ECC operations, decoding operations, encryption operations, cache operations, address translation between logical block addresses associated with the memory components 112A to 112N and physical block addresses, and address translation between application identifiers received from the host system 120 and corresponding areas in a set of areas of the memory components 112A to 112N. This can be used to restrict applications to reading and writing data only to corresponding areas in a set of areas associated with the respective applications. In such cases, a given application can read and write data only to the associated area, for example, by erasing data stored in the area and writing new data to the area, even if there may be available space elsewhere on the memory components 112A to 112N. The memory subsystem controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system 120 into command instructions to access the memory components 112A-112N, and convert responses associated with the memory components 112A-112N into information for use by the host system 120.

[0037] The memory subsystem 110 may also include additional circuits or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM or other temporary storage location or device) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory components 112A-112N.

[0038] The memory device may be a raw memory device (e.g., NAND), which is externally managed, for example, by an external controller (e.g., memory subsystem controller 115). The memory device may be a managed memory device (e.g., managed NAND), which is a raw memory device combined with a local embedded controller (e.g., a local media controller) for memory management within the same memory device package. Any of the memory components 112A to 112N may include a media controller (e.g., media controller 113A and media controller 113N) that manages the memory cells of the memory component, communicates with the memory subsystem controller 115, and executes memory requests (e.g., reads or writes) received from the memory subsystem controller 115.

[0039] According to some embodiments described herein, memory subsystem 110 includes a program pulse selection module 122 that performs or facilitates selecting a program pulse value (e.g., a voltage value) based on a plurality of memory reliability criteria or conditions associated with one or more memory components 112A-112N. In some embodiments, controller 115 includes at least a portion of program pulse selection module 122. For example, controller 115 may include processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, program pulse selection module 122 is part of host system 120, such as a software application or operating system on host system 120. In some embodiments, program pulse selection module 122 is part of media controller 113A and / or media controller 113N.

[0040] According to some embodiments, program pulse selection module 122 receives a request to program data in an individual memory component from the set of memory components 112A-112N. Program pulse selection module 122 calculates a plurality of memory reliability criteria associated with the individual memory component. Program pulse selection module 122 compares the plurality of memory reliability criteria with one or more thresholds and, based on the results of comparing the plurality of memory reliability criteria with the one or more thresholds, selects a program pulse for programming the data in the individual memory component. For example, program pulse selection module 122 may determine the number of disabled cells associated with the individual memory component at a particular level (e.g., L0 or L1) of the individual memory component in conjunction with a check failed cell count value (e.g., CFByte / CFBit) after an initial or first information cycle is stored in the individual memory component. Based on comparing the number of disabled cells with a first threshold and comparing the CFByte / CFBit at the particular level with a second threshold, program pulse selection module 122 may select a value for the program pulse for programming the data in the individual memory component.

[0041] As mentioned herein, the check fail cell count value represents a count of the total number of bits (in the case of a CFBit count value) and / or the total number of bytes (in the case of a CFByte count value) that are programmed (e.g., have a '0' logic level) or represented by one or more individual read levels of memory components 112A-N. The CFBit count values ​​and CFByte count values ​​may be cumulative such that a read level associated with a higher read voltage has a higher CFBit / CFByte count value than a read level associated with a lower read voltage.

[0042] In some examples, the memory component 112 may generate and assign a total predetermined CFBit / CFByte count value and divide the total predetermined CFBit / CFByte count value by the total number of read levels available for storing data in the memory components 112A-N. For example, the program pulse selection module 122 may store a first predetermined CFBit / CFByte count value representing a first total number of bits / bytes programmable at a first read level (e.g., L0 or L1) among a plurality of read levels, and may store a second predetermined CFBit / CFByte count value representing a second total number of bits / bytes programmable at a second read level (e.g., L2) among the plurality of read levels. The first total number may correspond to the total predetermined CFBit / CFByte count value, and the second total number may correspond to the total predetermined CFBit / CFByte count value minus a value calculated by dividing the total predetermined CFBit / CFByte count value by the total number of read levels. This process may continue until each read level is associated with a predetermined total number of bits / bytes, generating and associating a CFBit / CFByte count value with each read level.

[0043] Program pulse selection module 122 can generate a first threshold value associated with a CFBit count value used to select a programming pulse value for programming data to a respective read level. In some examples, the first threshold value is calculated as a function of a predetermined CFBit count value associated with the respective read level. For example, the first threshold value can correspond to 10%, 20%, or 30% of the corresponding predetermined CFBit count value associated with the respective read level.

[0044] Depending on the embodiment, the programming pulse selection module 122 may include logic (e.g., a set of transient or non-transitory machine instructions, such as firmware) or one or more components that cause the memory subsystem 110 (e.g., the memory subsystem controller 115) to perform the operations described herein with respect to the programming pulse selection module 122. The programming pulse selection module 122 may include tangible or non-tangible units capable of performing the operations described herein. Additional details regarding the operation of the programming pulse selection module 122 are described below.

[0045] Figure 2 FIG. 2 is a block diagram of an example programming pulse selection module 200 according to some embodiments of the present disclosure. As shown, the programming pulse selection module 200 includes a memory reliability criteria module 220 and a pulse selection module 230. For some embodiments, the programming pulse selection module 200 may differ from FIG. 2 in terms of components or arrangements. Figure 2 As shown (eg, fewer or more components). The program pulse selection module 200 may be implemented by the memory subsystem controller 115 and / or by one or more of the media controllers 113A-N.

[0046] Program pulse selection module 200 can be used to set a program pulse value for programming data in an individual memory component when a request to write or program data to the individual memory component is received. In these cases, program pulse selection module 200 can calculate a first memory reliability criterion for the individual memory component (e.g., checking the number of failed cell count values). In some cases, program pulse selection module 200 can perform the disclosed operations as a background process without receiving a request to write / read data from a host or in response to receiving a request to write / read data from a host.

[0047] The programming pulse selection module 200 may also calculate a second memory reliability criterion (e.g., the number of disabled cells after initial programming or the current PEC count value). The programming pulse selection module 200 then compares the first memory reliability criterion and the second memory reliability criterion to respective thresholds. The programming pulse selection module 200 selects a value for the programming pulse based on whether one or both of the first memory reliability criterion and the second memory reliability criterion exceed respective thresholds. In some cases, the programming pulse selection module 200 selects a first value if the first memory reliability criterion exceeds a first threshold, selects a second value if the first memory reliability criterion falls between the first and second thresholds, and selects a third value if the first memory reliability criterion is greater than the second threshold.

[0048] For example, if Figure 3In the illustrated distribution 300 of CFBits / CFBytes, the memory component 112 can store data in one of eight different levels (L1-L8). Each of the different levels can be read by applying a different read threshold voltage (read level). For example, data stored in the first level 310 can be read by applying a first read level range, data stored in the second level 312 can be read by applying a second read level range, data stored in the third level 314 can be read by applying a third read level range, and data stored in the fourth level 316 can be read by applying a fourth read level range. Ideally, the read level applied to optimally and most efficiently read data from a particular level is defined by a CoV, such as a first CoV 320, a second CoV 322, a third CoV 324, a fourth CoV 326, and a fifth CoV 328.

[0049] To enable the program pulse selection module 200 to select a program pulse value for programming data in a given level of an individual memory component, the memory component 112 stores or generates an ideal or predetermined CFBit / CFByte count value for each level. For example, a first CoV 320 may be associated with a first CFBit count (e.g., 7000), a second CoV 322 may be associated with a second CFBit count (e.g., 6000), and a third CoV 324 may be associated with a third CFBit count (e.g., 5000). A fourth CoV 326 may correspond to a CFBit count of 2000 and a CFByte count of 250, and a fifth CoV 328 may correspond to a CFBit count of 1000 and a CFByte count of 125. These are illustrative, and example quantities and CFBit and CFByte values ​​may be calculated and set to numbers different from these disclosed numbers. It can be seen that the CFBit count differs by a predetermined number between each corresponding CoV read. Using this information, the memory reliability criteria module 220 can determine and identify whether the current check fail count value for a given tier exceeds a threshold value to select an appropriate programming pulse value for programming data in the individual memory components.

[0050] For example, if Figure 4As shown, the pulse selection module 230 stores a lookup table 400 that maps different memory reliability criteria to corresponding different programming pulse values ​​and / or offsets. Specifically, the lookup table 400 stores a plurality of criteria 410 corresponding to corresponding thresholds 420 and programming pulse values ​​and / or offsets 430. The memory reliability criteria module 220 can receive a request from a host to program data into a particular memory component. In response, the memory reliability criteria module 220 communicates with the pulse selection module 230 to obtain a list of criteria 410 stored in the lookup table 400. The memory reliability criteria module 220 calculates a memory reliability value for each criterion corresponding to the particular memory component and obtains the corresponding threshold 420 from the pulse selection module 230. The memory reliability criteria module 220 can then determine whether one or more of the memory reliability values ​​exceeds a threshold. Based on this determination, the memory reliability criteria module 220 obtains the corresponding programming pulse value and / or offset from the pulse selection module 230 for programming the data into the particular memory component.

[0051] In some examples, the criteria 410 includes a first criteria combination 412. The first criteria combination 412 includes a first condition set 422 having a particular memory reliability threshold. In some cases, the first condition set 422 includes a first memory reliability criterion including a first average PEC boundary or threshold and a second memory reliability criterion including a first RBER boundary or threshold. The memory reliability criteria module 220 then retrieves and / or calculates the current RBER value associated with the individual memory components. The memory reliability criteria module 220 also retrieves and / or calculates the first RBER boundary or value for the individual memory components.

[0052] The memory reliability criteria module 220 compares the current average PEC count value to a first average PEC boundary or threshold. The memory reliability criteria module 220 also compares the current RBER value to the first RBER boundary or threshold. The memory reliability criteria module 220 determines either or both of the following: the current average PEC count value exceeds the first average PEC boundary or threshold, and / or the current RBER value exceeds the first RBER boundary or threshold. In response to determining either or both of the current average PEC count value exceeds the first average PEC boundary or threshold and / or the current RBER value fails to exceed the first RBER boundary or threshold, the memory reliability criteria module 220 retrieves a trimming set 432 associated with the first criteria combination 412 for use as a programming pulse for programming data to the individual memory components. In response to determining either or both of the current average PEC count value exceeds the first average PEC boundary or threshold and / or the current RBER value exceeds the first RBER boundary or threshold, the memory reliability criteria module 220 accesses a second average PEC boundary or threshold and a second RBER boundary or threshold corresponding to the second criteria combination. In response to determining that either or both of the current average PEC count value fails to exceed the second average PEC boundary or threshold and / or the current RBER value fails to exceed the second RBER boundary or threshold, the memory reliability criteria module 220 retrieves a trimming set associated with the second criteria combination to use as a programming pulse for programming data to the individual memory components.

[0053] In some cases, the memory reliability criteria module 220 may also consider the CFByte / CFBit value associated with the first level of an individual memory component, instead of or in addition to the RBER boundary or threshold. In some cases, the memory reliability criteria module 220 may also consider the number of disabled bits resulting from the initial programming of an individual memory component, instead of or in addition to the RBER boundary or threshold. For example, the memory reliability criteria module 220 may first or initially program the individual memory component (e.g., after the individual memory component is powered on and / or after the individual memory component is erased). After programming the individual memory component, the memory reliability criteria module 220 may perform a verification operation to count the number of improperly or erroneously programmed bits. The number of these bits is stored as the number of disabled bits resulting from the initial programming of the individual memory component.

[0054] The memory reliability criteria module 220 may compare the number of disabled bits to a first threshold. If the number of disabled bits does not exceed the first threshold, the memory reliability criteria module 220 may use a first value for a programming pulse used to program data to the individual memory component. If the number of disabled bits exceeds the first threshold, the memory reliability criteria module 220 may compare the number of disabled bits to a second threshold. If the number of disabled bits does not exceed the second threshold, the memory reliability criteria module 220 may use a second value for a programming pulse used to program data to the individual memory component. In some cases, the memory reliability criteria module 220 compares the number of disabled bits to the CFBit / CFByte of the first level of the individual memory component. The memory reliability criteria module 220 may select a programming pulse value based on whether the number of disabled bits exceeds the CFBit / CFByte of the first level of the individual memory component.

[0055] Figure 5 Flowchart of an example method 500 for performing programming pulse selection according to some embodiments of the present disclosure. The method 500 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 may be performed by a processor (e.g., a processor, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), a processor (e.g., a processor, circuitry, programmable logic, microcode, hardware of a device, integrated circuit, etc.), a processor (e.g., a processor, circuitry, programmable logic, microcode, microcode, hardware of a device, integrated circuit, etc.), a processor (e.g., a processor, circuitry, programmable logic, programmable logic, microcode, microcode, hardware of a device, integrated circuit, etc.), a processor (e.g., a processor, circuitry, programmable logic, programmable logic, microcode, microcode, programmable logic ... Figure 1 The memory subsystem controller 115 of the embodiment of the present invention performs method 500. In these embodiments, method 500 may be performed at least in part by the program pulse selection module 122. Although the processes are shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0056] Reference Figure 5 , method (or process) 500 begins at operation 505, where a processing device of the memory subsystem (e.g., a processor of the memory subsystem controller 115) receives a request to program data in an individual memory component in the set of memory components. In some cases, method 500 begins at operation 510, where the operation is performed in the background, independent of any host read / write requests being received. In these cases, operation 505 can be skipped.

[0057] At operation 510, the processing device of the memory subsystem calculates a plurality of memory reliability criteria associated with individual memory components in response to detecting a read error at operation 505. Subsequently, the processing device of the memory subsystem compares the plurality of memory reliability criteria with one or more thresholds at operation 515 and selects a programming pulse to program data to the individual memory components based on the results of comparing the plurality of memory reliability criteria with the one or more thresholds at operation 520.

[0058] Figure 6 Flowchart of an example method 600 for performing programming pulse selection according to some embodiments of the present disclosure. The method 600 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 600 may be performed by a processor that is configured to execute a program pulse selection. Figure 1 The memory subsystem controller 115 of the embodiment of the present invention performs method 600. In these embodiments, method 600 may be performed at least in part by the program pulse selection module 122. Although the processes are shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0059] Reference Figure 6Method (or process) 600 begins at operation 610, where a processing device of the memory subsystem (e.g., a processor of the memory subsystem controller 115) powers on the memory subsystem 110. Subsequently, at operation 620, for example, in response to receiving a request to program data to an individual memory component, the memory subsystem controller 115 obtains a plurality of memory reliability criteria. For example, the memory subsystem controller 115 obtains an average PEC count for all memory components of the memory subsystem 110 and / or an average PEC count for an individual memory component. The memory subsystem controller 115 also checks the RBER of the individual memory component. At operation 630, based on comparing the average PEC count and / or the RBER to one or more thresholds, the memory subsystem controller 115 determines whether the value exceeds the threshold. For example, the memory subsystem controller 115 checks whether the number of disabled cells after initial programming of the individual memory component and / or the CFBit / CFByte of the lowest, middle, or highest level of multiple levels of the individual memory component exceeds the corresponding threshold. At operation 640, if one or more of the values ​​exceed the threshold, the memory subsystem controller 115 updates the current programming pulse value (e.g., trimming set) used to program data to the individual memory components, for example, by reducing the voltage value. Otherwise, at operation 650, if one or more of the values ​​fail to exceed the threshold, the memory subsystem controller 115 maintains the current programming pulse value (e.g., trimming set). Subsequently, at operation 660, the memory subsystem controller 115 programs the data to the individual memory components using the current programming pulse value (e.g., using the updated or previously set value).

[0060] In view of the above disclosure, various examples are described below. It should be noted that one or more features of the examples taken independently or in combination should be considered to be within the disclosure of this application.

[0061] Example 1. A system comprising: a set of memory components; and a processing device operatively coupled to the set of memory components, the processing device configured to perform operations comprising: receiving a request to program data in an individual memory component in the set of memory components; calculating a plurality of memory reliability criteria associated with the individual memory component; comparing the plurality of memory reliability criteria to one or more thresholds; and selecting a programming pulse to program the data to the individual memory component based on a result of comparing the plurality of memory reliability criteria to the one or more thresholds.

[0062] Example 2. The system of example 1, wherein the plurality of memory reliability criteria includes an average program erase count (PEC) value and at least one additional metric.

[0063] Example 3. The system of example 2, wherein the at least one additional metric comprises a read bit error rate (RBER) value.

[0064] Example 4. The system of any of examples 2-3, wherein the at least one additional metric comprises a number of disabled cells generated after initial programming of the individual memory components.

[0065] Example 5. The system of example 4, wherein the disabled cells represent cells that have been improperly programmed, the number of disabled cells being determined during a verify phase of a memory programming operation.

[0066] Example 6. The system of any of Examples 2 to 5, wherein the at least one additional metric comprises one or more check fail unit count values, the one or more check fail unit count values ​​comprising at least one of one or more check fail bit (CFBit) count values ​​or one or more check fail byte (CFByte) count values.

[0067] Example 7. The system of example 6, the operations further comprising: calculating one or more failed check cell count values ​​corresponding to individual read levels of the individual memory components; and comparing the one or more failed check cell count values ​​to a threshold value of the one or more threshold values.

[0068] Example 8. The system of Example 7, wherein the operations further include: selecting a first value for the programming pulse in response to determining that the one or more failed check cell count values ​​fail to exceed the threshold; and selecting a second value for the programming pulse in response to determining that the one or more failed check cell count values ​​exceed the threshold.

[0069] Example 9. The system of any of Examples 7-8, wherein the operations further comprise: retrieving the PEC count value corresponding to the individual memory component; comparing the PEC count value corresponding to the individual memory component to an additional threshold value of the one or more threshold values; and selecting a value for the programming pulse based on a first result of comparing the one or more check fail cell count values ​​to the threshold value and a second result of comparing the PEC count value corresponding to the individual memory component to the additional threshold value.

[0070] Example 10. The system of any of examples 7 to 9, the operations further comprising: accessing a predetermined check fail cell count value associated with the individual read tier; and calculating the threshold value as a function of the predetermined check fail cell count value.

[0071] Example 11. The system of any of Examples 1 to 10, wherein the programming pulse comprises a trim set voltage value.

[0072] Example 12. The system of any of Examples 1 to 10, the operations further comprising storing a lookup table that maps a plurality of programming pulse values ​​to corresponding combinations of the plurality of memory reliability criteria.

[0073] Example 13. The system of any of Examples 1 to 12, wherein the plurality of memory reliability criteria includes a number of disabled cells generated after initial programming of the individual memory components and one or more failed check cell count values.

[0074] Example 14. The system of example 13, wherein the operations further comprise: calculating the one or more check failed cell count values ​​corresponding to the individual read levels of the individual memory components; comparing the one or more check failed cell count values ​​with a threshold value among the one or more threshold values; calculating the number of disabled cells corresponding to the individual memory components; and comparing the number of disabled cells with an additional threshold value among the one or more threshold values.

[0075] Example 15. The system of Example 14, the operations further comprising selecting a value for the programming pulse based on a first result of comparing the one or more check fail cell count values ​​to the threshold and a second result of comparing the number of disabled cells to the additional threshold.

[0076] Example 16. The system of any of Examples 13 to 15, the operations further comprising selecting a value for the programming pulse based on comparing the number of disabled cells associated with the individual memory component and the one or more fail check cell count values ​​associated with an individual read level of the individual memory component.

[0077] Methods and computer-readable storage media having instructions for performing any of the above examples.

[0078] Figure 7 An example machine is shown in the form of a computer system 700 within which a set of instructions may be executed for causing the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 700 may correspond to a host system (e.g., Figure 1 host system 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, to execute the operating system to execute the corresponding Figure 1In some embodiments, the machine may be connected (e.g., using a network) to other machines in a local area network (LAN), an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0079] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a network switch or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0080] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., ROM, flash memory, DRAM such as SDRAM or RDRAM, etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718 that communicate with each other via a bus 730.

[0081] Processing device 702 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, processing device 702 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing another instruction set, or a processor implementing a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as an ASIC, an FPGA, a digital signal processor (DSP), a network processor, or the like. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communicating over a network 720.

[0082] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. During execution of the instructions by the computer system 700, the instructions 726 may also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702, with the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may correspond to Figure 1 Memory subsystem 110.

[0083] In one embodiment, instructions 726 include functionality to implement corresponding region-based decoding (e.g., Figure 1 122 ). Although the machine-readable storage medium 724 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0084] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts can most effectively convey the substance of their work to others skilled in the art. Herein, and generally, an algorithm is conceived to be a self-consistent sequence of operations that produces a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0085] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the computer system's registers and memories and transforms it into other data represented in a similar manner as physical quantities within the computer system's memories or registers or other such information storage systems.

[0086] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks); ROM; RAM; erasable programmable read-only memory (EPROM); EEPROM; magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0087] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized devices for performing the methods described. The structures for various such systems will be presented as described above. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0088] The present disclosure may be provided in the form of a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform processes according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium, such as ROM, RAM, magnetic disk storage media, optical storage media, flash memory components, and the like.

[0089] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: a set of memory components; as well as a processing device operatively coupled to the set of memory components, the processing device configured to perform operations comprising: calculating a plurality of memory reliability criteria associated with individual memory components in the set of memory components; comparing the plurality of memory reliability criteria to one or more thresholds; as well as Program pulses used to program data to the individual memory components are selected based on the results of comparing the plurality of memory reliability criteria to the one or more thresholds.

2. The system of claim 1 , the operations comprising receiving a request to program the data in the individual memory component in the set of memory components, wherein the plurality of memory reliability criteria comprises an average program erase count (PEC) value and at least one additional metric.

3. The system of claim 2, wherein the at least one additional metric comprises a read bit error rate (RBER) value.

4. The system of claim 2, wherein the at least one additional metric comprises a number of disabled cells generated after initial programming of the individual memory components.

5. The system of claim 4, wherein the disabled cells represent cells that have been improperly programmed, the number of disabled cells being determined in a verify phase of a memory programming operation.

6. The system of claim 2, wherein the at least one additional metric comprises one or more check fail unit count values, the one or more check fail unit count values ​​comprising at least one of one or more check fail bit (CFBit) count values ​​or one or more check fail byte (CFByte) count values.

7. The system of claim 6, wherein the operations comprise: calculating one or more check fail cell count values ​​corresponding to respective read levels of the respective memory components; as well as The one or more inspection failed unit count values ​​are compared with a threshold value among the one or more threshold values.

8. The system of claim 7, wherein the operations comprise: selecting a first value for the programming pulse in response to determining that the one or more fail check cell count values ​​fail to exceed the threshold; as well as A second value for the programming pulse is selected in response to determining that the one or more fail check cell count values ​​exceed the threshold.

9. The system of claim 7, wherein the operations comprise: retrieving the PEC count value corresponding to the individual memory component; comparing the PEC count value corresponding to the individual memory component to an additional threshold value of the one or more threshold values; as well as A value for the programming pulse is selected based on a first result of comparing the one or more fail check cell count values ​​to the threshold and a second result of comparing the PEC count value corresponding to the individual memory component to the additional threshold.

10. The system of claim 7, wherein the operations comprise: accessing a predetermined check failed cell count value associated with the individual read level; as well as The threshold value is calculated as a function of the predetermined inspection failed cell count value.

11. The system of claim 1 , wherein the programming pulse comprises a trim set voltage value.

12. The system of claim 1, wherein the operations comprise: A lookup table is stored that maps a plurality of programming pulse values ​​to corresponding combinations of the plurality of memory reliability criteria.

13. The system of claim 1, wherein the plurality of memory reliability criteria include a number of disabled cells and one or more check fail cell count values ​​generated after initial programming of the individual memory components.

14. The system of claim 13, wherein the operations comprise: calculating the one or more check fail cell count values ​​corresponding to respective read levels of the respective memory components; comparing the one or more inspection failed unit count values ​​with a threshold value among the one or more threshold values; calculating the number of the disabled cells corresponding to the individual memory components; and The number of disabled cells is compared to an additional threshold value of the one or more threshold values.

15. The system of claim 14, wherein the operations comprise: A value for the programming pulse is selected based on a first result of comparing the one or more fail check cell count values ​​to the threshold and a second result of comparing the number of disabled cells to the additional threshold.

16. The system of claim 13, the operations comprising selecting a value for the programming pulse based on comparing the number of the disabled cells associated with the individual memory component and the one or more fail check cell count values ​​associated with an individual read level of the individual memory component.

17. A method comprising: calculating a plurality of memory reliability criteria associated with individual memory components; comparing the plurality of memory reliability criteria to one or more thresholds; as well as Program pulses used to program data to the individual memory components are selected based on the results of comparing the plurality of memory reliability criteria to the one or more thresholds.

18. The method of claim 17, wherein the plurality of memory reliability criteria comprises an average program erase count (PEC) value and at least one additional metric.

19. The method of claim 18, wherein the at least one additional metric comprises a read bit error rate (RBER) value.

20. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: calculating a plurality of memory reliability criteria associated with individual memory components; comparing the plurality of memory reliability criteria to one or more thresholds; as well as Program pulses used to program data to the individual memory components are selected based on the results of comparing the plurality of memory reliability criteria to the one or more thresholds.

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