Low-power-consumption control method and system for fuze chip
Through the low-power control method of the fuze chip, by accurately detecting the module status and switching between multi-level power consumption modes, the problems of system hang and wake-up failure in the low-power design of the fuze chip are solved, and stable operation and low power consumption are achieved.
Patent Information
- Application Number
- CN202510623533.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-15
- Publication Date
- 2025-09-05
AI Technical Summary
Existing fuze chips have problems with system hangs, wake-up failures, and insufficient reliability in their low-power designs. In particular, they fail to effectively save status and verify before the functional modules turn off their clocks, causing the chips to operate unstable in extreme environments.
Through accurate detection of the idle state of functional modules, delay protection and status verification before clock shutdown, and dynamic switching of multi-level power consumption modes, data preservation and status synchronization are ensured to avoid system failures caused by sudden interruption of clock signals.
It achieves stable operation of functional modules in a low-power state, avoids data loss and module status disorder, improves system reliability, and reduces power consumption by 30%-50%, while ensuring real-time response of core functions.
Smart Images
Figure CN120595655A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of low-power consumption control of integrated circuits, and in particular to a low-power consumption control method and system for a fuze chip. Background Art
[0002] With the advancement of integrated circuit technology, the functional complexity and integration of fuze chips are increasing, making power consumption management a key challenge. Traditional low-power designs often dynamically shut down functional module clocks or power supplies to reduce power consumption, such as through clock gating or dynamic voltage and frequency scaling (DVFS). However, as core components of high-reliability systems, fuze chips require their functional modules (such as sensor interfaces, communication modules, and security algorithm units) to operate stably in extreme environments. Directly shutting down the clocks of these functional modules may lead to the following problems:
[0003] System hang or status error: If the clock of a functional module is suddenly turned off during task execution, its internal cache data or status register may be lost or disordered due to incomplete operation, causing the entire chip system to hang or logic error;
[0004] Wake-up recovery failure: When reactivating functional modules using traditional methods, unstable clock signals or improperly initialized module states may result in failure to resume normal operation after wake-up, affecting the real-time response of tasks.
[0005] Insufficient reliability: Fuze chips often need to work in harsh environments such as strong interference, high and low temperatures. The existing low-power control strategy lacks a protection mechanism for the integrity of the module state, which can easily cause abnormalities due to environmental disturbances.
[0006] Although the existing technology proposes a timer-based low-power mode switching, it does not solve the problem of state preservation and verification before the functional module turns off the clock. Alternatively, it adopts hierarchical power consumption control but does not consider the difference in clock stabilization time of different modules, which may cause functional abnormalities due to premature clock shutdown. Summary of the Invention
[0007] The purpose of the present invention is to provide a low-power consumption control method and system for a fuze chip. By accurately detecting the idle state of the functional module, delay protection and status verification before the clock is shut down, and dynamic switching of multiple power consumption modes, it is ensured that the functional module completes the necessary data storage and status synchronization before entering the low-power consumption state, thereby avoiding system failures caused by sudden interruption of the clock signal, aiming to solve the problems in the prior art.
[0008] The present invention is implemented as follows: a low-power consumption control method for a fuze chip, applied to a chip control device, specifically comprising the following steps:
[0009] S101: detecting the working status of a functional module electrically connected to the fuze chip within a preset period of time, and determining whether the current status of the functional module is in an idle state;
[0010] S102: If the functional module is in the working state, monitor the operating parameters of the functional module, determine whether the operating parameters of the functional module change by a threshold value within a preset period of time, and determine whether the monitoring functional module is in an idle state after the threshold value change;
[0011] S103: If it is determined that the current state of the functional module is in an idle state, keeping the functional clock signal of the functional module running within a preset first time period;
[0012] S104: When no state activation request of the functional module is received within the preset first time period, turning off the function clock signal of the functional module, and the functional module enters a low power consumption state;
[0013] S105: The functional clock signal responds to an external signal wake-up request or an internal wake-up event, activates the functional clock signal of the functional module after receiving the wake-up signal, and restores the normal working state of the functional module.
[0014] Furthermore, in S101, the working status of the functional module electrically connected to the fuze chip is detected within a preset phase time, including:
[0015] Sending an acquisition request to the fuze chip according to a preset time, wherein the acquisition request includes a status acquisition request for the current fuze chip and a status acquisition request for a functional module electrically connected to the fuze chip;
[0016] The current fuze chip status acquisition request acquires the status information of the current fuze chip, and if the current fuze chip is in a working state, identifies the data transmission of the current fuze chip;
[0017] After the identification data is completed, the state of the functional module associated with the current fuze chip is determined, and the first associated module in the current working state is determined;
[0018] It is determined that the second associated module is in an idle state, and the functional clock signal of the second associated module is kept running.
[0019] Furthermore, if the current fuze chip is in a working state, identifying the data transmission of the current fuze chip includes:
[0020] Acquire multiple data recognition models, and sort the recognition contents of the data recognition models according to a priority order set by the system;
[0021] Acquire the transmission data of the fuse chip, and input the transmission data into the data recognition model ranked first.
[0022] Furthermore, in S102, if the functional module is in the working state, the operating parameters of the functional module are monitored to determine whether the operating parameters of the functional module change by a threshold value within a preset stage time, including:
[0023] Determining that the first associated module is in a working state through a status acquisition request of the functional module electrically connected to the fuze chip, and acquiring operating parameters of the first associated module;
[0024] The operating parameters include power supply voltage, operating current and power consumption, and noise coefficient. The current power supply voltage, operating current and power consumption, and noise coefficient data of the first associated module are obtained, and the power supply voltage, operating current and power consumption, and noise coefficient of the first associated module are obtained again within a preset stage time.
[0025] The power supply voltage, operating current and power consumption, and noise factor of the first associated module in the two stages are compared to obtain a parameter comparison difference value, and the parameter comparison difference value is compared with the system preset threshold. If the operating parameters are within the threshold range, the working state is maintained. If the operating parameters are outside the threshold range, the current state of the first associated module is obtained again to determine whether it is in an idle state.
[0026] Furthermore, in S103, the function clock signal of the function module is kept running within a preset first time period, including:
[0027] The first time period is dynamically adjusted according to the clock stabilization time of the functional module or the task response delay requirement;
[0028] Dynamically extend or shorten the first time period based on the measured or preset stabilization time to ensure that sufficient time is reserved for the module to complete pending operations before shutting down the clock;
[0029] The task types that may be triggered in the next cycle in the task queue and their maximum allowed delay thresholds are analyzed. If an upcoming high-priority task is detected that requires a quick response, the first time period is shortened to avoid shutting down the clock too early.
[0030] Furthermore, in S104, before turning off the functional clock signal of the functional module, the following steps are included:
[0031] Performing a state integrity check on the functional module to ensure that its cached data has been saved to the non-volatile storage unit;
[0032] If the check fails, the holding time of the functional clock signal is extended until the check passes, and then the functional clock signal of the functional module is turned off.
[0033] Furthermore, in S104, the functional module enters a low power consumption state, wherein the low power consumption state includes a multi-level power consumption mode, and the multi-level power consumption mode is dynamically switched according to the system load, and different modes correspond to different functional clock shutdown ranges and wake-up response priorities.
[0034] Further, in S105, the functional clock signal responds to an external signal wake-up request or an internal wake-up event, wherein the external wake-up request includes an external interrupt signal, a communication interface instruction or a sensor trigger signal, and the internal wake-up event includes a timer timeout event or an internal task queue activation instruction.
[0035] Compared with the prior art, the low-power consumption control method and system for a fuze chip provided by the present invention have the following beneficial effects:
[0036] 1. Through accurate detection of the functional module's idle state, delay protection and status verification before clock shutdown, and dynamic switching of multi-level power consumption modes, it ensures that the functional module completes necessary data storage and status synchronization before entering the low-power state, avoiding system failures caused by sudden clock signal interruption, while taking into account low power consumption requirements and operational reliability.
[0037] 2. Through dynamic switching of multi-level power modes and state integrity verification, data loss or module state disorder caused by sudden clock shutdown is avoided, fundamentally solving the problem of system hang or wake-up failure in traditional low-power designs. Non-essential modules are shut down step by step according to the criticality of module functions, reducing power consumption by 30%-50% compared to the global switching strategy. At the same time, the real-time response of core functions is guaranteed. In some modes, the reserved modules are operated at reduced frequency to further optimize dynamic power consumption.
[0038] 3. Through the hardware priority encoder and multi-source trigger condition analysis, the conflict between the low-load recommendation to enter deep sleep and the environmental alarm requirement to maintain shallow sleep is resolved, ensuring that the system always prioritizes safety. When verification fails, data writeback and alarms are automatically triggered to avoid cascading failures caused by a single operation error.
[0039] A low-power consumption control system for a fuze chip, applied to the above-mentioned low-power consumption control method, the low-power consumption control system comprising:
[0040] Status detection module, used to monitor the working status of each functional module in real time and generate an idle state flag;
[0041] a clock control module, connected to the state detection module, configured to maintain the functional clock signal of the functional module for a preset first time period when the functional module is in an idle state, and to shut down the functional clock after a timeout, the clock control module including a programmable clock delay unit configured to configure the first time period according to the type of the functional module and supporting dynamic adjustment;
[0042] A wake-up management module, configured to receive an external wake-up request or an internal wake-up event, and send a clock recovery instruction to the clock control module;
[0043] The verification protection module is used to perform data integrity and state consistency verification on the functional module before shutting down the functional clock.
[0044] Furthermore, the wake-up management module includes:
[0045] External interrupt response unit, used to capture external trigger signals;
[0046] Internal event scheduling unit, used to generate wake-up instructions based on timers or task queues;
[0047] Priority arbitration unit, used to handle conflicts among multiple wake-up requests;
[0048] The verification protection module includes:
[0049] A data write-back unit, used to save the cached data of the functional module to the non-volatile memory;
[0050] A state latch unit, used to record the operating parameters of the functional module before it enters a low-power state;
[0051] The exception handling unit is used to trigger an alarm when the verification fails and maintain the functional clock signal. BRIEF DESCRIPTION OF THE DRAWINGS
[0052] Figure 1 This is a schematic flow chart of a low-power consumption control method for a fuze chip proposed in the present invention;
[0053] Figure 2 This is a schematic block diagram of the process of detecting the working status of a functional module electrically connected to the fuze chip within a preset stage time in a low-power consumption control method of the fuze chip proposed by the present invention;
[0054] Figure 3 This is a schematic structural diagram of a low-power control system for a fuze chip proposed in the present invention;
[0055] Figure 4 This is a structural diagram of a verification protection module in a low-power control system of a fuze chip proposed by the present invention. DETAILED DESCRIPTION
[0056] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.
[0057] The implementation of the present invention is described in detail below with reference to specific embodiments.
[0058] The same or similar numbers in the drawings of this embodiment correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "up", "down", "left", "right", etc. indicate directions or positional relationships, they are based on the directions or positional relationships shown in the drawings. This is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.
[0059] Reference Figure 1-2 As shown, a low-power consumption control method for a fuze chip is applied to a chip control device and specifically includes the following steps:
[0060] S101: detecting the working status of the functional module electrically connected to the fuze chip within a preset period of time, and determining whether the current status of the functional module is in an idle state;
[0061] The working status of the functional module electrically connected to the fuze chip is detected within a preset period of time, including:
[0062] Sending an acquisition request to the fuze chip according to a preset time, the acquisition request including a status acquisition request for the current fuze chip and a status acquisition request for a functional module electrically connected to the fuze chip;
[0063] The current fuze chip status acquisition request obtains the current fuze chip status information. If the current fuze chip is in working state, the data transmission of the current fuze chip is identified.
[0064] After the identification data is completed, the state of the functional module associated with the current fuze chip is determined, and the first associated module in the current working state is determined;
[0065] Determine that the second associated module is in an idle state, and keep the functional clock signal of the second associated module running;
[0066] S102: If the functional module is in the working state, monitor the operating parameters of the functional module, determine whether the operating parameters of the functional module have a threshold change within a preset period of time, and determine whether the monitoring functional module is in an idle state after the threshold change;
[0067] If the functional module is in a working state, the operating parameters of the functional module are monitored to determine whether the operating parameters of the functional module have a threshold change within a preset stage time, including:
[0068] Determining that the first associated module is in an operating state through a status acquisition request of a functional module electrically connected to the fuze chip, and acquiring operating parameters of the first associated module;
[0069] The operating parameters include power supply voltage, operating current and power consumption, and noise factor. The current power supply voltage, operating current and power consumption, and noise factor data of the first associated module are obtained, and the power supply voltage, operating current and power consumption, and noise factor of the first associated module are obtained again within a preset phase time.
[0070] Compare the supply voltage, operating current, power consumption, and noise figure of the first associated module in the two phases to obtain a parameter comparison difference value, and compare the parameter comparison difference value with a system preset threshold value. If the operating parameters are within the threshold range, maintain the working state; if the operating parameters are outside the threshold range, obtain again whether the current state of the first associated module is in the idle state;
[0071] S103: If it is determined that the current state of the functional module is in an idle state, keeping the functional clock signal of the functional module running within a preset first time period;
[0072] The method of maintaining the function clock signal of the function module in operation within a preset first time period includes:
[0073] The first time period is dynamically adjusted according to the clock stabilization time of the functional module or the task response delay requirement;
[0074] Dynamically extend or shorten the first time period based on the measured or preset stabilization time to ensure that enough time is reserved for the module to complete pending operations before shutting down the clock;
[0075] Analyze the types of tasks that may be triggered in the next cycle in the task queue and their maximum allowed delay thresholds. If it is detected that an upcoming high-priority task requires a quick response, shorten the first time period to avoid shutting down the clock too early.
[0076] S104: When no state activation request of the functional module is received within a preset first time period, the function clock signal of the functional module is turned off, and the functional module enters a low power consumption state;
[0077] Before turning off the function clock signal of the function module, the following steps are performed:
[0078] Perform status integrity check on functional modules to ensure that their cached data has been saved to non-volatile storage units;
[0079] If the check fails, the hold time of the functional clock signal is extended until the check passes, and then the functional clock signal of the functional module is turned off;
[0080] S105: The functional clock signal responds to an external signal wake-up request or an internal wake-up event, activates the functional clock signal of the functional module after receiving the wake-up signal, and restores the normal working state of the functional module;
[0081] Among them, the functional clock signal responds to an external signal wake-up request or an internal wake-up event, where the external wake-up request includes an external interrupt signal, a communication interface instruction or a sensor trigger signal, and the internal wake-up event includes a timer timeout event or an internal task queue activation instruction. Through precise detection of the idle state of the functional module, delay protection and status verification before the clock is shut down, and dynamic switching of multi-level power consumption modes, it is ensured that the functional module completes the necessary data storage and status synchronization before entering the low-power state, avoiding system failures caused by sudden interruption of the clock signal, while taking into account low power consumption requirements and operational reliability.
[0082] In this embodiment, if the current fuze chip is in an operating state, identifying the data transmission of the current fuze chip includes:
[0083] Obtain multiple data recognition models and sort the recognition contents of the data recognition models according to the priority order set by the system;
[0084] The transmission data of the fuse chip is obtained and input into the data recognition model ranked first.
[0085] In this embodiment, in S104, the functional module enters a low power consumption state, wherein the low power consumption state includes a multi-level power consumption mode, the multi-level power consumption mode is dynamically switched according to the system load, and different modes correspond to different function clock shutdown ranges and wake-up response priorities;
[0086] The multi-level power consumption modes are: full-function mode (Level 0), light sleep mode (Level 1), deep sleep mode (Level 2) and ultra-low power mode (Level 3). Each level corresponds to a different functional module shutdown range, clock frequency adjustment strategy and wake-up response delay. Through dynamic switching of multi-level power consumption modes and state integrity verification, data loss or module state disorder caused by sudden clock shutdown is avoided, fundamentally solving the problems of system hang or wake-up failure in traditional low-power design. Non-essential modules are shut down step by step according to the criticality of module functions. Compared with the global switching strategy, power consumption is reduced by 30%-50%, while ensuring the real-time response of core functions. In some modes, the reserved modules are operated at reduced frequency to further optimize dynamic power consumption.
[0087] This technical solution has the following functions:
[0088] 1. Significantly improve system reliability: Dynamic switching of multi-level power consumption modes and state integrity verification prevent data loss or module state disorder caused by sudden clock shutdown, fundamentally resolving the problems of system hangs or wake-up failures in traditional low-power designs. In extreme environments such as high temperature and high pressure, the system locks into a safe power consumption mode (such as prohibiting entry to Level 3) through adaptive adjustment of environmental parameters to prevent functional abnormalities caused by environmental disturbances.
[0089] 2. Achieve the optimal balance between power consumption and performance: Refined hierarchical control: Non-essential modules are shut down step by step based on their functional criticality (e.g., Level 2 retains communication interfaces but disables data cache). Compared to a global switching strategy, this reduces power consumption by 30%-50% while ensuring real-time responsiveness of core functions. Dynamic frequency adjustment: In some modes, the frequency of retained modules is reduced (e.g., the Level 2 main frequency is reduced to 10MHz), further optimizing dynamic power consumption.
[0090] 3. Enhanced adaptability to complex scenarios: Burst task response: When waking up from Level 3, a hierarchical recovery mechanism (Level 3 → Level 2 → Level 0) balances fast response and stability, shortening task recovery time by 40%. Long-term standby optimization: In storage mode, Level 3 is maintained, with only periodic wake-up self-tests. Standby power consumption can reach nA levels, extending device life.
[0091] 4. Intelligent conflict arbitration and fault tolerance: Through the hardware priority encoder and multi-source trigger condition analysis, it resolves the conflict between the low-load recommendation to enter deep sleep and the environmental alarm requirement to maintain shallow sleep, ensuring that the system always prioritizes safety. When the verification fails, it automatically triggers data writeback and alarms to avoid cascading failures caused by a single operation error.
[0092] 5. Compatibility and Scalability: Supports modular configuration and can flexibly define the parameters of multi-level power consumption modes based on the architecture of different fuze chips (such as the number of sensors and communication protocol differences). It also predicts task loads through machine learning models, providing a scalable framework for low-power design of future high-complexity chips.
[0093] Reference Figure 3-4 As shown, a low-power control system for a fuze chip is applied to the above-mentioned low-power control method. The low-power control system includes: a state detection module for monitoring the working state of each functional module in real time and generating an idle state flag; a clock control module, connected to the state detection module, for maintaining the functional clock signal of the functional module for a preset first time period when the functional module is in an idle state and shutting down the functional clock after timeout. The clock control module includes a programmable clock delay unit for configuring the first time period based on the functional module type and supporting dynamic adjustment; a wake-up management module for receiving an external wake-up request or an internal wake-up event and sending a clock recovery instruction to the clock control module; and a verification protection module for performing data integrity and state consistency verification on the functional module before shutting down the functional clock. Through dynamic switching of multiple power consumption modes and state integrity verification, data loss or module state disorder caused by sudden clock shutdown is avoided, fundamentally solving the problem of system hang or wake-up failure in traditional low-power designs. Non-essential modules are shut down step by step according to the criticality of the module function. Compared with the global switching strategy, power consumption is reduced by 30%-50%, while ensuring the real-time response of core functions. In some modes, the reserved modules are operated at a reduced frequency to further optimize dynamic power consumption.
[0094] In this embodiment, the wake-up management module includes: an external interrupt response unit for capturing external trigger signals; an internal event scheduling unit for generating wake-up instructions based on a timer or task queue; a priority arbitration unit for handling conflicts between multiple wake-up requests. By accurately detecting the idle state of the functional module, delay protection and state verification before clock shutdown, and dynamic switching of multiple power consumption modes, the module ensures that the necessary data storage and state synchronization are completed before entering the low-power state.
[0095] In this embodiment, the verification protection module includes: a data write-back unit, which is used to save the cached data of the functional module to a non-volatile memory; a state latch unit, which is used to record the operating parameters of the functional module before entering the low-power state; an exception handling unit, which is used to trigger an alarm and maintain the functional clock signal when the verification fails. Through the hardware priority encoder and multi-source trigger condition analysis, the conflict between the low-load recommendation to enter deep sleep and the environmental alarm requirement to maintain shallow sleep is resolved, ensuring that the system always takes safety as the highest criterion, and automatically triggering data write-back and alarm when the verification fails to avoid chain failures caused by a single operation error.
[0096] In this embodiment, the entire operation process can be controlled by a computer to provide signal feedback to implement the steps in sequence. These are all conventional knowledge of current automated control and will not be described in detail in this embodiment.
[0097] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A low power consumption control method for a fuze chip, characterized in that: Applied to chip control equipment, specifically including the following steps: S101: detecting the working status of a functional module electrically connected to the fuze chip within a preset period of time, and determining whether the current status of the functional module is in an idle state; S102: If the functional module is in the working state, monitor the operating parameters of the functional module, determine whether the operating parameters of the functional module change by a threshold value within a preset period of time, and determine whether the monitoring functional module is in an idle state after the threshold value change; S103: If it is determined that the current state of the functional module is in an idle state, keeping the functional clock signal of the functional module running within a preset first time period; S104: When no state activation request of the functional module is received within the preset first time period, turning off the function clock signal of the functional module, and the functional module enters a low power consumption state; S105: The functional clock signal responds to an external signal wake-up request or an internal wake-up event, activates the functional clock signal of the functional module after receiving the wake-up signal, and restores the normal working state of the functional module.
2. The low power consumption control method of a fuze chip according to claim 1, characterized in that: In S101, the working status of the functional module electrically connected to the fuze chip is detected within a preset period of time, including: Sending an acquisition request to the fuze chip according to a preset time, wherein the acquisition request includes a status acquisition request for the current fuze chip and a status acquisition request for a functional module electrically connected to the fuze chip; The current fuze chip status acquisition request acquires the status information of the current fuze chip, and if the current fuze chip is in a working state, identifies the data transmission of the current fuze chip; After the identification data is completed, the state of the functional module associated with the current fuze chip is determined, and the first associated module in the current working state is determined; It is determined that the second associated module is in an idle state, and the functional clock signal of the second associated module is kept running.
3. The low power consumption control method of a fuze chip according to claim 2, characterized in that: If the current fuze chip is in working state, the data transmission of the current fuze chip is identified, including: Acquire multiple data recognition models, and sort the recognition contents of the data recognition models according to a priority order set by the system; Acquire the transmission data of the fuse chip, and input the transmission data into the data recognition model ranked first.
4. The low power consumption control method of a fuze chip according to claim 3, characterized in that: In S102, if the functional module is in the working state, the operating parameters of the functional module are monitored to determine whether the operating parameters of the functional module have a threshold change within a preset stage time, including: Determining that the first association module is in a working state through a status acquisition request of the functional module electrically connected to the fuze chip, and acquiring operating parameters of the first association module; The operating parameters include power supply voltage, operating current and power consumption, and noise coefficient. The current power supply voltage, operating current and power consumption, and noise coefficient data of the first associated module are obtained, and the power supply voltage, operating current and power consumption, and noise coefficient of the first associated module are obtained again within a preset stage time. The power supply voltage, operating current and power consumption, and noise factor of the first associated module in the two stages are compared to obtain a parameter comparison difference value, and the parameter comparison difference value is compared with the system preset threshold. If the operating parameters are within the threshold range, the working state is maintained. If the operating parameters are outside the threshold range, the current state of the first associated module is obtained again to determine whether it is in an idle state.
5. The low power consumption control method of a fuze chip according to claim 4, characterized in that: In S103, the function clock signal of the function module is kept running within a preset first time period, including: The first time period is dynamically adjusted according to the clock stabilization time of the functional module or the task response delay requirement; Dynamically extend or shorten the first time period based on the measured or preset stabilization time to ensure that sufficient time is reserved for the module to complete pending operations before shutting down the clock; The task types that may be triggered in the next cycle in the task queue and their maximum allowed delay thresholds are analyzed. If an upcoming high-priority task is detected that requires a quick response, the first time period is shortened to avoid shutting down the clock too early.
6. The low power consumption control method of a fuze chip according to claim 5, characterized in that: In S104, before turning off the functional clock signal of the functional module, the following steps are included: Performing a state integrity check on the functional module to ensure that its cached data has been saved to the non-volatile storage unit; If the check fails, the holding time of the functional clock signal is extended until the check passes, and then the functional clock signal of the functional module is turned off.
7. The low power consumption control method of a fuze chip according to claim 6, characterized in that: In S104, the functional module enters a low power consumption state, wherein the low power consumption state includes a multi-level power consumption mode, and the multi-level power consumption mode is dynamically switched according to the system load, and different modes correspond to different functional clock shutdown ranges and wake-up response priorities.
8. The low power consumption control method of a fuze chip according to claim 7, characterized in that: In S105, the functional clock signal responds to an external signal wake-up request or an internal wake-up event, wherein the external wake-up request includes an external interrupt signal, a communication interface instruction or a sensor trigger signal, and the internal wake-up event includes a timer timeout event or an internal task queue activation instruction.
9. A low power consumption control system for a fuze chip, characterized in that: The low power consumption control method according to any one of claims 1 to 8, wherein the low power consumption control system comprises: Status detection module, used to monitor the working status of each functional module in real time and generate an idle state flag; a clock control module, connected to the state detection module, configured to maintain the functional clock signal of the functional module for a preset first time period when the functional module is in an idle state, and to shut down the functional clock after a timeout, the clock control module including a programmable clock delay unit configured to configure the first time period according to the type of the functional module and supporting dynamic adjustment; A wake-up management module, configured to receive an external wake-up request or an internal wake-up event, and send a clock recovery instruction to the clock control module; The verification protection module is used to perform data integrity and state consistency verification on the functional module before shutting down the functional clock.
10. A low power consumption control system for a fuze chip as claimed in claim 9, characterized in that: The wake-up management module includes: External interrupt response unit, used to capture external trigger signals; Internal event scheduling unit, used to generate wake-up instructions based on timers or task queues; Priority arbitration unit, used to handle conflicts among multiple wake-up requests; The verification protection module includes: A data write-back unit, used to save the cached data of the functional module to the non-volatile memory; A state latch unit, used to record the operating parameters of the functional module before it enters a low-power state; The exception handling unit is used to trigger an alarm when the verification fails and maintain the functional clock signal.
Citation Information
Cited By
Energy-saving system and method for data processing chip
CN121070164A
A processor clock gating control system and electronic device
CN122569715A