Method and system for digitally debugging and optimizing upper computer

Abstract

The invention discloses a digital debugging optimization processing method and system for an upper computer, and relates to the technical field of industrial automation and real-time control, and the method comprises the steps: generating a compensation amount based on a real-time network delay variance and an equipment inertia coefficient, and solving the problem of instruction time sequence drift caused by switch networking fluctuation; particularly, in a high-disturbance environment, action connection errors of precise equipment such as a welding robot and the like are compressed to be within a millisecond level through sliding window contraction and amplification coefficient self-adaptive adjustment, and the mechanical collision risk caused by field failure of preset parameters in a traditional scheme is avoided; in addition, the physical model of the PLC is mapped into motion response parameters, such as inertia and damping coefficients, by utilizing an equipment type library, so that time sequence calibration of equipment of different systems is realized under a unified platform; hardware does not need to be transformed or a special clock chip does not need to be additionally arranged, and the debugging cost of cross-manufacturer equipment integration is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of industrial automation and real-time control, and in particular to a method and system for digital debugging and optimization processing of a host computer. Background Art

[0002] In automated production lines such as automotive manufacturing and electronic assembly, the host computer system needs to coordinate with dozens of PLC devices to complete precise motion control. Such scenarios place extremely high demands on timing synchronization between devices. For example, the trajectory connection of welding robots or the start and stop of material conveyor belts must ensure that the motion interval error is less than milliseconds. As the scale of production lines expands and the number of device communication links increases, network transmission delay fluctuations become an inherent challenge. Especially in cross-regional device collaboration scenarios, such as distributed factories, when the host computer sends instructions to PLCs in different physical locations, the actual execution time of the instructions will be subject to unpredictable offsets due to factors such as switch queue scheduling and signal attenuation.

[0003] In recent years, the mainstream solution has adopted timestamp marking and hardware clock synchronization technology; the host computer uses the IEEE1588 precision clock protocol to add nanosecond-level timestamps to control instructions, and the PLC calibrates the execution time according to the local clock after receiving it; some systems have introduced software-defined networks (SDN) to dynamically optimize data flow paths through centralized controllers to reduce transmission jitter; in a virtual debugging environment, the digital twin platform can preview network delay scenarios, generate fixed compensation parameters and write them into the PLC firmware.

[0004] In actual applications, the hardware clock synchronization of the above solution relies on dedicated chips, which makes it difficult to deploy uniformly in scenarios where heterogeneous PLCs are mixed. For example, PLC devices with different technical systems coexist, for example, those using different clock architectures or communication protocols. Secondly, the fixed compensation parameters cannot adapt to the real-time changing network status of the production line. When sudden traffic causes fluctuations in the switch network, the preset compensation values ​​will exacerbate the timing misalignment. There is a deviation between the network simulation in the virtual debugging phase and the actual physical layer behavior, causing the compensation model to fail on site. These problems lead to the continued existence of production risks such as robot arm collisions and material accumulation. Therefore, a host computer digital debugging and optimization processing solution is urgently needed to solve such problems. Summary of the Invention

[0005] In view of the above existing problems, the present invention is proposed.

[0006] The present invention provides a host computer digital debugging optimization processing method and system to solve the problem that network delay fluctuations and heterogeneous device clock differences lead to timing misalignment in multi-PLC group control, and fixed compensation solutions are difficult to adapt to dynamic environments.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0008] In a first aspect, an embodiment of the present invention provides a method for optimizing digital debugging of a host computer, which includes: step S1, the host computer sends control instructions to multiple PLC devices and adds a high-precision timestamp to each instruction;

[0009] Step S2: receiving the actual execution time fed back by each PLC and calculating the dynamic compensation amount based on historical transmission delay data;

[0010] Step S3, adjusting the sending timing of subsequent instructions according to the dynamic compensation amount;

[0011] The adjusting the sending timing of subsequent instructions includes:

[0012] a) Shift the original instruction sequence in time axis;

[0013] b) performing frame-by-frame reorganization on the instructions that exceed the execution window after translation;

[0014] c) Add checksum to ensure instruction integrity.

[0015] As a preferred solution of the host computer digital debugging optimization processing method described in the present invention, step S2 specifically includes:

[0016] Use a sliding window to count the latency variance of the last N instruction transfers;

[0017] Generate dynamic compensation value based on the inertia coefficient of the target PLC device;

[0018] In step S2, the delay variance is combined with the device inertia coefficient to generate the dynamic compensation amount: After round-trip delays, the sliding window statistical method is used to calculate the delay variance, and then the compensation amount is derived based on this, including:

[0019] Calculate the delay variance, in the length In the window of

[0020] ,

[0021] in, is the number of samples in the window, is the sample index, Indicates the Round trip delay, in ms, is the average delay of the window, in ms, is the delay variance, in units of ;

[0022] Extracting the volatility, the square root of the variance gives the standard deviation:

[0023] ,

[0024] in, is the delay standard deviation, ms;

[0025] Combined with the target PLC inertia coefficient, weight is introduced :

[0026] ,

[0027] in, is the inertia weight, dimensionless, is the target PLC inertia coefficient, in units of , is the reference inertia coefficient, in units of ;

[0028] The coefficient is dynamically amplified according to the network fluctuation amplitude, and the adjustment formula is:

[0029] ,

[0030] in, is the magnification factor, dimensionless, is the maximum amplification, is the preset system parameter, is a natural constant, is the fluctuation threshold, in ms;

[0031] The final compensation expression is:

[0032] ,

[0033] in, is the dynamic compensation amount, the unit is ms, is the inertia weight, is the magnification factor, is the delay standard deviation.

[0034] As a preferred solution of the upper computer digital debugging optimization processing method of the present invention, wherein: the device inertia coefficient is obtained by matching a preset device type library, and the device type library stores motion response parameters of different PLC models;

[0035] The construction of the device type library includes:

[0036] Map the PLC model and motion response parameters into key-value pairs;

[0037] The response parameters include the acceleration threshold and the mechanical damping coefficient range;

[0038] Real-time matching of parameter entries by device ID.

[0039] As a preferred solution of the host computer digital debugging optimization processing method described in the present invention, step S3 includes:

[0040] Determine the transmission environment level in real time based on the network status classifier;

[0041] Selecting a compensation strategy corresponding to the transmission environment level to perform timing adjustment;

[0042] The determination of the transmission environment level includes:

[0043] When the packet loss rate exceeds the preset threshold, it is defined as a high disturbance level;

[0044] When the delay variance exceeds 3 times the historical mean, it is defined as a medium disturbance level;

[0045] Enable an aggressive compensation strategy for high disturbance levels: shorten the sliding window to the first threshold;

[0046] Enables a conservative compensation strategy for medium disturbance levels: maintains a sliding window.

[0047] As a preferred solution of the upper computer digital debugging optimization processing method described in the present invention, wherein: the network status classifier in step S3 calculates the fluctuation variance of packet loss rate, jitter and delay through a sliding window;

[0048] In step S3, the network status classifier's environment level determination strategy is to extract three indicators, namely, packet loss rate, jitter, and delay standard deviation, from the communication buffer at regular intervals, and complete the environment classification according to the following process:

[0049] Normalize the indicators:

[0050] , , ,

[0051] in, is the normalized packet loss rate, The current window packet loss rate, in %. is the upper limit of the acceptable maximum packet loss rate, %. is the normalized jitter, is the current window jitter mean, in ms, is the jitter threshold, in ms, is the normalized delay standard deviation, is the delay standard deviation, in ms, is the delay fluctuation threshold, in ms;

[0052] Generate adaptive weights:

[0053] , , ,

[0054] in, are the weights of packet loss rate, jitter, and delay variance, dimensionless, For the past The variance of the packet loss rate in each sampling period, in %², is the jitter variance in ms², is the standard deviation of the delay, in ms², is the weight statistics window length;

[0055] Calculate the environmental score: ,

[0056] in, is the comprehensive environmental score, dimensionless;

[0057] Perform level mapping:

[0058] ,

[0059] in, To determine the output environment level, is the medium disturbance threshold, is the high disturbance threshold.

[0060] As a preferred solution of the upper computer digital debugging optimization processing method described in the present invention, in step S3, a compensation strategy is selected according to the transmission environment level to adjust the dynamic compensation amount and network environment level After the classifier obtains the grade, the statistical window length and amplification factor are adjusted synchronously according to the following steps to achieve differential compensation, including:

[0061] Calculate the grade coefficient:

[0062] ,

[0063] in, is the grade coefficient, dimensionless, is the window shrinkage coefficient, is the environmental level, with a value of 1 indicating low disturbance, 2 indicating medium disturbance, and 3 indicating high disturbance;

[0064] Update the sliding window length: ,

[0065] in, The length of the current cycle delay statistics window, in bars. The table is rounded up. is the reference window length, in bars;

[0066] Dynamic adjustment of amplification:

[0067] ,

[0068] in, To increase the level of As a benchmark, To increase the coefficient of amplification;

[0069] Calculate the adaptive coefficient weight:

[0070] ,

[0071] in, is the level adaptation coefficient, dimensionless, is a natural constant, is the delay standard deviation, in ms, is the delay fluctuation threshold, in ms;

[0072] Level compensation output:

[0073] ,

[0074] in, is the final dynamic compensation amount after environmental level correction, ms, is the inertia weight, dimensionless.

[0075] In a second aspect, the present invention provides a host computer digital debugging optimization processing system, comprising:

[0076] Instruction distribution module, used to send control instructions with time stamps to PLC devices;

[0077] Dynamic analysis module, used to calculate instruction transmission delay variance and dynamic compensation amount;

[0078] The timing scheduling module is used to adjust the instruction sending timing.

[0079] As a preferred solution of the host computer digital debugging and optimization processing system described in the present invention, the dynamic analysis module includes:

[0080] Variance calculation unit, which counts transmission delay fluctuations based on a sliding window;

[0081] The compensation generation unit calls the inertia coefficient in the device type library to calculate the compensation amount.

[0082] As a preferred solution of the host computer digital debugging and optimization processing system described in the present invention, the timing scheduling module includes:

[0083] Environmental classification unit, real-time identification of network transmission status level;

[0084] The strategy execution unit selects preset compensation strategies according to different levels.

[0085] As a preferred solution of the host computer digital debugging and optimization processing system described in the present invention, the device type library associates the PLC physical model with motion response parameters, and the motion response parameters include acceleration and mechanical damping coefficient.

[0086] The beneficial effects of the present invention are as follows: the present invention generates a compensation amount based on the real-time network delay variance and the device inertia coefficient to solve the instruction timing drift caused by the fluctuation of the switch networking; especially in a high-disturbance environment, the sliding window shrinkage and the adaptive adjustment of the amplification factor can compress the motion connection error of precision equipment such as welding robots to within the millisecond level, avoiding the risk of mechanical collision caused by the failure of preset parameters in the traditional solution on site; in addition, the device type library is used to map the PLC physical model to motion response parameters (such as inertia and damping coefficient), so that PLC devices of different systems can achieve timing calibration under a unified platform; there is no need to modify hardware or add dedicated clock chips, which reduces the debugging cost of cross-manufacturer equipment integration.

[0087] The present invention dynamically divides the environment into levels based on indicators such as packet loss rate and jitter, and matches differentiated strategies for different disturbance intensities: shortening the statistical window and increasing the compensation margin in high disturbance conditions to quickly suppress the impact of sudden traffic; maintaining lightweight computing in low disturbance conditions to reduce unnecessary instruction frame splitting operations; this design significantly reduces the computing load of the host computer and ensures the stability of long-term operation; through the time axis translation and frame reorganization mechanism, it ensures that the instructions after timing adjustment are delivered completely within the PLC execution window; adding check codes to prevent data misalignment during transmission and avoid production line chain failures caused by the loss of a single instruction. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0089] Figure 1 This is a flow chart of a method for optimizing digital debugging of a host computer in Example 1.

[0090] Figure 2 This is a schematic diagram of the framework of a host computer digital debugging and optimization processing system in Example 1. DETAILED DESCRIPTION

[0091] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0092] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0093] Secondly, the term "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive of other embodiments.

[0094] Example 1, with reference to Figure 1 and Figure 2 This embodiment provides a host computer digital debugging optimization processing method, including the following steps:

[0095] Step S1: The host computer sends control instructions to multiple PLC devices and adds a high-precision timestamp to each instruction;

[0096] Step S2: receiving the actual execution time fed back by each PLC and calculating the dynamic compensation amount based on historical transmission delay data;

[0097] Step S2 specifically includes:

[0098] Use a sliding window to count the latency variance of the last N instruction transfers;

[0099] Generate dynamic compensation value based on the inertia coefficient of the target PLC device;

[0100] In step S2, the delay variance is coupled with the device inertia coefficient to generate the dynamic compensation amount: in order to correct the network jitter and the device dynamic characteristics synchronously, after obtaining the latest After round-trip delays, the sliding window statistical method is used to calculate the delay variance, and then the compensation amount is derived based on this, including:

[0101] Calculate the delay variance, in the length In the window of

[0102] ,

[0103] in, is the number of samples in the window, is the sample index, Indicates the Round trip delay, in ms, is the average delay of the window, in ms, is the delay variance, in units of ;

[0104] Extracting the volatility, the square root of the variance gives the standard deviation:

[0105] ,

[0106] in, is the delay standard deviation, ms;

[0107] Combined with the target PLC inertia coefficient, weight is introduced :

[0108] ,

[0109] in, is the inertia weight, dimensionless, is the target PLC inertia coefficient, in units of , is the reference inertia coefficient, in units of ;

[0110] The coefficient is dynamically amplified according to the network fluctuation amplitude, and the adjustment formula is:

[0111] ,

[0112] in, is the magnification factor, dimensionless, For maximum amplification, is a natural constant, is the fluctuation threshold, in ms;

[0113] The final compensation expression is:

[0114] ,

[0115] in, is the dynamic compensation amount, the unit is ms, is the inertia weight, is the magnification factor, is the standard deviation of delay;

[0116] Specifically, this step captures recent delay fluctuations through a sliding window, quantifies the jitter intensity with standard deviation, and then uses inertia weight Incorporate physical response characteristics into timing correction to ensure that compensation matches the equipment load capacity; exponential amplification factor It increases rapidly with the increase of fluctuations, remains approximately linear in the weak jitter area, and provides additional margin in the strong jitter area to balance stability and agility; the final compensation amount Simultaneously coupling network status and device inertia to achieve greater timing reserve in high-inertia and high-jitter scenarios, while avoiding excessive lead instructions in low-inertia and low-jitter scenarios, improving execution window consistency and overall operational smoothness;

[0117] The device inertia coefficient is obtained by matching the preset device type library. The device type library stores the motion response parameters of different PLC models. The construction of the device type library includes:

[0118] Map the PLC model and motion response parameters into key-value pairs;

[0119] The response parameters include the acceleration threshold and the mechanical damping coefficient range;

[0120] Real-time matching of parameter entries by device ID;

[0121] Step S3, adjusting the sending timing of subsequent instructions according to the dynamic compensation amount;

[0122] Adjusting the sending timing of subsequent instructions includes:

[0123] a) Shift the original instruction sequence in time axis;

[0124] b) performing frame-by-frame reorganization on the instructions that exceed the execution window after translation;

[0125] c) Add checksum to ensure the integrity of the instruction;

[0126] Step S3 includes:

[0127] Determine the transmission environment level in real time based on the network status classifier;

[0128] Select a compensation strategy corresponding to the transmission environment level to perform timing adjustment;

[0129] In step S3, the network status classifier's environment level determination strategy is to extract three indicators, namely, packet loss rate, jitter, and delay standard deviation, from the communication buffer at regular intervals, and complete the environment classification according to the following process:

[0130] Normalize the indicators:

[0131] , , ,

[0132] in, is the normalized packet loss rate, The current window packet loss rate, in %. is the upper limit of the acceptable maximum packet loss rate, %. is the normalized jitter, is the current window jitter mean, in ms, is the jitter threshold, in ms, is the normalized delay standard deviation, is the delay standard deviation, in ms, is the delay fluctuation threshold, in ms;

[0133] Generate adaptive weights:

[0134] , , ,

[0135] in, are the weights of packet loss rate, jitter, and delay variance, dimensionless, For the past The variance of the packet loss rate in each sampling period, in %², is the jitter variance in ms², is the standard deviation of the delay, in ms², is the weight statistics window length (periods, unitless);

[0136] Calculate the environmental score: ,

[0137] in, is the comprehensive environmental score, dimensionless;

[0138] Perform level mapping:

[0139] ,

[0140] in, To determine the output environment level, is the medium disturbance threshold, is the high disturbance threshold;

[0141] Specifically, the classifier considers three key indicators: packet loss, jitter, and delay, and uses adaptive weights to reflect their short-term fluctuation ratios: if jitter contributes the most, then Automatically increase the score to be more sensitive to timing drift. If packet loss increases dramatically, Dominant, giving priority to triggering aggressive compensation strategies; normalization processing ensures that indicators of different dimensions can be calculated in parallel, and thresholds The three-level scheduling system allows the scheduling module to quickly tighten the window in high-disturbance scenarios and maintain minimal intervention in low-disturbance scenarios, reducing unnecessary instruction de-framing and reassembly. The overall strategy responds quickly to sudden changes in network status and maintains lightweight judgment during stable periods, balancing robustness and efficiency.

[0142] The determination of the transmission environment level includes:

[0143] When the packet loss rate exceeds the preset threshold, it is defined as a high disturbance level;

[0144] When the delay variance exceeds 3 times the historical mean, it is defined as a medium disturbance level;

[0145] Enable an aggressive compensation strategy for high disturbance levels: shorten the sliding window to the first threshold;

[0146] Enable conservative compensation strategy for medium disturbance levels: keep sliding window;

[0147] In step S3, a compensation strategy is selected according to the transmission environment level, which is to set the dynamic compensation amount and network environment level After the classifier obtains the grade, the statistical window length and amplification factor are adjusted synchronously according to the following steps to achieve differential compensation, including:

[0148] Calculate the grade coefficient:

[0149] ,

[0150] in, is the grade coefficient, dimensionless, is the window shrinkage coefficient, is the environmental level, with a value of 1 indicating low disturbance, 2 indicating medium disturbance, and 3 indicating high disturbance;

[0151] Update the sliding window length: ,

[0152] in, The length of the current cycle delay statistics window, in bars. The table is rounded up. is the reference window length, in bars;

[0153] Dynamic adjustment of amplification:

[0154] ,

[0155] in, To increase the level of As a benchmark, To increase the coefficient of amplification;

[0156] Calculate the adaptive coefficient weight:

[0157] ,

[0158] in, is the level adaptation coefficient, dimensionless, is a natural constant, is the delay standard deviation, in ms, is the delay fluctuation threshold, in ms;

[0159] Level compensation output:

[0160] ,

[0161] in, is the final dynamic compensation amount after environmental level correction, ms, is the inertia weight, dimensionless;

[0162] Specifically, the strategy shrinks or expands the statistical window in real time according to the network level: when the disturbance is severe, the window length is significantly shortened to suppress the tailing effect of old data on compensation, and sufficient samples are maintained when the network is stable to smooth out transient anomalies; the amount of amplification increases with the level, so that time compensation obtains a higher lead margin in a high-disturbance environment, and maintains a mild correction in the low-disturbance stage to avoid an increase in network load; after combining the inertia weight, the dual factors of device dynamics and network status are coordinated to adjust, which not only reduces the hysteresis of high-inertia hardware, but also prevents low-inertia systems from generating command congestion due to over-compensation; the overall process responds adaptively when switching between different environments, reduces the number of manual parameter adjustments, and improves the timing stability and task consistency of long-term operation.

[0163] This embodiment also provides a host computer digital debugging optimization processing system, including:

[0164] Instruction distribution module, used to send control instructions with time stamps to PLC devices;

[0165] Dynamic analysis module, used to calculate instruction transmission delay variance and dynamic compensation amount;

[0166] Timing scheduling module, used to adjust the instruction sending timing;

[0167] Dynamic analysis modules include:

[0168] Variance calculation unit, which counts transmission delay fluctuations based on a sliding window;

[0169] The compensation generation unit calls the inertia coefficient in the device type library to calculate the compensation amount;

[0170] The timing scheduling module includes:

[0171] Environmental classification unit, real-time identification of network transmission status level;

[0172] Strategy execution unit, which selects preset compensation strategies according to different levels;

[0173] The device type library associates the PLC physical model with motion response parameters, which include acceleration and mechanical damping coefficient.

[0174] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A host computer digital debugging optimization processing method, characterized in that: The following steps are involved: Step S1: The host computer sends control instructions to multiple PLC devices and adds a high-precision timestamp to each instruction; Step S2: receiving the actual execution time fed back by each PLC and calculating the dynamic compensation amount based on historical transmission delay data; Step S3, adjusting the sending timing of subsequent instructions according to the dynamic compensation amount; The adjusting the sending timing of subsequent instructions includes: a) Shift the original instruction sequence in time axis; b) performing frame-by-frame reorganization on the instructions that exceed the execution window after translation; c) Add checksum to ensure instruction integrity.

2. A host computer digital debugging optimization processing method according to claim 1, characterized in that: Step S2 specifically includes: Use a sliding window to count the latency variance of the last N instruction transfers; Generate dynamic compensation value based on the inertia coefficient of the target PLC device; In step S2, the delay variance is combined with the device inertia coefficient to generate the dynamic compensation amount: After round-trip delays, the sliding window statistical method is used to calculate the delay variance, and then the compensation amount is derived based on this, including: Calculate the delay variance, in the length In the window of ， in, is the number of samples in the window, is the sample index, Indicates the Round trip delay, in ms, is the average delay of the window, in ms, is the delay variance, in units of ; Extracting the volatility, the square root of the variance gives the standard deviation: ， in, is the delay standard deviation, ms; Combined with the target PLC inertia coefficient, weight is introduced : ， in, is the inertia weight, dimensionless, is the target PLC inertia coefficient, in units of , is the base inertia coefficient, in units of ; The coefficient is dynamically amplified according to the network fluctuation amplitude, and the adjustment formula is: ， in, is the magnification factor, dimensionless, is the maximum amplification, is the preset system parameter, is a natural constant, is the fluctuation threshold, in ms; The final compensation expression is: ， in, is the dynamic compensation amount, the unit is ms, is the inertia weight, is the magnification factor, is the standard deviation of the delay.

3. A host computer digital debugging optimization processing method according to claim 2, characterized in that: The device inertia coefficient is obtained by matching a preset device type library, and the device type library stores motion response parameters of different PLC models; The construction of the device type library includes: Map the PLC model and motion response parameters into key-value pairs; The response parameters include the acceleration threshold and the mechanical damping coefficient range; Real-time matching of parameter entries by device ID.

4. A host computer digital debugging optimization processing method according to claim 1, characterized in that: Step S3 includes: Determine the transmission environment level in real time based on the network status classifier; Selecting a compensation strategy corresponding to the transmission environment level to perform timing adjustment; The determination of the transmission environment level includes: When the packet loss rate exceeds the preset threshold, it is defined as a high disturbance level; When the delay variance exceeds 3 times the historical mean, it is defined as a medium disturbance level; Enable an aggressive compensation strategy for high disturbance levels: shorten the sliding window to the first threshold; Enables a conservative compensation strategy for medium disturbance levels: maintains the sliding window size.

5. A host computer digital debugging optimization processing method according to claim 4, characterized in that: In step S3, the network status classifier calculates the fluctuation variance of packet loss rate, jitter and delay through a sliding window; In step S3, the network status classifier's environment level determination strategy is to extract three indicators, namely, packet loss rate, jitter, and delay standard deviation, from the communication buffer at regular intervals, and complete the environment classification according to the following process: Normalize the indicators: ， ， ， in, is the normalized packet loss rate, The current window packet loss rate, in %. is the upper limit of the acceptable maximum packet loss rate, %. is the normalized jitter, is the current window jitter mean, in ms, is the jitter threshold, in ms, is the normalized delay standard deviation, is the delay standard deviation, in ms, is the delay fluctuation threshold, in ms; Generate adaptive weights: ， ， ， in, are the weights of packet loss rate, jitter, and delay variance, dimensionless, For the past The variance of the packet loss rate in each sampling period, in %², is the jitter variance in ms², is the standard deviation of the delay, in ms², is the weight statistics window length; Calculate the environmental score: , in, is the comprehensive environmental score, dimensionless; Perform level mapping: ， in, To determine the output environment level, is the medium disturbance threshold, is the high disturbance threshold.

6. A host computer digital debugging optimization processing method according to claim 4, characterized in that: In step S3, a compensation strategy is selected according to the transmission environment level, which is to set the dynamic compensation amount and network environment level After the classifier obtains the grade, the statistical window length and amplification factor are adjusted synchronously according to the following steps to achieve differential compensation, including: Calculate the grade coefficient: ， in, is the grade coefficient, dimensionless, is the window shrinkage coefficient, is the environmental level, with a value of 1 indicating low disturbance, 2 indicating medium disturbance, and 3 indicating high disturbance; Update the sliding window length: , in, The length of the current cycle delay statistics window, in bars. The table is rounded up. is the reference window length, in bars; Dynamic adjustment of amplification: ， in, To increase the level of As a benchmark, To increase the coefficient of amplification; Calculate the adaptive coefficient weight: ， in, is the level adaptation coefficient, dimensionless, is a natural constant, is the delay standard deviation, in ms, is the delay fluctuation threshold, in ms; Level compensation output: ， in, is the final dynamic compensation amount after environmental level correction, ms, is the inertia weight, dimensionless.

7. A host computer digital debugging optimization processing system, based on a host computer digital debugging optimization processing method according to any one of claims 1 to 6, characterized in that: include: Instruction distribution module, used to send control instructions with time stamps to PLC devices; Dynamic analysis module, used to calculate instruction transmission delay variance and dynamic compensation amount; The timing scheduling module is used to adjust the instruction sending timing.

8. A host computer digital debugging and optimization processing system according to claim 7, characterized in that: The dynamic analysis module includes: Variance calculation unit, which counts transmission delay fluctuations based on a sliding window; The compensation generation unit calls the inertia coefficient in the device type library to calculate the compensation amount.

9. A host computer digital debugging and optimization processing system according to claim 7, characterized in that: The timing scheduling module includes: Environmental classification unit, real-time identification of network transmission status level; The strategy execution unit selects preset compensation strategies according to different levels.

10. A host computer digital debugging and optimization processing system according to claim 8, characterized in that: The device type library associates the PLC physical model with motion response parameters, and the motion response parameters include acceleration and mechanical damping coefficient.

Images