Circuit based on CORDIC algorithm and operation method thereof

Abstract

The invention provides a circuit based on a CORDIC algorithm and an operation method thereof, and relates to the technical field of hardware implementation of functions. The circuit comprises a control module, an iterative operation module and a post-processing module, the control module is used for generating target configuration information so as to configure a function type included in the iterative operation module, an operation mode corresponding to the function type and the number of iterations, and the iterative operation module is used for generating target configuration information. The iterative calculation module is used for carrying out iterative calculation on the preprocessed intermediate data based on the target configuration information to obtain target data, and the post-processing module is used for carrying out post-processing on the target data obtained after iteration is completed and outputting a processed result. According to the invention, the calculation of the trigonometric function, the linear function and the hyperbolic function is realized through iterative approximation, and the calculation is realized by configuring the corresponding number of iterations according to the precision required by the use demand, so that the use efficiency of the CORDIC algorithm circuit is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of hardware implementation of functions, and in particular to a circuit based on a CORDIC (Coordinate Rotation Digital Computer) algorithm and an operation method thereof. Background Art

[0002] The calculation of mathematical functions, such as trigonometric, linear, and hyperbolic functions, is a core component of many algorithms in fields such as communications, aerospace, and digital signal processing. However, these functions are often difficult to directly calculate in hardware. Traditional table lookup methods or polynomial approximation methods often require large storage resources or high computational complexity, making them difficult to meet the requirements of high-performance, low-power hardware design.

[0003] The Coordinate Rotation Digital Computer (CORDIC) algorithm approximates the calculation results of complex functions through iterative shift and addition and subtraction operations, avoiding complex multiplication operations and significantly reducing the difficulty of hardware implementation. The general iterative formula of the CORDIC algorithm is as follows:

[0004]

[0005] Among them, parameters m and e i Varies depending on the computational objective:

[0006] When calculating trigonometric functions, m=1, ;

[0007] When calculating linear functions, m=0, ;

[0008] When calculating hyperbolic functions, m=-1, ;

[0009] In rotation mode, ; In vector mode, .

[0010] Figure 1 The algorithm structure block diagram corresponding to a general iterative formula provided in the prior art; the algorithm structure block diagram corresponding to the general iterative formula is as follows Figure 1 As shown in the figure. MUX (Multiplexer): Multiplexer, used to select an output from multiple input signals. X / Y / Z Register: X / Y / Z register, used to store the coordinate value (X, Y) and angle value (Z) of the current iteration. atan / 2⁻ 1 / atanh Lookup Table: stores pre-calculated angle values ​​(such as arctan(2⁻ 1 ) or arctanh(2⁻ 1)), used for CORDIC iterative calculation. Iteration (i) Counter: Iteration counter, records the current iteration number (i), controls shift and angle search. Shift: Shift operation, performs arithmetic right shift on X or Y data (equivalent to multiplying by 2⁻ 1 ). dᵢ and m Control: Control signal that determines the direction of rotation (dᵢ = ±1) and CORDIC mode (m = 1 triangular, m = 0 linear, m = -1 hyperbolic).

[0011] This circuit is a typical CORDIC iteration unit, used to implement hardware calculations of trigonometric, hyperbolic, or linear functions. Its workflow is as follows: Input selection (MUX): There is a MUX in front of each register (X, Y, Z) to select the initial input data or the result of the previous iteration. In the first iteration, the MUX selects the initial value of the external input (X0, Y0, Z0); in subsequent iterations, it selects the result of the previous calculation (Xᵢ, Yᵢ, Zᵢ). Shift operation (Shift): The X and Y data are arithmetically shifted right by i bits according to the current iteration number i (equivalent to multiplying by 2⁻ 1 The shifted data (X≫i, Y≫i) is fed into the addition and subtraction unit for the next step. Angle Lookup (Lookup Table): The lookup table is only used for the calculation of Zᵢ in each iteration. The contents of the lookup table are determined by the CORDIC mode (m): Triangular (m=1): , linear (m=0): , hyperbolic (m=-1): Addition and subtraction operations: X and Y paths: Based on the dᵢ and m control signals, the following operations are performed (using trigonometric as an example): , ; Z path: update remaining angle Iteration control: The iteration counter (i) is incremented until a preset number of iterations (e.g., 16) is reached, at which point the result converges to the target accuracy.

[0012] Existing CORDIC hardware implementations typically use a fixed number of iterations, but the computational accuracy requirements vary significantly across different application scenarios. For example, high-precision navigation systems may require a higher number of iterations to ensure the accuracy of the calculation results, while real-time signal processing systems may prioritize computational speed and allow for a moderate reduction in accuracy to reduce the computational cycle. However, traditional CORDIC circuits cannot dynamically adjust the number of iterations, resulting in redundant calculations in low-precision scenarios and reduced computational efficiency. Therefore, designing a CORDIC hardware implementation with a configurable number of iterations to flexibly adapt to varying accuracy and performance requirements has become a pressing technical challenge.

[0013] Public content

[0014] The technical problem to be solved by the present disclosure is to overcome the defect in the prior art that the traditional CORDIC circuit cannot dynamically adjust the number of iterations, resulting in redundant calculations still being performed in low-precision demand scenarios, thereby reducing the computing efficiency, and provide a circuit based on the CORDIC algorithm and its computing method.

[0015] The present disclosure solves the above technical problems through the following technical solutions:

[0016] The present disclosure provides a circuit based on a CORDIC algorithm, the circuit comprising: a control module, an iterative operation module and a post-processing module;

[0017] The control module is configured to generate target configuration information to configure the function type included in the iterative operation module, the operation mode corresponding to the function type, and the number of iterations;

[0018] The iterative calculation module is used to perform iterative calculation on the pre-processed intermediate data based on the target configuration information to obtain target data;

[0019] The post-processing module is used to post-process the target data obtained through iteration and output the processed results.

[0020] In this solution, a configurable control module is used to support switching between multiple function types. This solution also allows the number of iterations to be configured on demand to achieve a dynamic balance between calculation accuracy and operation speed. The post-processing module can automatically select data processing strategies according to different function types. Through the above technical solution, this application solves the problem of low resource utilization caused by the solidification of iterative parameters of traditional CORDIC circuits, and realizes on-demand adjustment of hardware calculation accuracy and operation speed. This solution enables a single circuit to adapt to the computing requirements of different application scenarios, effectively reducing power consumption while ensuring calculation accuracy, and improving the reuse rate of hardware resources. Especially in real-time systems that require dynamic adjustment of calculation parameters, the overall system performance can be significantly improved through online reconfiguration.

[0021] Optionally, the circuit further includes a pre-processing module;

[0022] The preprocessing module is used to preprocess the input initial data according to the configured function type to obtain the intermediate data.

[0023] In this solution, the preprocessing module performs bit expansion, quadrant mapping, or parameter normalization on the input data according to the configured function type (such as trigonometric function, hyperbolic function, or linear function), eliminating the risk of subsequent data calculation overflow and reducing the loss of calculation results to improve data calculation accuracy. Combined with the flexible configuration of the control module, the multiplier-free pipeline calculation of the iteration module, and the precision compensation of the post-processing module, hardware resource reuse is achieved throughout the entire process.

[0024] Optionally, the iterative operation module includes: an input selection unit, a first shift unit, a second shift unit, an addition and subtraction operation unit, and an output selection unit;

[0025] The input selection unit is configured to select the initial data in a first iteration and select the result of the previous iteration in subsequent iterations to generate first intermediate data; the first intermediate data includes data in the X direction, data in the Y direction, and data in the Z direction;

[0026] The first shift unit is configured to perform a shift operation on the data in the X direction to obtain second intermediate data;

[0027] The second shift unit is configured to perform a shift operation on the data in the Y direction to obtain third intermediate data;

[0028] The addition and subtraction operation unit is used to perform addition and subtraction operations on the first intermediate data, the second intermediate data, the third intermediate data, the data in the Z direction, and data output by a preset lookup table; the data output by the preset lookup table is determined by the function type and the current number of iterations;

[0029] The output selection unit is used, when performing an operation on X-direction data, to select a result from the operation results output by the addition and subtraction operation unit or from the results output by the input selection unit according to the operation mode corresponding to the function type and the current number of iterations, and feed the result back to the input end of the input selection unit; when performing an operation on Y- and Z-direction data, the output selection unit is used to select a result from the operation results output by the addition and subtraction operation unit according to the operation mode corresponding to the function type and the current number of iterations, and feed the result back to the input end of the input selection unit.

[0030] In this solution, a universal iterative operation module that supports multi-mode operations is constructed to solve the problem that traditional CORDIC hardware cannot flexibly configure function types and iteration times. Through a dynamic data path selection mechanism, seamless switching between initial data and intermediate iterative results is achieved, ensuring the correct execution of different iteration times. The configurable shift unit and mode-related output selection logic are used to meet the special requirements of trigonometric, linear, and hyperbolic functions for shift operations, ensuring the accurate calculation of various mathematical models. The dynamic acquisition method of angle compensation values ​​based on the lookup table effectively supports the parameter differences between rotation mode and vector mode, improving the reuse efficiency of hardware resources.

[0031] Optionally, the input selection unit includes a first selector, a second selector and a third selector;

[0032] The first selector is used to select the initial data in the X direction in the first iteration, and to select the data in the X direction in the previous iteration result in subsequent iterations;

[0033] The second selector is used to select the initial data in the Y direction in the first iteration, and select the data in the Y direction in the previous iteration result in subsequent iterations;

[0034] The third selector is used to select the initial data in the Z direction in the first iteration, and to select the data in the Z direction in the result of the previous iteration in subsequent iterations.

[0035] Optionally, the input of the first shift unit comes from the data in the X direction output by the first selector, and the input of the second shift unit comes from the data in the Y direction output by the second selector.

[0036] Optionally, the addition and subtraction operation unit includes a first adder, a second adder, a third adder, a first subtractor, a second subtractor and a third subtractor;

[0037] The inputs of the first adder and the first subtractor include the X-direction data output by the first selector and the Y-direction shift data output by the second shift unit;

[0038] The inputs of the second adder and the second subtractor include the Y-direction data output by the second selector and the X-direction shifted data output by the first shift unit;

[0039] The inputs of the third adder and the third subtractor include the data in the Z direction output by the third selector and the data output by the preset lookup table;

[0040] The output selection unit includes a fourth selector, a fifth selector and a sixth selector;

[0041] The input of the fourth selector includes the output data of the first adder, the output data of the first subtractor and the X-direction data output by the first selector;

[0042] The input of the fifth selector includes the output data of the second adder and the output data of the second subtractor;

[0043] An input of the sixth selector includes output data of the third adder and output data of the third subtractor.

[0044] Optionally, the function type includes trigonometric function, linear function, and hyperbolic function;

[0045] The modes corresponding to the trigonometric function, the linear function and the hyperbolic function are rotation modes or vector modes.

[0046] Optionally, the control module may also be configured to update the target configuration information based on a user's selection.

[0047] In this solution, through the above technical solution, this application solves the problem of poor scenario adaptability caused by the fixed parameters of traditional CORDIC hardware circuits, and achieves dynamic balance control between calculation accuracy and operation speed. Users can flexibly configure the number of iterations according to actual application needs.

[0048] Optionally, the post-processing module includes a bit truncation processing unit, an overflow judgment unit and a quadrant recovery unit;

[0049] The bit truncation processing unit is used to perform a bit truncation processing operation on the data after the iteration;

[0050] The overflow judgment unit is used to perform an overflow judgment operation on the data after the bit truncation processing;

[0051] The quadrant recovery unit is used to perform a quadrant recovery processing operation on the data after overflow judgment.

[0052] In this solution, through the above technical solutions, this application solves the three major technical problems of precision redundancy, numerical out-of-bounds, and spatial offset in the iterative results. The bit truncation unit ensures that the output data meets the target precision specification to avoid resource waste; the overflow judgment unit actively identifies and handles numerical anomalies to prevent the output of erroneous results; the quadrant recovery unit corrects the spatial errors caused by the calculation range limitation of the algorithm to ensure the geometric correctness of the calculation results. The three work together to enable the hardware implementation of the CORDIC algorithm to have the comprehensive capabilities of adaptive precision adjustment, active safety protection, and spatial mapping correction.

[0053] The present disclosure further provides an operation method based on the CORDIC algorithm, the operation method being used to control the circuit based on the CORDIC algorithm as described above, the operation method comprising:

[0054] Receive configuration parameters input by a user and generate target configuration information based on the configuration parameters; the configuration parameters include a function type, an operation mode corresponding to the function type, and a number of iterations;

[0055] Iteratively calculating the preprocessed intermediate data based on the target configuration information to obtain target data;

[0056] Post-process the target data obtained after iteration, and output the processed results.

[0057] On the basis of conforming to the common sense in this field, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0058] The positive progress of this disclosure is:

[0059] The present disclosure dynamically configures the function type (such as trigonometric, linear, hyperbolic functions, etc.), operation mode (rotation / vector mode) and number of iterations through the control module, so that the iterative operation module can efficiently complete the parallel iterative calculation without multipliers. Combined with the precision correction and format conversion of the post-processing module, it ultimately achieves high-precision transcendental function operations with low hardware resource consumption (only shifters and adders are required), while supporting flexible switching of multiple operation functions, significantly improving the versatility and energy efficiency of the computing unit.

[0060] The present disclosure aims to use operations that are easily implemented by hardware, such as addition, subtraction, and shifting, to iteratively approximate the calculation of trigonometric functions, linear functions, and hyperbolic functions, and to configure the corresponding number of iterations according to the required accuracy to achieve the calculation, thereby improving the efficiency of the CORDIC algorithm circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 This is a block diagram of an algorithm structure corresponding to a general iterative formula provided in the prior art;

[0062] Figure 2 A circuit diagram based on a CORDIC algorithm provided in an embodiment of the present disclosure;

[0063] Figure 3 A flowchart of a CORDIC algorithm-based calculation method provided in an embodiment of the present disclosure;

[0064] Figure 4 A schematic structural diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0066] It should be noted that if this embodiment involves directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0067] In addition, if there are descriptions involving "first", "second", etc. in this embodiment, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by this disclosure.

[0068] Example 1

[0069] See also Figure 2 , this embodiment provides a circuit based on the CORDIC algorithm, Figure 2 This is a circuit schematic diagram based on the CORDIC algorithm provided in an embodiment of the present disclosure, which includes: a control module, an iterative operation module and a post-processing module; the control module is used to generate target configuration information to configure the function type included in the iterative operation module, the operation mode corresponding to the function type and the number of iterations; the iterative operation module is used to iteratively calculate the preprocessed intermediate data based on the target configuration information to obtain target data; the post-processing module is used to post-process the target data obtained after the iteration and output the processed results.

[0070] By dynamically configuring the function type (e.g., trigonometric, linear, hyperbolic, etc.), operation mode (rotation / vector mode), and number of iterations through the control module, the iterative operation module can efficiently complete parallel iterative calculations without multipliers. Combined with the precision correction and format conversion of the post-processing module, high-precision transcendental function calculations are ultimately achieved with low hardware resource consumption (requiring only shifters and adders). Flexible switching of multiple operation functions is also supported, significantly improving the versatility and energy efficiency of the computing unit. This disclosure aims to iteratively approximate the calculation of trigonometric, linear, and hyperbolic functions using operations that are easily implemented in hardware, such as addition, subtraction, and shifting. The calculations are then configured with the corresponding number of iterations based on the required accuracy, thereby improving the efficiency of the CORDIC algorithm circuit.

[0071] Specifically, the user needs to first configure the function type to be calculated, the operation mode corresponding to the function type, and the number of iterations. After receiving the user's input, the control module generates target configuration information based on the input information. The function types include trigonometric functions, linear functions, and hyperbolic functions; the modes corresponding to trigonometric functions, linear functions, and hyperbolic functions are rotation modes or vector modes.

[0072] Rotation mode involves performing function calculations by rotating coordinates to successively approximate the target angle. Specifically, a sign bit determination mechanism is used to control the rotation direction, combined with a shift adder to implement coordinate iteration. Vector mode involves calculating the modulus or phase angle of the input vector. Specifically, a sign comparison circuit is used to determine the vector's quadrant, combined with a shift accumulation unit to achieve modulus approximation. Specifically, this circuit receives external configuration parameters through a control module and encodes the function type, operation mode, and number of iterations as control signals. When performing trigonometric function calculations, the control module configures the iterative operation module to enter rotation mode or vector mode and sets the corresponding number of iterations. The iterative operation module uses preset shift parameters based on the current iteration number and performs shift addition / subtraction operations through a multi-stage pipeline structure. During each iteration, a data selection unit switches the data path based on the control signal to ensure that the correct operation path is used for each function type. After the set number of iterations, the post-processing module processes the calculation results and outputs them.

[0073] In this embodiment, the circuit also includes a preprocessing module; the preprocessing module is used to preprocess the input initial data according to the configured function type to obtain intermediate data. The preprocessing module can perform operations such as bit expansion, shifting and quadrant processing on the initial data input by the user. By adding the preprocessing module, the hardware circuit based on the CORDIC algorithm is further optimized. Its technical effect is that the preprocessing module performs preprocessing such as bit expansion, quadrant mapping or parameter normalization on the input data according to the configured function type (such as trigonometric function, hyperbolic function or linear function), eliminates the risk of subsequent data calculation overflow and reduces the loss of calculation results to improve data calculation accuracy; combined with the flexible configuration of the control module, the multiplier-free pipeline calculation of the iterative module and the accuracy compensation of the post-processing module, the hardware resource reuse of the whole process is realized.

[0074] During the preprocessing stage, the circuit performs the following operations on the initial input data (X0, Y0, Z0): Bit extension: To detect overflow in subsequent calculations, the input data needs to be bit-extended. The purpose of bit extension is to increase the number of bits in the data so that overflow can be detected during the calculation process. Shifting: To improve data precision, the input data may be shifted. Shifting can retain some decimals in the data during the calculation, thereby achieving higher accuracy in subsequent calculations. Quadrant manipulation: The CORDIC algorithm typically performs calculations in the first quadrant, so it is necessary to rotate the input data from other quadrants (second, third, and fourth quadrants) to the first quadrant. The purpose of quadrant manipulation is to simplify the subsequent calculation process.

[0075] Among them, the preprocessing module refers to the functional unit that converts the format of the input data, which can be implemented by a combination of a data bit expansion circuit, a quadrant converter and a shift register. The module selects the corresponding preprocessing strategy according to the function type, for example, performing quadrant conversion when calculating trigonometric functions. The function type refers to the category of mathematical functions to be calculated, which can be trigonometric functions, hyperbolic functions or linear functions, and the type is identified by the configuration register. The initial data refers to the original calculation parameters input to the CORDIC circuit, for example, it can be fixed-point data containing three dimensions of X, Y, and Z. The intermediate data refers to the standardized data after format conversion, which can be the trigonometric function input parameters with quadrant alignment or the parameters with bit expansion.

[0076] Specifically, the preprocessing module activates the corresponding data processing path according to the function type identifier of the configuration register. When the function type is a trigonometric function, the module converts the input angle parameter from any quadrant to the first quadrant range, for example, subtracting π from the angle value of the second quadrant for conversion. For trigonometric, linear and hyperbolic function calculations, the module performs data bit width expansion operations, such as adding a sign extension bit to the high bit of the original data to prevent overflow errors during the calculation process. The preprocessed intermediate data has a unified format standard and can be directly input into the subsequent iterative operation module for cyclic calculation, eliminating the different requirements for the input data format of different function types. The shift operations in the preprocessing stage are all left shifts.

[0077] In this embodiment, the iterative operation module includes: an input selection unit, a first shift unit, a second shift unit, an addition and subtraction operation unit, and an output selection unit; the input selection unit is used to select initial data in the first iteration and select the result of the previous iteration in subsequent iterations to generate first intermediate data; the first intermediate data includes data in the X direction, data in the Y direction, and data in the Z direction; the first shift unit is used to perform a shift operation on the data in the X direction to obtain second intermediate data; the second shift unit is used to perform a shift operation on the data in the Y direction to obtain third intermediate data; the addition and subtraction operation unit is used to perform the addition and subtraction operation on the first intermediate data, the second intermediate data, the third intermediate data, and the Z direction. The data in the X direction and the data output by the preset lookup table are added or subtracted; the data output by the preset lookup table is determined by the function type and the current number of iterations; the output selection unit is used to select a result from the operation results output by the addition and subtraction operation unit or the result output by the input selection unit according to the operation mode corresponding to the function type and the current number of iterations when performing the operation of the X direction data, and feed it back to the input end of the input selection unit; when performing the operation of the Y and Z direction data, it is used to select a result from the operation results output by the addition and subtraction operation unit according to the operation mode corresponding to the function type and the current number of iterations, and feed it back to the input end of the input selection unit. Through the above technical solution, the present application constructs a universal iteration unit that supports multi-mode operation, solving the problem that traditional CORDIC hardware cannot flexibly configure the function type and number of iterations. Through the dynamic data path selection mechanism, seamless switching between initial data and iterative intermediate results is achieved to ensure the correct execution of different numbers of iterations. The configurable shift unit and mode-related output selection logic are used to meet the special requirements of trigonometric functions, linear functions and hyperbolic functions for shift operations, ensuring the accurate calculation of various mathematical models. The dynamic acquisition method of angle compensation value based on the lookup table effectively supports the parameter differences between rotation mode and vector mode, and improves the reuse efficiency of hardware resources.

[0078] The input selection unit includes a first selector, a second selector, and a third selector. The first selector is used to select the initial data in the X direction during the first iteration, and the data in the X direction from the previous iteration result during subsequent iterations. The second selector is used to select the initial data in the Y direction during the first iteration, and the data in the Y direction from the previous iteration result during subsequent iterations. The third selector is used to select the initial data in the Z direction during the first iteration, and the data in the Z direction from the previous iteration result during subsequent iterations. The input of the first shift unit comes from the X direction data output by the first selector, and the input of the second shift unit comes from the Y direction data output by the second selector.

[0079] The addition and subtraction operation unit includes a first adder, a second adder, a third adder, a first subtractor, a second subtractor, and a third subtractor; the inputs of the first adder and the first subtractor include the X-direction data output by the first selector and the Y-direction shift data output by the second shift unit; the inputs of the second adder and the second subtractor include the Y-direction data output by the second selector and the X-direction shift data output by the first shift unit; the inputs of the third adder and the third subtractor include the Z-direction data output by the third selector and the data output by the preset lookup table.

[0080] The output selection unit includes a fourth selector, a fifth selector, and a sixth selector; the input of the fourth selector includes the output data of the first adder, the output data of the first subtractor, and the X-direction data output by the first selector; the input of the fifth selector includes the output data of the second adder and the output data of the second subtractor; and the input of the sixth selector includes the output data of the third adder and the output data of the third subtractor.

[0081] Iterative calculation is performed on the preprocessed data as follows Figure 2 As shown, Figure 2The part in the box is a circuit for an iterative calculation. In each iteration, this circuit first inputs the pre-processed initial data and the result of the previous iteration into a two-choice selector, namely the first selector 201, the second selector 202 and the third selector 203. The first selector 201, the second selector 202 and the third selector 203 output the initial data in the first operation, and output the result of the previous iteration in subsequent iterative operations. The data X and Y output by the first selector 201 and the second selector 202 are input to the first shift unit 204 and the second shift unit 205 for shifting, respectively. The X output by the first selector 201 and the Y output by the second shift unit 205 are input to the first adder 207 and the first subtractor 208, and then the output result of the first adder 207, the output result of the first subtractor 208 and the first selector 201 are added together. The output X is input to a one-out-of-three selector, namely, the fourth selector 213. The output Y of the second selector 202 and the output X of the first shift unit 204 are input to the second adder 209 and the second subtractor 210. The output of the second adder 209 and the output of the second subtractor 210 are then input to a one-out-of-two fifth selector 214. The output Z of the third selector 203 and the data output of the preset lookup table 206 are input to the third adder 211 and the third subtractor 212. The output of the third adder 211 and the output of the third subtractor 212 are then input to a one-out-of-two sixth selector 215. Finally, the outputs of the fourth selector 213, the fifth selector 214, and the sixth selector 215 are returned to the inputs of the first selector 201, the second selector 202, and the third selector 203, respectively, completing one iteration. Finally, all iterative calculations are executed according to the configured number of iterations. The MUX (Multiplexer) is a multiplexer used to select an output from multiple input signals, with the selected output determined by a control signal (such as the Mode signal). The LUT (Look-Up Table) is a lookup table that stores preset fixed data (such as trigonometric function values) and allows for fast table lookup and output of the result via an input address. The shifter is a shifter that performs left or right shifts on binary data (such as bit shifts in multiplication or division). Iteration times are the number of times an algorithm (such as CORDIC) loops, affecting computational accuracy. Z0 / Y0 / X0 are initial input values, which may represent the initial values ​​of the angle (Z) or coordinates (X, Y). Mode is a control signal that determines the circuit's operating mode (such as rotation mode or vector mode). This circuit is a typical CORDIC (Coordinate Rotation Digital Computing) algorithm implementation, used for calculating trigonometric functions, vector rotations, or hyperbolic functions. Its core modules and process are as follows: Input module: X0 / Y0 / Z0: Initial coordinates (X, Y) and angle (Z), inputs are selected via the MUX signal.Mode: Controls the algorithm mode (e.g., rotation mode calculates angles, vector mode calculates amplitudes). Iterationtimes: Sets the number of iterations (usually related to accuracy). Core arithmetic unit: LUT (206 / 212, etc.): Stores pre-calculated rotation angles (e.g., arctan(2^-i)) for query during iteration. Shifter (209, etc.): Shifts the X / Y data sequentially (corresponding to the 2^-i scaling in rotation). Addition and subtraction (+ / - module): Updates the X / Y / Z values ​​according to the rotation direction (e.g., X ← X ± Y>>i). Data path control: Multiplexer (MUX): Selects the intermediate value or initial value input in the iteration. Quadrant preprocessing (215): Converts the input angle to the first quadrant to simplify the calculation. Overflow / truncation processing: Prevents overflow and retains the valid bit width. Output processing: The final output X / Y may be the rotated coordinates or trigonometric function values ​​(e.g., cos / sin), and Z may be the remaining angle or amplitude.

[0082] In this embodiment, the post-processing module includes a bit truncation processing unit, an overflow judgment unit and a quadrant recovery unit; the bit truncation processing unit is used to perform a bit truncation processing operation on the data after the iteration is completed; the overflow judgment unit is used to perform an overflow judgment operation on the data after the bit truncation processing; the quadrant recovery unit is used to perform a quadrant recovery processing operation on the data after the overflow judgment. After completing the set number of iterations, the post-processing module performs a bit truncation processing on the calculation result to eliminate redundant data, and corrects the sign and numerical range of the calculation result through the quadrant recovery unit. The data after the iteration is subjected to bit truncation, overflow judgment and quadrant recovery processing. The overflow judgment method here is to judge whether the extended high bit is consistent with the sign bit. If they are consistent, the result does not overflow. If they are inconsistent, the result overflows. If you want to prevent overflow, you can configure an anti-overflow result coefficient. At this time, the data after the iteration will be proportionally reduced according to the configured coefficient so that the final result does not overflow.

[0083] Specifically, the post-processing process is executed in a fixed order of bit truncation, overflow judgment, and quadrant recovery. First, the bit truncation processing unit compresses the bit width of the iterative result, for example, truncating the 32-bit intermediate data to 16 bits of valid data to eliminate the invalid low bits generated by the pre-processing bit expansion. The overflow judgment unit then compares the sign bit of the truncated data. When it detects that the sign bit does not match the high-bit data, an overflow alarm signal is triggered. At this time, dynamic proportional adjustment can be performed according to the configured anti-overflow coefficient. Finally, the quadrant recovery unit applies an angle compensation operation to the processed data based on the quadrant conversion parameters stored in the pre-processing stage. For example, when calculating trigonometric functions, a 180-degree phase compensation is performed on the result in the second quadrant, so that the output result is mapped back to the correct quadrant where the original data is located.

[0084] Through the above technical solutions, this application solves the three major technical problems of precision redundancy, numerical out-of-bounds, and spatial offset in iterative results. The bit truncation unit ensures that the output data meets the target precision specification to avoid resource waste; the overflow judgment unit actively identifies and handles numerical anomalies to prevent the output of erroneous results; the quadrant recovery unit corrects the spatial errors caused by the calculation range limitations of the algorithm to ensure the geometric correctness of the calculation results. The three work together to enable the hardware implementation of the CORDIC algorithm to have the comprehensive capabilities of adaptive precision adjustment, active safety protection, and spatial mapping correction.

[0085] In this embodiment, the control module can also be used to update target configuration information based on user selection. Updating target configuration information based on user selection refers to modifying the function type, operation mode, or number of iterations in real time according to external input instructions. This can be achieved by using a bus interface to receive register write operations, and by changing the operation parameters by configuring the numerical mapping relationship of the registers. The number of iterations is configured to control the balance between calculation accuracy and operation speed, the function type is configured to switch between different mathematical operation modes, and the operation mode is configured to determine the rotation direction or vector processing method. This dynamic configuration mechanism enables the hardware circuit to respond to external control signals to reset parameters during operation, and can adapt to a variety of application scenarios without redesigning the circuit structure.

[0086] Through the above technical solution, this application solves the problem of poor scenario adaptability caused by the fixed parameters of traditional CORDIC hardware circuits, and achieves a dynamic balance between calculation accuracy and operation speed. Users can flexibly configure the number of iterations according to actual application needs.

[0087] Example 2

[0088] Corresponding to the aforementioned circuit embodiment of the CORDIC algorithm, the present disclosure also provides an embodiment of an operation method based on the CORDIC algorithm.

[0089] Figure 3 This is a flow chart of an operation method based on the CORDIC algorithm provided in an embodiment of the present disclosure. The operation method is used to control the circuit based on the CORDIC algorithm as described above. The operation method includes:

[0090] S101: receiving configuration parameters input by a user and generating target configuration information based on the configuration parameters; the configuration parameters include a function type, an operation mode corresponding to the function type, and a number of iterations;

[0091] S102: performing iterative calculation on the pre-processed intermediate data based on the target configuration information to obtain target data;

[0092] S103: Post-process the target data obtained after the iteration and output the processed results.

[0093] Specifically, in various application fields such as communications and aerospace that require the calculation of trigonometric, linear, and hyperbolic functions, it is difficult to directly use hardware to implement function calculations. The emergence of the CORDIC algorithm has solved this problem well. The algorithm uses operations that are easy to implement in hardware, such as addition, subtraction, and shifting, to complete the above-mentioned complex function calculations, and has extremely high application value.

[0094] This disclosure proposes a CORDIC hardware implementation circuit with configurable accuracy for various applications with different requirements for computational accuracy. The specific implementation steps are as follows:

[0095] (1) The CORDIC hardware implementation circuit disclosed in this disclosure is a peripheral of the Advanced High-performance Bus (AHB). Therefore, when using it, the registers must first be configured through the AHB bus, including the type of function to be calculated, the data to be calculated, and the required number of iterations.

[0096] (2) After the configuration is completed, the circuit preprocesses the input data.

[0097] (3) The circuit performs iterative calculations on the pre-processed data for a set number of times.

[0098] (4) After the iteration is completed, the iterative result is restored to obtain the final calculation result, which is read out through the AHB bus.

[0099] Example 3

[0100] Figure 4 This is a structural diagram of an electronic device provided in an embodiment of the present disclosure. The electronic device includes a memory, a processor, and a computer program stored in the memory and used to run on the processor. When the processor executes the computer program, the CORDIC algorithm-based operation method described in any of the above embodiments is implemented. Figure 4 The electronic device 40 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0101] like Figure 4 As shown, the electronic device 40 may be a general-purpose computing device, such as a server device. Components of the electronic device 40 may include, but are not limited to, the at least one processor 41, the at least one memory 42, and a bus 43 connecting different system components (including the memory 42 and the processor 41).

[0102] The bus 43 includes a data bus, an address bus, and a control bus.

[0103] The memory 42 may include a volatile memory, such as a random access memory (RAM) 421 and / or a cache memory 422 , and may further include a read-only memory (ROM) 423 .

[0104] The memory 42 may also include a program tool 425 (or utility) having a set (at least one) of program modules 424, such program modules 424 including but not limited to: an operating system, one or more application programs, other program modules and program data, each of which or some combination may include an implementation of a network environment.

[0105] The processor 41 executes various functional applications and data processing by running the computer program stored in the memory 42, such as the CORDIC algorithm-based operation method provided in any of the above embodiments.

[0106] The electronic device 40 can also communicate with one or more external devices 44 (e.g., a keyboard, pointing device, etc.). This communication can be performed via an input / output (I / O) interface 45. Furthermore, the electronic device 40 can also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 46. As shown, the network adapter 46 communicates with other modules of the electronic device 40 via a bus 43. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the electronic device 40, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (RAID) systems, tape drives, and data backup storage systems.

[0107] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided and embodied by multiple units / modules.

[0108] Example 4

[0109] An embodiment of the present disclosure further provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the operation method based on the CORDIC algorithm provided in any of the above embodiments is implemented.

[0110] The readable storage medium may include, but is not limited to, a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0111] Example 5

[0112] An embodiment of the present disclosure further provides a computer program product, including a computer program, which implements any of the above-mentioned CORDIC algorithm-based operation methods when executed by a processor.

[0113] The program code for executing the computer program product of the present disclosure may be written in any combination of one or more programming languages, and the program code may be executed entirely on the user device, partially on the user device, as a standalone software package, partially on the user device and partially on a remote device, or entirely on the remote device.

[0114] While specific embodiments of the present disclosure have been described above, those skilled in the art will appreciate that these are merely illustrative and that the scope of protection of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, and such changes and modifications are intended to fall within the scope of protection of the present disclosure.

Claims

1. A circuit based on the CORDIC algorithm, characterized in that: The circuit includes: a control module, an iterative operation module and a post-processing module; The control module is configured to generate target configuration information to configure the function type included in the iterative operation module, the operation mode corresponding to the function type, and the number of iterations; The iterative calculation module is used to perform iterative calculation on the pre-processed intermediate data based on the target configuration information to obtain target data; The post-processing module is used to post-process the target data obtained through iteration and output the processed results.

2. The circuit based on the CORDIC algorithm according to claim 1, wherein: The circuit further includes a pre-processing module; The preprocessing module is used to preprocess the input initial data according to the configured function type to obtain the intermediate data.

3. The circuit based on the CORDIC algorithm according to claim 2, wherein: The iterative operation module includes: an input selection unit, a first shift unit, a second shift unit, an addition and subtraction operation unit and an output selection unit; The input selection unit is configured to select the initial data in a first iteration and select the result of the previous iteration in subsequent iterations to generate first intermediate data; the first intermediate data includes data in the X direction, data in the Y direction, and data in the Z direction; The first shift unit is configured to perform a shift operation on the data in the X direction to obtain second intermediate data; The second shift unit is configured to perform a shift operation on the data in the Y direction to obtain third intermediate data; The addition and subtraction operation unit is used to perform addition and subtraction operations on the first intermediate data, the second intermediate data, the third intermediate data, the data in the Z direction, and data output by a preset lookup table; the data output by the preset lookup table is determined by the function type and the current number of iterations; The output selection unit is used, when performing an operation on X-direction data, to select a result from the operation results output by the addition and subtraction operation unit or from the results output by the input selection unit according to the operation mode corresponding to the function type and the current number of iterations, and feed the result back to the input end of the input selection unit; when performing an operation on Y- and Z-direction data, the output selection unit is used to select a result from the operation results output by the addition and subtraction operation unit according to the operation mode corresponding to the function type and the current number of iterations, and feed the result back to the input end of the input selection unit.

4. The circuit based on the CORDIC algorithm according to claim 3, wherein: The input selection unit includes a first selector, a second selector and a third selector; The first selector is used to select the initial data in the X direction in the first iteration, and to select the data in the X direction in the previous iteration result in subsequent iterations; The second selector is used to select the initial data in the Y direction in the first iteration, and select the data in the Y direction in the previous iteration result in subsequent iterations; The third selector is used to select the initial data in the Z direction in the first iteration, and to select the data in the Z direction in the result of the previous iteration in subsequent iterations.

5. The circuit based on the CORDIC algorithm according to claim 4, wherein: The input of the first shift unit comes from the X-direction data output by the first selector, and the input of the second shift unit comes from the Y-direction data output by the second selector.

6. The circuit based on the CORDIC algorithm according to claim 4, wherein: The addition and subtraction operation unit includes a first adder, a second adder, a third adder, a first subtractor, a second subtractor and a third subtractor; The inputs of the first adder and the first subtractor include the X-direction data output by the first selector and the Y-direction shift data output by the second shift unit; The inputs of the second adder and the second subtractor include the Y-direction data output by the second selector and the X-direction shift data output by the first shift unit; The inputs of the third adder and the third subtractor include the data in the Z direction output by the third selector and the data output by the preset lookup table; The output selection unit includes a fourth selector, a fifth selector and a sixth selector; The input of the fourth selector includes the output data of the first adder, the output data of the first subtractor and the X-direction data output by the first selector; The input of the fifth selector includes the output data of the second adder and the output data of the second subtractor; An input of the sixth selector includes output data of the third adder and output data of the third subtractor.

7. The circuit based on the CORDIC algorithm according to any one of claims 1 to 6, characterized in that: The function types include trigonometric functions, linear functions, and hyperbolic functions; The modes corresponding to the trigonometric function, the linear function and the hyperbolic function are rotation modes or vector modes.

8. The circuit based on the CORDIC algorithm according to claim 1, wherein: The control module is further configured to update the target configuration information based on a user's selection.

9. The circuit based on the CORDIC algorithm according to claim 1, wherein: The post-processing module includes a bit truncation processing unit, an overflow judgment unit and a quadrant recovery unit; The bit truncation processing unit is used to perform a bit truncation processing operation on the data after the iteration; The overflow judgment unit is used to perform an overflow judgment operation on the data after the bit truncation processing; The quadrant recovery unit is used to perform a quadrant recovery processing operation on the data after overflow judgment.

10. A calculation method based on the CORDIC algorithm, characterized in that: The operation method is used to control a circuit based on a CORDIC algorithm according to any one of claims 1 to 9, and the operation method includes: Receive configuration parameters input by a user and generate target configuration information based on the configuration parameters; the configuration parameters include a function type, an operation mode corresponding to the function type, and a number of iterations; Iteratively calculating the preprocessed intermediate data based on the target configuration information to obtain target data; Post-process the target data obtained after iteration, and output the processed results.

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