Memory
By using NMOS tubes as selection tubes and PMOS tubes as storage tubes in the memory and independently setting back gate electrodes, the programming interference and large area problems of existing memories are solved, and a smaller selection tube size and less decoder area are achieved.
Patent Information
- Application Number
- CN202510630789.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-15
- Publication Date
- 2025-09-05
AI Technical Summary
Existing memories are prone to program disturbance and have a large area.
NMOS tubes are used as selection tubes, PMOS tubes are used as storage tubes, the source of the selection tube is used as the bit line end, the source of the storage tube is used as the source line end, and the selection tube is placed in the NMOS group, the storage tube is placed in the PMOS group, and the back gate electrode is set independently to reduce programming interference.
The area of the memory and the programming interference are reduced, the size requirement of the selection tube is lowered, and the area of the decoder is reduced.
Smart Images
Figure CN120600071A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor integrated circuit, and in particular to a memory. Background Art
[0002] Existing memories include OTP memories using one-time programmable (OTP) cells. Figure 1 As shown in FIG. , it is the layout of the OTP unit of the existing memory; Figure 2 As shown in FIG. , it is a circuit diagram of an OTP unit of an existing memory; Figure 3 , which is a circuit diagram of a memory array of an existing memory; the OTP unit 101 is composed of two PMOS tubes connected in series, one of which is a selection tube 202 and the other is a storage tube 203.
[0003] like Figure 1 As shown, the selection transistor 202 and the storage transistor 203 are formed in the same active region 104, and the active region 104 is composed of an N-type well region. Figure 2 As shown, the N-type well region is connected to the N-well electrode VNW, and the N-type well regions of all the OTP cells 101 in the memory array are connected to the N-well electrode VNW.
[0004] The gate 105 of the selection transistor 202 is a selection gate (SG).
[0005] The gate 106 of the storage transistor 203 is a floating gate (FG).
[0006] The source and drain regions of the select transistor 202 are self-aligned in the active region 104 on both sides of the gate 105. The source and drain regions of the storage transistor 203 are self-aligned in the active region 104 on both sides of the gate 106. The drain region of the select transistor 202 and the source region of the storage transistor 203 are shared; the source region of the select transistor 202 is connected to the source line VSL. Figure 3 In the embodiment, the source lines VSL of all the selection transistors 202 are connected together.
[0007] The drain region of the storage transistor 203 is connected to the corresponding bit line VBL. Figure 3 In FIG. 1 , multiple rows of bit lines are shown, such as bit line VBL. <1> 、VBL <2> 、VBL <3> and VBL <4> .
[0008] The electrode terminal VSG of the gate 105 of the selection transistor 202 is connected to the word line VWL. Figure 3 In FIG. 1 , multiple columns of word lines are shown, such as word line VWL. <1> 、VWL <2> and VWL <3> .
[0009] Existing memories are prone to program disturb, as explained below:
[0010] Figure 3 In the embodiment, the OTP cell selected for reading or programming is individually indicated by a mark 101a, and the three OTP cells adjacent to the selected OTP cell 101a are indicated by marks 101b, 101c, and 101d, respectively. The OTP cell 101b is located in the same row as the OTP cell 101a, the OTP cell 101c is located in the same column as the OTP cell 101a, the OTP cell 101d is located in the same column as the OTP cell 101b, and the OTP cell 101d is located in the same row as the OTP cell 101c.
[0011] Table 1
[0012]
[0013] As shown in Table 1, Program in Table 1 indicates programming, selected cell indicates the selected OTP cell 101a, and unselected cell indicates the unselected OTP cell; the four OTP cells in Table 1 are numbered 1, 2, 3, and 4, respectively. The first OTP cell is located in the selected OTP cell 101a; the other three OTP cells are unselected OTP cells, namely: Figure 3 The third OTP unit 101b is Figure 3 The fourth OTP unit 101c is Figure 3 VWL represents the voltage of the word line of the corresponding OTP cell, VBL represents the voltage of the bit line of the corresponding OTP cell, VSL represents the voltage of the source line, and VNW represents the voltage of the N-well electrode.
[0014] It can be seen that when programming, the VWL corresponding to the first OTP unit is Figure 3 VWL <2> , the applied voltage is 0V; the VBL corresponding to the first OTP unit is Figure 3 VBL in <2> , the applied voltage is 0V, the voltage of VSL is the programming voltage (VPP), the voltage of VNW is also VPP, and VPP is a high voltage greater than the power supply voltage. Figure 3 It can be seen that the selection tube of the OTP unit 101a will be turned on, the high voltage of VSL will be transmitted to the source region of the storage tube of the OTP unit 101a, and the gate-source coupling will turn on the storage tube of the OTP unit 101a. Finally, under the action of the high voltage of the source region of the storage tube and the high voltage of VNW, the floating gate of the OTP unit 101a is programmed by hot electron injection.
[0015] Compared with the first OTP unit, the VWL corresponding to the second OTP unit is Figure 3 VWL <3> , the applied voltage is VPP. The voltage of VBL of the second OTP unit is the same as the voltage of VBL of the first OTP unit. The second OTP unit will generate programming interference. This is mainly because, although the VWL corresponding to the second OTP unit is VPP, the selection tube of the second OTP unit will be turned off. However, in fact, the selection tube of the second OTP unit is prone to leakage, especially at high temperatures. The leakage of the selection tube of the second OTP unit can affect the storage information of the storage tube of the second OTP unit, thereby generating programming interference.
[0016] Compared with the first OTP unit, the voltage of VWL of the third OTP unit is the same as the voltage of VWL of the first OTP unit, and the VBL of the third OTP unit is Figure 3 VBL in <3> , the applied voltage is VPP.
[0017] The voltage of VWL of the fourth OTP cell is the same as the voltage of VWL of the second OTP cell, and the voltage of VBL of the fourth OTP cell is the same as the voltage of VBL of the third OTP cell.
[0018] Table 2
[0019]
[0020] The "read" in Table 2 represents a read operation. In Table 2, the first to fourth OTP units are the same as those in Table 1. The corresponding voltages during reading are shown in Table 2, and the unit of each voltage is V. Summary of the Invention
[0021] To solve the above technical problems, the present invention provides a memory that can reduce the memory area and lower program disturbance.
[0022] In order to solve the above technical problems, the memory provided by the present invention includes a storage array composed of a plurality of OTP units.
[0023] The OTP unit includes a selection tube composed of an NMOS tube and a storage tube composed of a PMOS tube.
[0024] The source of the selection tube serves as the bit line terminal of the OTP unit.
[0025] The drain of the selection tube is connected to the drain of the storage tube.
[0026] The source of the storage tube serves as the source line end of the OTP unit.
[0027] The gate of the selection tube serves as the selection gate of the OTP unit, and the gate of the storage tube is a floating gate.
[0028] The memory array includes an NMOS group and a PMOS group.
[0029] Each of the selection tubes is formed in the NMOS group.
[0030] Each of the storage transistors is formed in the PMOS group.
[0031] The programming voltage of the OTP unit is greater than the power supply voltage, the maximum voltage of the voltage domain of the NMOS group is the power supply voltage; the maximum voltage of the voltage domain of the PMOS group is the programming voltage.
[0032] A further improvement is that the NMOS group is formed in a P-type semiconductor substrate; the P-type semiconductor substrate is connected to a substrate electrode, and the substrate electrode serves as a back gate electrode of each of the selection transistors.
[0033] A further improvement is that the PMOS group is formed in an N-type well, which is located in the P-type semiconductor substrate; the N-type well is connected to an N-well electrode, which serves as a back gate electrode of each storage transistor;
[0034] A further improvement is that the NMOS group includes a plurality of NMOS columns, and each of the NMOS columns includes a plurality of the selection tubes.
[0035] The gates of the selection transistors in the same NMOS column are connected together.
[0036] A further improvement is that, in the NMOS group, the selection tubes located in each NMOS column are arranged into multiple rows, and the selection tubes in the same row are aligned.
[0037] A further improvement is that the PMOS group includes a plurality of storage tubes, and the storage tubes are arranged in multiple rows and columns.
[0038] A further improvement is that the area of the selection tube is smaller than the area of the storage tube, and the area of the NMOS group is smaller than the area of the PMOS group.
[0039] A further improvement is that each of the OTP units is formed by connecting the selection tube in the NMOS group and the corresponding storage tube in the PMOS group.
[0040] In the memory array, the gates of the selection transistors of the OTP units in the same column are connected to the word lines in the same column.
[0041] The sources of the selection transistors of the OTP units in the same row are connected to the bit lines of the same row.
[0042] The source of the storage transistor of each of the OTP units is connected to a source line.
[0043] A further improvement is that, during programming, the selected OTP unit is a programming unit, and the voltage applied to the programming unit includes:
[0044] The voltage of the word line is the power supply voltage.
[0045] The voltage of the bit line is a first voltage, which is a positive voltage and is lower than the power supply voltage.
[0046] The voltage of the source line is the programming voltage, and the voltage of the N-well electrode is the programming voltage.
[0047] A further improvement is that, during programming, the voltage of the word line of each non-selected OTP unit in a different column from the programming unit is 0V.
[0048] A further improvement is that, during reading, the voltage applied to the selected OTP unit includes:
[0049] The voltage of the word line is the power supply voltage.
[0050] The voltage of the bit line is the power supply voltage minus a first bias voltage. The first bias voltage is the gate-source voltage of the selection tube. The first bias voltage is greater than or equal to the threshold voltage of the selection tube to ensure that the selection tube is turned on.
[0051] The voltage of the source line is the power supply voltage, and the voltage of the N-well electrode is the power supply voltage.
[0052] A further improvement is that the gate of the selection tube is made of polysilicon, and a first gate dielectric layer is formed at the bottom of the gate of the selection tube.
[0053] A further improvement is that the gate of the storage tube is made of polysilicon, and a second gate dielectric layer is formed at the bottom of the gate of the storage tube.
[0054] A further improvement is that the material of the first gate dielectric layer includes an oxide layer.
[0055] The material of the second gate dielectric layer includes an oxide layer.
[0056] A further improvement is that, during programming, each non-selected OPT cell in a different column and the same row as the programming cell is a program disturb cell.
[0057] The voltage of the substrate electrode is lower than the first voltage.
[0058] The present invention first makes special arrangements for the OTP unit, wherein the selection tubes are NMOS tubes and the storage tubes are PMOS tubes. Furthermore, the present invention also makes special arrangements for the storage array, wherein the selection tubes are all placed in the NMOS group and the storage tubes are all placed in the PMOS group. The present invention also uses the source of the selection tube as the bit line terminal and the source of the storage tube as the source line terminal. This connection structure enables the maximum voltage of the selection tube during read and write operations to be the power supply voltage, without being subjected to a large programming voltage. Since the size of the selection tube needs to meet voltage resistance requirements, the larger the operating voltage, the larger the size of the selection tube is required to be, and vice versa. Therefore, the size of the selection tube of the present invention can be made small. When all the selection tubes are placed in the NMOS group, the area of the NMOS group can be greatly reduced. At the same time, the area of the decoder required for decoding the selection gate, that is, the word line, is also reduced, thereby ultimately reducing the area of the memory.
[0059] In the present invention, since an NMOS tube is used as a selection tube, compared with a PMOS tube, the back gate electrode of the selection tube and the back gate electrode of the storage tube can be independently set. In this way, by setting the voltage of the back gate electrode of the selection tube, the leakage of each selection tube in a different column from the programming unit can be greatly reduced during programming, thereby reducing programming interference. BRIEF DESCRIPTION OF THE DRAWINGS
[0060] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0061] Figure 1 This is the layout of the OTP unit of the existing memory;
[0062] Figure 2 This is a circuit diagram of an OTP unit of an existing memory;
[0063] Figure 3 It is a circuit diagram of a memory array of an existing memory;
[0064] Figure 4 is a circuit diagram of an OTP unit of a memory according to an embodiment of the present invention;
[0065] Figure 5 is a layout of a memory array of a memory according to an embodiment of the present invention;
[0066] Figure 6 It is along Figure 5 Schematic diagram of the cross-sectional structure of the selection tube at the center line AA;
[0067] Figure 7 It is along Figure 5 Schematic diagram of the cross-sectional structure of the storage tube at the center line BB. DETAILED DESCRIPTION
[0068] like Figure 4 , which is a circuit diagram of an OTP unit 201 of a memory according to an embodiment of the present invention; the memory according to the embodiment of the present invention includes a storage array composed of a plurality of OTP units 201 .
[0069] The OTP unit 201 includes a selection transistor 202 composed of an NMOS transistor and a storage transistor 203 composed of a PMOS transistor.
[0070] The source of the selection transistor 202 serves as the bit line terminal BL of the OTP unit 201 .
[0071] The drain of the selection tube 202 is connected to the drain of the storage tube 203 .
[0072] The source of the storage transistor 203 serves as the source line terminal SL of the OTP unit 201 .
[0073] The gate 305 of the selection transistor 202 serves as the selection gate SG of the OTP unit 201 , and the gate 308 of the storage transistor 203 is a floating gate.
[0074] like Figure 5 , which is a layout of a memory array of a memory according to an embodiment of the present invention; the memory array includes an NMOS group 301 and a PMOS group 302 .
[0075] Each of the selection transistors 202 is formed in the NMOS group 301 .
[0076] Each of the storage transistors 203 is formed in the PMOS group 302 .
[0077] The programming voltage of the OTP unit 201 is greater than the power supply voltage. The maximum voltage of the voltage domain of the NMOS group 301 is the power supply voltage; the maximum voltage of the voltage domain of the PMOS group 302 is the programming voltage.
[0078] In the embodiment of the present invention, Figure 6 As shown, it is along Figure 5 Schematic diagram of the cross-sectional structure of the selection tube at the center line AA; the NMOS group 301 is formed in the P-type semiconductor substrate 401. Back Figure 4 As shown, the P-type semiconductor substrate 401 is connected to a substrate electrode Psub, and the substrate electrode Psub serves as a back gate electrode of each of the selection transistors 202 .
[0079] like Figure 6 As shown, a field oxide 402 is further formed in the P-type semiconductor substrate 401 , and the field oxide 402 is usually formed using shallow trench isolation (STI). Figure 6In the embodiment, the selection tube 202 forms a first active region 304 , and the field oxide 402 is formed around the first active region 304 , that is, the P-type semiconductor substrate 401 between the field oxide 402 constitutes the first active region 304 . Figure 5 The first active region 304 corresponding to each selection transistor 202 is also shown.
[0080] In this embodiment of the present invention, the gate 305 of the select transistor 202 is made of polysilicon, and a first gate dielectric layer 404 is formed at the bottom of the gate 305 of the select transistor 202. A first source / drain region 403a and a second source / drain region 403b are formed on either side of the gate 305 of the select transistor 202. The first source / drain region 403a and the second source / drain region 403b of the select transistor 202 are symmetrically arranged. When the first source / drain region 403a serves as the source region of the select transistor 202, the second source / drain region 403b serves as the drain region of the select transistor 202, and vice versa. The electrode connected to the source region of the select transistor 202 is the source electrode, and the electrode connected to the drain region of the select transistor 202 is the drain electrode.
[0081] In some embodiments, the material of the first gate dielectric layer 404 includes an oxide layer.
[0082] In the embodiment of the present invention, the PMOS group 302 is formed in the N-type well 306. Figure 7 As shown, it is along Figure 5 Schematic diagram of the cross-sectional structure of the storage tube at the center line BB; the N-type well 306 is located in the P-type semiconductor substrate 401; the N-type well 306 is connected to the N-well electrode NW, and the N-well electrode NW serves as the back gate electrode of each of the storage tubes 203.
[0083] In the embodiment of the present invention, the gate 308 of the storage tube 203 is made of polysilicon, and a second gate dielectric layer 405 is formed at the bottom of the gate 308 of the storage tube 203 .
[0084] A first source / drain region 406a and a second source / drain region 406b are formed on either side of the gate 308 of the storage transistor 203. The first source / drain region 406a and the second source / drain region 406b of the storage transistor 203 are symmetrically arranged. When the first source / drain region 406a serves as the source region of the storage transistor 203, the second source / drain region 406b serves as the drain region of the storage transistor 203, and vice versa. The electrode connected to the source region of the storage transistor 203 is called the source electrode, and the electrode connected to the drain region of the storage transistor 203 is called the drain electrode.
[0085] In some embodiments, the material of the second gate dielectric layer 405 includes an oxide layer.
[0086] In the embodiment of the present invention, Figure 5As shown, the NMOS group 301 includes a plurality of NMOS columns 303 , and each of the NMOS columns 303 includes a plurality of the selection transistors 202 .
[0087] The gates 305 of the selection transistors 202 in the same NMOS column 303 are connected together.
[0088] In the NMOS group 301 , the selection tubes 202 in the NMOS columns 303 are arranged in multiple rows, and the selection tubes 202 in the same row are aligned.
[0089] The PMOS group 302 includes a plurality of storage transistors 203 , and the storage transistors 203 are arranged in multiple rows and columns.
[0090] In some embodiments, as Figure 5 As shown, the PMOS group 302 is composed of multiple memory transistor assemblies 307. Each memory transistor assembly 307 includes two memory transistors 203. A contact hole 310 is formed in the middle region of the memory transistor assembly 307. The bottom of the contact hole 310 is connected to the N-type well 306, and the top of the contact hole 310 is connected to an electrode 311 formed from a front metal layer. Electrode 311 serves as the N-well electrode NW. The memory transistor assembly 307 also includes four symmetrically arranged P+ doped regions 309. Figure 7 The first source-drain region 406 a and the second source-drain region 406 b of the corresponding storage tube 203 are composed of the P+ doped regions 309 at corresponding positions.
[0091] The area of the selection tube 202 is smaller than that of the storage tube 203, and the area of the NMOS group 301 is smaller than that of the PMOS group 302. Figure 5 As shown, in the NMOS group 301, the number of the selection tubes 202 in 8 columns × 4 rows is 32, in the PMOS group 302, the number of the storage tube combinations 307 is 16, and the number of the storage tubes 203 is also 32. However, the area occupied by the NMOS group 301 is significantly smaller.
[0092] Each of the OTP units 201 is formed by connecting the selection transistor 202 in the NMOS group 301 and the corresponding storage transistor 203 in the PMOS group 302 . Figure 5 In the embodiment, the drain of each selection transistor 202 in the NMOS group 301 is connected to the drain of the corresponding storage transistor 203 in the PMOS group 302 through a metal interconnection line. Figure 5 The metal interconnects are not shown.
[0093] In the memory array, the gates 305 of the selection transistors 202 of the OTP units 201 in the same column are connected to the word lines in the same column.
[0094] The sources of the selection transistors 202 of the OTP cells 201 in the same row are connected to the bit lines of the same row.
[0095] The source of the storage transistor 203 of each OTP unit 201 is connected to a source line.
[0096] During programming, the selected OTP unit 201 is a programming unit, and the voltage applied to the programming unit includes:
[0097] The voltage of the word line is the power supply voltage.
[0098] The voltage of the bit line is a first voltage, which is a positive voltage and is less than the power supply voltage. In some embodiments, the first voltage is 0.3V
[0099] The voltage of the source line is the programming voltage, and the voltage of the N-well electrode NW is the programming voltage.
[0100] During programming, the voltage of the word line of each non-selected OTP cell 201 in a different column from the programming cell is 0V.
[0101] During programming, each non-selected OPT cell in a different column and the same row as the programming cell serves as a program disturb cell. The voltage of the substrate electrode Psub is lower than the first voltage to reduce leakage current of the select transistor 202 of the program disturb cell, thereby reducing program disturb on the storage transistor 203 of the program disturb cell.
[0102] During reading, the voltage applied to the selected OTP unit 201 includes:
[0103] The voltage of the word line is the power supply voltage.
[0104] The voltage of the bit line is the power supply voltage minus a first bias voltage. The first bias voltage is the gate-source voltage of the selection transistor 202. The first bias voltage is greater than or equal to the threshold voltage of the selection transistor 202 to ensure that the selection transistor 202 is turned on.
[0105] The voltage of the source line is the power supply voltage, and the voltage of the N-well electrode NW is the power supply voltage.
[0106] Please refer to Table 3 for the voltages applied during programming and reading:
[0107] Table 3
[0108]
[0109]
[0110] In Table 3, "read" represents a read operation on the selected OTP cell 201; "PGM" represents a programming operation on the programming cell; "PGM disturb" represents the voltage applied to the unselected OTP cell 201 in the same row but different column as the programming cell, i.e., the program disturb cell, during the programming operation on the programming cell; "VDD" represents the power supply voltage; "bias" represents the first bias voltage; and "VPP" represents the programming voltage, with 0.3V being the first voltage. "SG" represents the select gate of the corresponding OTP cell 201. Since "SG" is connected to the word line, the voltage of "SG" also represents the voltage of the corresponding word line; "BL" represents the bit line terminal of the corresponding OTP cell 201. Since "BL" is connected to the corresponding bit line, the voltage of "BL" also represents the voltage of the corresponding bit line; and "SL" represents the source line terminal of the OTP cell 201. Since the source line terminals of all OTP cells 201 are connected to the source line, the voltage of "SL" also represents the voltage of the source line. "NW" represents the N-well electrode. The N-well electrodes of all OTP cells 201 are connected together.
[0111] The embodiment of the present invention first makes special arrangements for the OTP unit 201, employing an NMOS transistor for the select transistor 202 and a PMOS transistor for the storage transistor 203. Furthermore, the memory array is specially configured, with all select transistors 202 placed in the NMOS group 301 and all storage transistors 203 placed in the PMOS group 302. In the embodiment of the present invention, the source of the select transistor 202 serves as the bit line terminal BL, and the source of the storage transistor 203 serves as the source line terminal SL. This connection structure ensures that the maximum voltage of the select transistor 202 during read and write operations is the power supply voltage, without being subjected to large programming voltages. Since the size of the select transistor 202 must meet withstand voltage requirements, the larger the operating voltage, the larger the size of the select transistor 202. Therefore, the size of the select transistor 202 in the embodiment of the present invention can be reduced. Placing all select transistors 202 in the NMOS group 301 significantly reduces the area of the NMOS group 301. Simultaneously, the area of the decoder required to decode the select gate SG, i.e., the word line, is also reduced, ultimately reducing the area of the memory.
[0112] In the embodiment of the present invention, since an NMOS transistor is used as the selection transistor 202, compared with a PMOS transistor used as the selection transistor 202, the back gate electrode of the selection transistor 202 and the back gate electrode of the storage transistor 203 in the embodiment of the present invention can be independently set. In this way, by setting the voltage of the back gate electrode of the selection transistor 202, the leakage of each selection transistor 202 in a different column from the programming unit can be greatly reduced during programming, thereby reducing program interference.
[0113] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.
Claims
1. A memory, characterized in that: including a storage array composed of a plurality of OTP units; The OTP unit includes a selection tube composed of an NMOS tube and a storage tube composed of a PMOS tube; The source of the selection tube serves as the bit line terminal of the OTP unit; The drain of the selection tube is connected to the drain of the storage tube; The source electrode of the storage tube serves as the source line terminal of the OTP unit; The gate of the selection tube serves as the selection gate of the OTP unit, and the gate of the storage tube is a floating gate; The memory array includes an NMOS group and a PMOS group; Each of the selection tubes is formed in the NMOS group; Each of the storage transistors is formed in the PMOS group; The programming voltage of the OTP unit is greater than the power supply voltage, the maximum voltage of the voltage domain of the NMOS group is the power supply voltage; the maximum voltage of the voltage domain of the PMOS group is the programming voltage.
2. The memory according to claim 1, wherein: The NMOS group is formed in a P-type semiconductor substrate; the P-type semiconductor substrate is connected to a substrate electrode, and the substrate electrode serves as a back gate electrode of each selection transistor.
3. The memory according to claim 2, wherein: The PMOS group is formed in an N-type well, which is located in the P-type semiconductor substrate; the N-type well is connected to an N-well electrode, which serves as a back gate electrode of each storage transistor.
4. The memory according to claim 3, wherein: The NMOS group includes a plurality of NMOS columns, and each of the NMOS columns includes a plurality of selection tubes; The gates of the selection transistors in the same NMOS column are connected together.
5. The memory according to claim 4, wherein: In the NMOS group, the selection tubes located in each NMOS column are arranged into multiple rows, and the selection tubes in the same row are aligned.
6. The memory according to claim 4, wherein: The PMOS group includes a plurality of storage tubes, and the storage tubes are arranged in multiple rows and columns.
7. The memory according to claim 6, wherein: The area of the selection tube is smaller than that of the storage tube, and the area of the NMOS group is smaller than that of the PMOS group.
8. The memory according to claim 6, wherein: Each of the OTP units is formed by connecting the selection tube in the NMOS group and the corresponding storage tube in the PMOS group; In the memory array, the gates of the selection transistors of the OTP units in the same column are connected to the word lines in the same column; The source of each selection transistor of the OTP unit in the same row is connected to the bit line of the same row; The source of the storage transistor of each of the OTP units is connected to a source line.
9. The memory according to claim 8, wherein: During programming, the selected OTP unit is the programming unit, and the voltage applied to the programming unit includes: The voltage of the word line is the power supply voltage; The voltage of the bit line is a first voltage, which is a positive voltage and is less than the power supply voltage; The voltage of the source line is the programming voltage, and the voltage of the N-well electrode is the programming voltage.
10. The memory according to claim 9, wherein: During programming, the voltage of the word line of each non-selected OTP cell in a different column from the programming cell is 0V.
11. The memory according to claim 8, wherein: During reading, the voltage applied to the selected OTP unit includes: The voltage of the word line is the power supply voltage; The voltage of the bit line is the power supply voltage minus a first bias voltage, the first bias voltage is the gate-source voltage of the selection tube, and the first bias voltage is greater than or equal to the threshold voltage of the selection tube to ensure that the selection tube is turned on; The voltage of the source line is the power supply voltage, and the voltage of the N-well electrode is the power supply voltage.
12. The memory according to claim 7, wherein: The gate of the selection tube is made of polysilicon, and a first gate dielectric layer is formed at the bottom of the gate of the selection tube.
13. The memory according to claim 12, wherein: The gate of the storage tube is made of polysilicon, and a second gate dielectric layer is formed at the bottom of the gate of the storage tube.
14. The memory according to claim 13, wherein: The material of the first gate dielectric layer includes an oxide layer; The material of the second gate dielectric layer includes an oxide layer.
15. The memory according to claim 10, wherein: During programming, each non-selected OPT cell in a different column and the same row as the programming cell is a program disturb cell; The voltage of the substrate electrode is lower than the first voltage.
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