Preparation method of addressable silicon-based integrated nano laser and laser

Abstract

The invention relates to the technical field of lasers, in particular to a preparation method of an addressable silicon-based integrated nano laser and the laser, and the method comprises the steps: sequentially growing a transition layer and an epitaxial layer on a silicon wafer substrate; a plurality of grooves are obtained on the P-surface contact layer through photoetching and developing, metal layers grow in the grooves, and P-surface electrodes are obtained; a gap is reserved between the P-surface electrodes, the epitaxial layer is etched downwards along the gap and over-etched to the N-surface contact layer, and an N-surface electrode through hole is formed; tiN is firstly deposited in the N-surface electrode through hole, then metal tungsten is deposited, and the N-surface electrode through hole is filled with the metal tungsten. A brand new silicon-based nano laser process route is provided by growing a laser epitaxial structure on a silicon substrate and combining a process technical route of 65nm nodes of a silicon-based integrated circuit, and the process compatibility of the laser and the front and rear ends of a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) is shown.

Description

Technical Field

[0001] The present application relates to the technical field of lasers, and in particular to a method for preparing an addressable silicon-based integrated nano-laser and a laser. Background Art

[0002] As electronic chip manufacturing approaches physical limits, bandwidth and energy consumption challenges for electrical interconnects become increasingly prominent. Optical interconnects offer a theoretical bandwidth density 1,000 times greater than copper interconnects, while consuming only one-tenth the power. Traditional discrete III-V lasers struggle to meet these density and cost requirements. Silicon-based integrated solutions can reduce optical engine size to the millimeter level.

[0003] Lasers will become a core component of the next-generation information infrastructure. Many companies are already deploying monolithic integrated laser CPUs in consumer electronics and photonic human-machine interfaces, opening up new application scenarios. This technology is not just an engineering challenge; it represents a deep integration of basic science and industrial needs.

[0004] The traditional process is to bond III-V wafers to a silicon substrate through plasma activation or low-temperature bonding technology, and then form a laser structure through photolithography and etching. However, the disadvantage is that the thermal stress and defects at the bonding interface are difficult to control, resulting in unstable laser quality. Summary of the Invention

[0005] In order to solve the above problems, the present application provides a method for preparing an addressable silicon-based integrated nanolaser and a laser.

[0006] One of the objectives of this application is to provide a method for preparing an addressable silicon-based integrated nanolaser using the following technical solution: A method for preparing an addressable silicon-based integrated nanolaser comprises the following steps: S1. Growing a transition layer and an epitaxial layer in sequence on a silicon wafer substrate; the epitaxial layer includes an N-side contact layer at the bottom and a P-side contact layer at the top, as well as several functional layers located between the N-side contact layer and the P-side contact layer; S2. A plurality of grooves are obtained on the P-side contact layer by photolithography and development, and a metal layer is grown in the grooves to obtain a P-side electrode; S3, leaving a gap between the P-side electrodes and the P-side electrodes, etching the epitaxial layer downward along the gap, over-etching to the N-side contact layer, and forming an N-side electrode through hole; S4, first depositing TiN in the N-side electrode through-hole, then depositing metal tungsten, and filling the N-side electrode through-hole, thereby realizing the N-side electrode extraction; S5. Deposit a SiO2 mask layer on the entire surface of the epitaxial layer, transfer the pattern to the mask layer, and etch away the epitaxial structure, epitaxial transition layer, and part of the silicon through the mask layer, thereby isolating different laser units; S6. Depositing a SiCOH dielectric layer on the mask layer, and further depositing a SiN layer on the dielectric layer, performing photolithography and etching to form connecting through holes facing the P-side electrode and the N-side electrode, exposing the P-side electrode and the N-side electrode; S7. Electroplating is performed in the connection through-hole with Cu to fill the connection through-hole.

[0007] By adopting the above technical solution, this application fabricates lasers directly on silicon substrates without bonding heterogeneous materials. By directly epitaxially growing III-V materials on silicon substrates and growing laser epitaxial structures on silicon, combined with the process technology route of the 65nm node of silicon-based integrated circuits, a new silicon-based nanolaser process route is proposed. This demonstrates the compatibility of lasers with CMOS front-end and back-end processes and improves the stability of laser quality. Nanolasers can be designed according to actual requirements, enabling addressable operation of multiple laser tubes.

[0008] Preferably, in S3, after the P-side electrode is formed, S31, depositing and growing a SiN layer, a SiO2 layer, and an APF layer on the epitaxial layer in sequence from bottom to top, transferring the pattern to the APF layer by photolithography to form APF strips, with gaps left between the APF strips; S32, growing SiN outside the APF strip to form a spacer layer, the APF strip is wrapped by SiN to form SiN strips, and gaps are left between the SiN strips; S33, etching away the SiN on the top of the SiN strip, and etching away the APF strip inside the SiN strip together; S34, etching downwards the gaps between the SiN strips to remove the SiO2 layer below the gaps; S35, SiN strips and SiO2 as sacrificial layers are all etched away, and the pattern is transferred to the SiN layer to form a number of wrapping strips wrapped around the P-side electrode; S36, etching the gaps between the wrapping bars, over-etching to the N-side contact layer, and the formed through holes are the N-side electrode through holes.

[0009] Preferably, in S33 , the distance between the SiN strips is 150 nm, and the spacing is controlled by the thickness of the SiN strips.

[0010] By adopting the above technical solution, using SiO2 and APF as intermediate transition sacrificial layers, the specifications of the SiN strips are controlled to ensure the distance accuracy between the SiN strips, thereby ensuring the etching accuracy of the electrode through-holes.

[0011] Preferably, in S4, after the N-side electrode through hole is formed, S41, depositing a layer of SiN on the inner wall of the N-side electrode through-hole to form a space layer; S42, etching and removing the SiN at the bottom of the N-side electrode through-hole to expose the N-side contact layer; S43, and then deposit TiN and metal tungsten.

[0012] By adopting the above technical solution, the SiN layer isolates and protects the sidewalls of the electrode through-hole, so that the deposited TiN and tungsten only contact the bottom N-side contact layer.

[0013] Preferably, in S43, TiN and tungsten are overfilled in the N-side electrode through-hole to ensure that it is full; S44, removing excess tungsten and TiN through CMP chemical mechanical planarization, with SiN as the CMP stop layer, and controlling the amount of tungsten loss not to be lower than the upper surface of the P-side contact layer; S45. Remove the SiN on and around the P-side electrode by wet etching the wrapping strip to expose the P-side electrode.

[0014] By adopting the above technical solution, the upper surface of tungsten is leveled by CMP to ensure the flatness of the surface.

[0015] As a preference, it also includes, S8, planarizing by CMP, stopping on SiN, and depositing an Al layer on the SiN; S9. Etch the Al layer to form a plurality of Al sheets directly in contact with Cu.

[0016] By adopting the above technical solution, the Al sheet is subsequently used as an external metal layer for wire bonding, which facilitates external wiring.

[0017] Preferably, in S1, the growth process of the transition layer is: First, 1 μm thick GaAs is grown on silicon to reduce the lattice mismatch between silicon and the subsequent laser epitaxial structure; then 10 cycles of 9.3 nm In are grown. 0.15 The GaAs / 12nm GaAs strained superlattice layer prevents dislocations below from propagating to the epitaxial structure above; a 0.35um GaAs layer is then grown to filter dislocations.

[0018] Another object of the present application is to provide an addressable silicon-based integrated nanolaser, which adopts the following technical solution: An addressable silicon-based integrated nano-laser is prepared by the above-mentioned method for preparing an addressable silicon-based integrated nano-laser.

[0019] In summary, this application includes at least one of the following beneficial technical effects: This application uses a transition layer to alleviate lattice mismatch, thereby directly epitaxially growing III-V materials on a silicon substrate; at the same time, a monolithic silicon-based integrated laser and a preparation route compatible with the laser and CMOS front-end and back-end processes are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic diagram of the chip structure in step S2 in Example 1; FIG2( a ) is a schematic diagram of the chip structure in step S31 in the embodiment; FIG2( b ) is a schematic diagram of the chip structure in step S32 in the embodiment; FIG2( c ) is a schematic diagram of the chip structure in step S33 of the embodiment; FIG2( d ) is a schematic diagram of the chip structure in step S36 in the embodiment; FIG3( a ) is a schematic diagram of the chip structure in step S41 in the embodiment; FIG3( b ) is a schematic diagram of the chip structure in step S43 in the embodiment; FIG3( c ) is a schematic diagram of the chip structure in step S44 in the embodiment; FIG3( d ) is a schematic diagram of the chip structure in step S45 in the embodiment; FIG4( a ) is a schematic diagram of the chip structure in step S61 in the embodiment; FIG4( b ) is a schematic diagram of the chip structure in step S62 in the embodiment; FIG4( c ) is a schematic diagram of the chip structure in step S9 in the embodiment.

[0021] Description of reference numerals: 1. Substrate; 2. Transition layer; 3. Epitaxial layer; 4. N-side contact layer; 5. P-side contact layer; 6. Functional layer; 7. Trench; 8. P-side electrode; 9. N-side electrode through hole; 10. Mask layer; 11. Dielectric layer; 12. Connecting through hole; 13. APF strip; 14. SiN strip; 15. Wrapping strip; 16. Space layer; 17. Lead-out dielectric; 18. Al sheet. DETAILED DESCRIPTION

[0022] The present application is further described in detail below in conjunction with all the accompanying drawings.

[0023] Example 1:

[0024] The present invention discloses a method for preparing an addressable silicon-based integrated nano-laser, comprising the following steps: S1. Reference Figure 1, a transition layer 2 and an epitaxial layer 3 are sequentially grown on a silicon wafer substrate 1; the epitaxial layer 3 includes an N-side contact layer 4 at the bottom and a P-side contact layer 5 at the top, as well as several functional layers 6 located between the N-side contact layer 4 and the P-side contact layer 5. The growth process of the transition layer 2 is as follows: First, 1 μm thick GaAs is grown on silicon to reduce the lattice mismatch between silicon and the subsequent laser epitaxial structure; then 10 cycles of 9.3 nm In are grown. 0.15 A GaAs / 12nm GaAs strained superlattice layer prevents dislocations from propagating to the epitaxial structure above; a 0.35µm GaAs layer is then grown to filter dislocations. Finally, the epitaxial layers 3 are sequentially grown on top.

[0025] S2, reference Figure 1 A plurality of grooves 7 with a width of 100 nm and a length of 1 μm are obtained on the P-side contact layer 5 by photolithography and development. Ti / Pt / Au / TiN is grown in the grooves 7 by magnetron sputtering, and the unnecessary parts are stripped off by the lift-off process to obtain the P-side electrodes 8. In this embodiment, three P-side electrodes 8 are used as an example for explanation.

[0026] S31. Referring to FIG. 2(a), a SiN layer, a SiO2 layer and an APF layer are sequentially deposited and grown on the entire surface of the epitaxial layer 3 from bottom to top, and the pattern is transferred to the APF layer by photolithography to form APF strips 13. There are gaps between the APF strips 13 and the APF strips 13. There are three APF strips 13 in total, and the three APF strips 13 are directly opposite to the three P-surface electrodes 8.

[0027] S32. Referring to FIG. 2( b ), SiN is grown as a whole outside the APF strip 13 to form a spacer layer. The APF strip 13 is wrapped by SiN to form a SiN strip 14. A gap is left between the SiN strips 14. The distance between the SiN strips 14 is 150 nm, and the gap is controlled by the thickness of the SiN strip 14.

[0028] S33, referring to FIG. 2(c), the SiN on the top of the APF strip 13 and the bottom of the adjacent APF strip 13 is dry-etched by a one-step self-aligned etching process, and etching is continued after the APF strip 13 is exposed.

[0029] S34. Referring to FIG. 2( d ), the gaps between the SiN strips 14 are etched downward to remove the SiO 2 layer below the gaps. The SiO 2 layer serves as a transition sacrificial layer.

[0030] S35, referring to FIG. 2( d ), the SiN strips 14 and SiO 2 as the sacrificial layer are all etched away, and the pattern is transferred to the SiN layer to form a plurality of wrapping strips 15 wrapped around the P-side electrode 8; S36 , referring to FIG. 2 ( d ), etching the gaps between the wrapping bars 15 and over-etching to the N-side contact layer 4 , and the formed through holes are the N-side electrode through holes 9 .

[0031] S41 , referring to FIG. 3( a ), a layer of SiN is deposited on the inner wall of the N-side electrode through-hole 9 to form a space layer 16 .

[0032] S42 , referring to FIG. 3( b ), the SiN at the bottom of the N-side electrode through-hole 9 is removed by etching to expose the N-side contact layer 4 .

[0033] S43, referring to FIG. 3(b), TiN and metal tungsten are sequentially deposited as the lead-out medium 17, and the lead-out medium 17 overfills the N-side electrode through-hole 9 to ensure that it is full.

[0034] S44, referring to FIG. 3(c), excess lead-out dielectric 17 is removed by CMP chemical mechanical planarization. The CMP stop layer is SiN, and the amount of tungsten loss is controlled not to be lower than the upper surface of the P-side contact layer 5.

[0035] S45 , referring to FIG. 3 ( d ), the SiN on and around the P-surface electrode 8 is removed by wet etching the wrapping strip 15 , exposing the P-surface electrode 8 .

[0036] S5. Referring to FIG. 4(a), a SiO2 mask layer 10 is deposited on the entire surface of the epitaxial layer 3, the pattern is transferred to the mask layer 10, and the epitaxial structure, the epitaxial transition layer 2 and part of the silicon are etched away through the mask layer 10, thereby isolating different laser units.

[0037] S61 , referring to FIG. 4 ( a ), a SiCOH dielectric layer 11 is deposited on the mask layer 10 , and a SiN layer is further deposited on the dielectric layer 11 .

[0038] S62. Referring to FIG. 4( b ), the SiN layer is photolithographically and etched to form connecting through-holes 12 facing the P-side electrode 8 and the N-side electrode, exposing the P-side electrode 8 and the N-side electrode. The chemical vapor deposition interlayer dielectric SiCOH is primarily used to isolate the different laser units and provide electrical insulation to prevent current interference between adjacent lasers during operation.

[0039] S7 . Referring to FIG. 4( c ), Cu is electroplated in the connection through-hole 12 to fill the connection through-hole 12 .

[0040] S8, referring to FIG4(c), planarizing is performed using CMP, stopping on SiN, and depositing an Al layer on the SiN; S9. Referring to FIG. 4( c ), the Al layer is etched to form a plurality of Al sheets 18 that are in direct contact with the Cu.

[0041] Example 2:

[0042] The embodiment of the present application discloses an addressable silicon-based integrated nano-laser manufactured by a method for preparing an addressable silicon-based integrated nano-laser in the above embodiment.

[0043] The above are all preferred embodiments of the present application, and are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A method for preparing an addressable silicon-based integrated nanolaser, characterized in that: The following steps are involved: S1. A transition layer (2) and an epitaxial layer (3) are sequentially grown on a silicon wafer substrate (1); the epitaxial layer (3) includes an N-face contact layer (4) at the bottom and a P-face contact layer (5) at the top, as well as a plurality of functional layers (6) located between the N-face contact layer (4) and the P-face contact layer (5); S2, obtaining a plurality of grooves (7) on the P-side contact layer (5) by photolithography and development, growing a metal layer in the grooves (7), and obtaining a P-side electrode (8); S3, leaving a gap between the P-side electrode (8) and the P-side electrode (8), etching the epitaxial layer (3) downward along the gap, over-etching to the N-side contact layer (4), and forming an N-side electrode through hole (9); S4, first depositing TiN in the N-side electrode through-hole (9), then depositing metal tungsten, and filling the N-side electrode through-hole (9), thereby achieving N-side electrode extraction; S5, depositing a SiO2 mask layer (10) on the entire surface of the epitaxial layer (3), transferring the pattern to the mask layer (10), and etching away the epitaxial structure and the epitaxial transition layer (2) and part of the silicon through the mask layer (10), thereby isolating different laser units; S6. Depositing a SiCOH dielectric layer (11) on the mask layer (10), and further depositing a SiN layer on the dielectric layer (11), performing photolithography and etching to form a connecting through hole (12) facing the P-side electrode (8) and the N-side electrode, exposing the P-side electrode (8) and the N-side electrode; S7. Electroplating the connection through hole (12) with Cu to fill the connection through hole (12).

2. The method for preparing an addressable silicon-based integrated nanolaser according to claim 1, wherein: In S3, after the P-side electrode (8) is formed, S31, depositing and growing a SiN layer, a SiO2 layer, and an APF layer on the epitaxial layer (3) from bottom to top in sequence, transferring the pattern to the APF layer by photolithography to form APF strips (13), with gaps between the APF strips (13); S32, growing SiN outside the APF strip (13) as a whole to form a spacer layer, the APF strip (13) is wrapped by SiN to form a SiN strip (14), and gaps are left between the SiN strips (14); S33, etching away the SiN on the top of the SiN strip (14), and etching away the APF strip (13) inside the SiN strip together; S34, etching downwards the gaps between the SiN strips (14) to remove the SiO2 layer below the gaps; S35, SiN strips (14) and SiO2 as a sacrificial layer are all etched away, and the pattern is transferred to the SiN layer to form a number of wrapping strips (15) wrapped around the P-side electrode (8); S36, etching the gaps between the wrapping bars (15) and the wrapping bars (15), over-etching to the N-side contact layer (4), and the formed through-holes are the N-side electrode through-holes (9).

3. The method for preparing an addressable silicon-based integrated nanolaser according to claim 2, wherein: In S33, the distance between the SiN strips (14) is 150 nm, and the spacing is controlled by the thickness of the SiN strips (14).

4. The method for preparing an addressable silicon-based integrated nanolaser according to claim 2, wherein: In S4, after the N-side electrode through hole (9) is formed, S41, depositing a layer of SiN on the inner wall of the N-side electrode through-hole (9) to form a space layer (16); S42, etching and removing the SiN at the bottom of the N-side electrode through-hole (9) to expose the N-side contact layer (4); S43, and then deposit TiN and metal tungsten.

5. The method for preparing an addressable silicon-based integrated nanolaser according to claim 4, wherein: In S43, TiN and tungsten are overfilled into the N-side electrode through hole (9) to ensure that it is full; S44, removing excess tungsten and TiN through CMP chemical mechanical planarization, with the CMP stop layer being SiN, and controlling the amount of tungsten loss to not be lower than the upper surface of the P-side contact layer (5); S45. Remove the SiN on and around the P-surface electrode (8) by wet etching the wrapping strip (15), exposing the P-surface electrode (8).

6. The method for preparing an addressable silicon-based integrated nanolaser according to claim 1, wherein: Also includes, S8, planarizing by CMP, stopping on SiN, and depositing an Al layer on the SiN; S9. Etching the Al layer to form a plurality of Al sheets (18) directly in contact with Cu.

7. The method for preparing an addressable silicon-based integrated nanolaser according to claim 1, wherein: In S1, the growth process of the transition layer (2) is: First, 1 μm thick GaAs is grown on silicon to reduce the lattice mismatch between silicon and the subsequent laser epitaxial structure; then 10 cycles of 9.3 nm In are grown. 0.15 The GaAs / 12nm GaAs strained superlattice layer prevents dislocations below from propagating to the epitaxial structure above; a 0.35um GaAs layer is then grown to filter dislocations.

8. An addressable silicon-based integrated nanolaser, characterized by: The invention is prepared by the preparation method of an addressable silicon-based integrated nano-laser according to any one of claims 1 to 7.

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