Method for improving stability of electrical thickness of ONO lamination in memory device
By calculating the equivalent oxide thickness of the silicon nitride layer and adjusting the thickness of the second oxide layer in stages, the problem of unstable electrical thickness of the ONO stack was solved, achieving more precise electrical thickness control and performance improvement.
Patent Information
- Application Number
- CN202510709439.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-29
- Publication Date
- 2025-09-05
AI Technical Summary
When controlling the electrical thickness stability of the ONO stack in memory devices, the existing technology ignores the difference in dielectric constants between silicon nitride and oxide materials, resulting in unstable electrical thickness, affecting device performance and production yield.
By obtaining the measured values of the thickness of each layer, calculating the equivalent oxide thickness of the silicon nitride layer, and adjusting the thickness of the second oxide layer based on the difference, a stepped APC wet immersion treatment is used to precisely control the electrical thickness of the ONO stack.
It achieves more precise electrical thickness control, effectively compensates for silicon nitride layer thickness fluctuations, improves device performance and production yield, and provides more effective process monitoring methods.
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Figure CN120603249A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for improving the electrical thickness stability of an ONO stack in a memory device. Background Art
[0002] In memory devices such as flash memory, the ONO stack structure is typically composed of a first oxide layer (Oxide 1), a silicon nitride layer (SiN), and a second oxide layer (Oxide 2), which serves as the intergate dielectric layer between the floating gate (FG) and the control gate (CG). The total electrical thickness (EOT) and stability of the three-layer ONO stack, as well as the coupling ratio between the floating gate and the control gate, have a crucial impact on the overall performance of the memory device, such as read / write speed, data retention, and reliability.
[0003] In the prior art, to control and maintain a stable electrical thickness of the ONO stack, a wet immersion (Dip) process using Advanced Process Control (APC) is typically used to monitor and adjust the total physical thickness (THKSUM) of the ONO stack. Specifically, after the deposition of the second oxide layer (Oxide2), the thickness of the second oxide layer is corrected based on the difference between the measured total physical thickness of the ONO and the target physical thickness, in order to achieve the target total physical thickness of the ONO stack.
[0004] However, because silicon nitride (SiN) materials and oxide (usually silicon dioxide) materials have different dielectric constants (the dielectric constant of SiN is generally about 7.5, while the dielectric constant of SiO2 is generally about 3.9). Therefore, even if the total physical thickness of the ONO stack is precisely controlled to the target value through the APC Dip process, if the thickness ratio of the silicon nitride layer and the oxide layer fluctuates (for example, the thickness of the silicon nitride layer fluctuates in the previous process), the actual electrical thickness of the ONO stack will still deviate and become unstable. This instability in electrical thickness will directly affect the capacitive coupling characteristics of the device, thereby adversely affecting the final performance and production yield of the device.
[0005] Therefore, how to more accurately control the electrical thickness of the ONO stack, especially when there may be process fluctuations in the physical thickness of each layer, is a technical problem that needs to be solved urgently in the current semiconductor manufacturing field. Summary of the Invention
[0006] The present invention aims to solve the problems existing in the prior art and at least provide a useful alternative. Specifically, the main technical problem to be solved by the present invention is that the prior art generally adopts a method of adjusting the thickness of the second oxide layer (Oxide2) by performing an APC (Advanced Process Control) wet immersion (Dip) based on measuring the total physical thickness (THKSUM) of the ONO stack when controlling the electrical thickness stability of the ONO stack in a memory device. However, due to the different dielectric constants of silicon nitride (SiN) and oxide (Oxide) materials, even if the total physical thickness is controlled, if the thickness ratio of the silicon nitride layer and the oxide layer constituting the ONO stack changes due to process fluctuations (especially fluctuations in the thickness of the silicon nitride layer), the actual electrical thickness (EOT) of the ONO stack will still be unstable, thereby affecting the performance and reliability of the memory device.
[0007] To achieve the above and other related objectives, the present invention provides a method for improving the electrical thickness stability of an ONO stack in a memory device, wherein the ONO stack comprises a first oxide layer, a silicon nitride layer, and a second oxide layer stacked in sequence, and at least comprises:
[0008] Step 1, obtaining a measured value of the thickness of the first oxide layer (t_Ox1_measured), a measured value of the thickness of the silicon nitride layer (t_SiN_measured), and a measured value of the thickness of the second oxide layer after deposition of the second oxide layer and before wet immersion treatment (t_Ox2_after-deposition-measured);
[0009] Step 2: multiplying the measured thickness value of the silicon nitride layer (t_SiN_measured) by a preset conversion coefficient (K_coefficient) to obtain the equivalent oxide thickness of the silicon nitride layer (t_SiN_equivalent);
[0010] Step 3: Calculate the target thickness of the second oxide layer (t_Ox2_target) based on the preset target electrical thickness of the ONO stack (EOT_ONO_target), the measured thickness of the first oxide layer (t_Ox1_measured), and the equivalent oxide thickness of the silicon nitride layer (t_SiN_equivalent);
[0011] Step 4: Calculate the difference (Δ_Ox2) between the measured thickness of the second oxide layer after deposition (t_Ox2_measured after deposition) and the target thickness of the second oxide layer (t_Ox2_target);
[0012] Step 5: Performing an advanced process control wet soak treatment on the second oxide layer based on the difference (Δ_Ox2) to adjust the thickness of the second oxide layer so that the actual electrical thickness of the ONO stack after the wet soak treatment is close to the target electrical thickness.
[0013] Preferably, in step 2, the conversion coefficient (K_coefficient) is 0.47.
[0014] Preferably, in step three, the target thickness of the second oxide layer (t_Ox2_target) is calculated by the following formula: t_Ox2_target=EOT_ONO_target-t_Ox1_measured-t_SiN_equivalent.
[0015] Preferably, in step five, performing APC wet immersion treatment on the second oxide layer based on the difference (Δ_Ox2) includes: selecting a corresponding wet immersion gear for wet immersion according to the size of the difference (Δ_Ox2).
[0016] Preferably, in step 5, selecting a corresponding wet soaking gear for wet soaking includes:
[0017] If the difference (Δ_Ox2) is greater than -10 angstroms and less than or equal to 0 angstroms, no wet soaking treatment is performed;
[0018] If the difference (Δ_Ox2) is greater than 0 angstroms and less than or equal to 2 angstroms, selecting a first wet soaking gear to perform a wet soaking treatment to remove the second oxide layer of a preset first thickness;
[0019] If the difference (Δ_Ox2) is greater than 2 angstroms and less than or equal to 4 angstroms, selecting a second wet soaking gear to perform wet soaking treatment to remove the second oxide layer of a preset second thickness;
[0020] If the difference (Δ_Ox2) is greater than 4 angstroms and less than or equal to 10 angstroms, a third wet immersion level is selected to perform wet immersion treatment to remove the second oxide layer having a preset third thickness.
[0021] Preferably, the first wet immersion gear removes the second oxide layer with a thickness of 1 angstrom, the second wet immersion gear removes the second oxide layer with a thickness of 3 angstroms, and the third wet immersion gear removes the second oxide layer with a thickness of 5 angstroms.
[0022] Preferably, the preset target electrical thickness of the ONO stack (EOT_ONO_target) is 141 angstroms.
[0023] Preferably, the first oxide layer and the second oxide layer are both silicon dioxide layers.
[0024] Preferably, the storage device is a flash memory device.
[0025] Preferably, the conversion coefficient (K_coefficient) is the ratio of the dielectric constant of the silicon dioxide material to the dielectric constant of the silicon nitride material.
[0026] As described above, the method of improving the electrical thickness stability of the ONO stack in a memory device according to the present invention has the following beneficial effects:
[0027] 1. More precise control of electrical thickness: Instead of relying solely on the total physical thickness of the ONO stack, this invention incorporates the concept of equivalent oxide thickness of the silicon nitride layer to account for differences in dielectric constants among the various layers when calculating the target thickness of the second oxide layer. APC Dip adjustments are made based on the difference between this more accurate target thickness and the actual deposited thickness, enabling more direct and precise control of the final electrical thickness of the ONO stack, stabilizing it near the target value.
[0028] 2. Effectively Compensate for Silicon Nitride Layer Thickness Fluctuations: The method of this invention effectively addresses silicon nitride layer thickness fluctuations that may occur during the previous process. Even if the silicon nitride layer thickness varies, this method effectively compensates for variations by calculating its equivalent oxide thickness and adjusting the target thickness of the second oxide layer accordingly. This reduces the impact of silicon nitride layer fluctuations on the final ONO electrical thickness and significantly improves electrical thickness stability.
[0029] 3. Improve device performance and yield: By achieving more stable ONO electrical thickness control, the present invention helps ensure the consistency and reliability of key electrical parameters of memory devices (such as flash memory) (such as the coupling ratio between the floating gate and the control gate, threshold voltage stability, read and write performance, etc.), thereby improving the overall performance of the device and the yield in the production process.
[0030] 4. Provide more effective process monitoring means: The method based on equivalent thickness calculation introduced in the present invention can establish an online monitoring indicator that can more directly reflect the electrical thickness status, providing more effective feedback and control basis for the production process. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 Schematic diagram showing a method for improving the electrical thickness stability of an ONO stack in a memory device according to the present invention;
[0032] Figure 2 Shown is a schematic diagram of the structure of the flash memory portion of the present invention;
[0033] Figure 3 Shown is a schematic diagram comparing the electrical thickness scatter plots of ONO of the present invention and the prior art;
[0034] Figure 4 It shows a schematic diagram comparing the overall fluctuation of the electrical thickness of ONO according to the present invention and the prior art. DETAILED DESCRIPTION
[0035] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.
[0036] The present invention provides an improved ONO stack (eg, a first oxide layer 102, a silicon nitride layer 103, and a second oxide layer 104) in a memory device. Figure 2 A method for improving electrical thickness stability of an ONO stack in a flash memory, comprising the following steps:
[0037] Step 1: Obtain the measured thickness values of the first oxide layer 102 (t_Ox1_measured), the measured thickness value of the silicon nitride layer 103 (t_SiN_measured), and the measured thickness value of the second oxide layer 104 after deposition and before wet soaking (t_Ox2_afterdeposition_measured). This step is the basis for subsequent precise calculation and compensation. By accurately measuring the thickness of each initial layer, precise input parameters are provided for subsequent electrical thickness control.
[0038] Step 2: Multiply the measured thickness of the silicon nitride layer 103 (t_SiN_measured) by a preset conversion coefficient (K_coefficient) to obtain the equivalent oxide thickness of the silicon nitride layer 103 (t_SiN_equivalent). The core of this key step is to recognize the difference in the contribution of the different dielectric constants of silicon nitride and oxide materials to the electrical thickness. By introducing the conversion coefficient, the physical thickness of the silicon nitride layer 103 is "equivalent" to the oxide thickness with the same capacitance effect. This allows the electrical thickness of the entire ONO stack to be evaluated and calculated based on a unified oxide thickness, greatly improving the accuracy of subsequent adjustments and, in particular, effectively addressing the impact of thickness fluctuations of the silicon nitride layer 103 itself.
[0039] In some embodiments, in step 2, the conversion coefficient (K_ coefficient) is approximately 0.47. This specific value is based on the ratio of the typical relative dielectric constants of silicon oxide (such as SiO2, with a relative dielectric constant of approximately 3.9) and silicon nitride (such as Si3N4, with a relative dielectric constant of approximately 7.5) (for example, 3.9 / 7.5≈0.52, and in actual production, an empirical optimization value such as 0.47 may be obtained according to the specific material and process calibration). It can more accurately reflect how thick the silicon nitride layer 103 is electrically equivalent to the oxide layer. Using this coefficient for conversion can better fit the actual physical effect and improve the accuracy of ONO electrical thickness prediction and control.
[0040] Furthermore, in some embodiments, the conversion coefficient (K_coefficient) is the ratio of the dielectric constant of the silicon dioxide material to the dielectric constant of the silicon nitride material. This provides a physical basis for determining the conversion coefficient, making the calculation of the equivalent thickness not merely empirical but based on the intrinsic electrical properties of the materials, thereby making the present method more widely applicable and more theoretically accurate.
[0041] Step 3: Calculate the target thickness (t_Ox2_target) of the second oxide layer 104 based on the preset target electrical thickness of the ONO stack (EOT_ONO_target), the measured thickness of the first oxide layer 102 (t_Ox1_measured), and the equivalent oxide thickness (t_SiN_equivalent) of the silicon nitride layer 103. This step establishes the ideal thickness of the second oxide layer 104, given the known contributions of other layers (including equivalent contributions) and the final electrical thickness target. This serves as the core basis for subsequent APCDip adjustments.
[0042] In some embodiments, in step 3, the target thickness (t_Ox2_target) of the second oxide layer 104 is calculated using the following formula:
[0043] t_Ox2_target=EOT_ONO_target-t_Ox1_measured-t_SiN_equivalent.
[0044] This formula directly reflects the principle of electrical thickness superposition (after equivalent conversion), making the calculation of the target thickness of the second oxide layer 104 simple and clear. The target thickness calculated in this way is intended to ensure that after subsequent processing, the electrical thickness of the entire ONO stack can accurately reach the preset target value, thereby ensuring device performance.
[0045] Step 4: Calculate the difference (Δ_Ox2) between the measured thickness of the second oxide layer 104 after deposition (t_Ox2_measured after deposition) and the target thickness of the second oxide layer 104 (t_Ox2_target). This difference directly reflects the deviation between the current deposition state of the second oxide layer 104 and the ideal target state and is key to determining the subsequent APC Dip treatment method and throughput.
[0046] Step 5: Based on the difference (Δ_Ox2), the second oxide layer 104 is subjected to an advanced process control (APC) wet soak (Dip) process to adjust the thickness of the second oxide layer 104, so that the actual electrical thickness of the ONO stack after the wet soak process is close to the target electrical thickness. This step is the execution link for achieving precise control of the electrical thickness. Through APC Dip, the second oxide layer 104 is selectively and quantitatively removed according to the deviation obtained by the above calculation, so that the electrical thickness of the entire ONO stack is finally stabilized near the target value. Compared with the traditional APC Dip based only on the physical total thickness, the present invention directly calibrates the "electrical thickness", taking into account the differences in the dielectric constants of each layer, so the control effect is better, and the fluctuation range of the ONO electrical thickness can be effectively reduced, making it closer to the target value, thereby significantly improving the performance stability and production yield of the memory device, especially when the thickness of the silicon nitride layer 103 fluctuates greatly, the improvement effect is more obvious.
[0047] In some embodiments, in step five, performing an APC Dip treatment on the second oxide layer 104 based on the difference (Δ_Ox2) includes: selecting a corresponding Dip level for wet immersion according to the size of the difference (Δ_Ox2). This step-by-step treatment method achieves refined and differentiated control of the thickness adjustment of the second oxide layer 104. Different etching intensities can be adopted according to the actual deviation, avoiding the problem of over-etching or under-etching caused by a "one-size-fits-all" approach, and improving the flexibility and accuracy of the adjustment.
[0048] Furthermore, in some embodiments, in step 5, selecting the corresponding Dip gear for wet soaking includes:
[0049] If the difference (Δ_Ox2) is greater than -10 angstroms and less than or equal to 0 angstroms, no Dip process is performed; if the difference (Δ_Ox2) is greater than 0 angstroms and less than or equal to 2 angstroms, a first Dip level is selected to perform Dip process to remove the second oxide layer 104 of a predetermined first thickness;
[0050] If the difference (Δ_Ox2) is greater than 2 angstroms and less than or equal to 4 angstroms, the second Dip level is selected to perform Dip processing to remove the second oxide layer 104 having a preset second thickness;
[0051] If the difference (Δ_Ox2) is greater than 4 angstroms and less than or equal to 10 angstroms, the third Dip level is selected to perform Dip processing to remove the second oxide layer 104 with a predetermined third thickness.
[0052] This specific gear setting provides a clear operating guide for APC Dip. For example, when the difference is in the (-10,0] angstrom range, it means that the thickness of the second oxide layer 104 after deposition is very close to or even slightly thinner than the target physical thickness required for the target electrical thickness (considering that it itself is an oxide layer and no conversion is required). At this time, no Dip treatment can avoid unnecessary process steps and potential damage. For different degrees of positive deviation, Dip gears with different etching amounts are used for precise removal. These specific difference ranges and corresponding processing methods are based on a large amount of process experimental data and device performance requirements optimization, which can ensure effective and economical adjustments to various deviation situations.
[0053] In some embodiments, the first Dip level removes about 1 angstrom of the second oxide layer 104, the second Dip level removes about 3 angstroms of the second oxide layer 104, and the third Dip level removes about 5 angstroms of the second oxide layer 104. By clarifying the specific removal amount corresponding to each Dip level, the thickness adjustment process becomes more quantitative and predictable. For example, removing incremental thicknesses of 1 angstrom, 3 angstroms, and 5 angstroms can cover deviation correction requirements from small to large, further ensuring the accuracy of the adjustment and the stability of the final electrical thickness, thereby helping to improve the batch-to-batch and intra-chip uniformity of the device.
[0054] To further illustrate the present invention, in some embodiments, the target electrical thickness of the ONO stack (EOT_ONO_target) can be 141 angstroms. Setting a clear target electrical thickness value (e.g., 141 angstroms) provides a clear benchmark for overall process control. This target value is carefully selected based on device design (e.g., the required coupling ratio between the floating gate 101 and the control gate 105, operating voltage, etc.). Through the method of the present invention, even in the face of fluctuations in upstream processes (e.g., deposition of the silicon nitride layer 103), the final ONO electrical thickness can be stably controlled at approximately 141 angstroms, which is crucial for ensuring consistency in key electrical parameters such as the device's threshold voltage, program / erase speed, and data retention characteristics.
[0055] In some embodiments, both the first oxide layer 102 and the second oxide layer 104 are silicon dioxide layers. Using silicon dioxide as the oxide layer in an ONO structure is a mature and widely used technology in semiconductor memory device manufacturing, and it exhibits excellent insulation and interface properties. In the present invention, specifying that the oxide layer is silicon dioxide facilitates more precise application of the conversion coefficient based on the difference in dielectric constant between silicon dioxide and silicon nitride.
[0056] In some embodiments, the memory device is a flash memory device. The method of the present invention is particularly suitable for flash memory devices that require extremely stable electrical thickness of the ONO layer. In flash memory devices, the ONO layer serves as a critical dielectric layer between the floating gate 101 and the control gate 105. Precise control of its electrical thickness directly affects the device's erase window, durability, data retention, and reliability. The method of the present invention can significantly reduce fluctuations in ONO electrical thickness, thereby improving the overall performance, production yield, and market competitiveness of flash memory devices.
[0057] Example:
[0058] The process of the present invention is further described below by using a specific example, but the present invention is not limited to this example.
[0059] Assuming the ONO electrical thickness target (EOT_ONO_target) is known to be 141 angstroms and the conversion factor K_factor is 0.47, during a production run, the thickness of the first oxide layer 102 (Oxide1) was measured to be 52.7 angstroms, the thickness of the silicon nitride layer 103 (SiN) was measured to be 65.6 angstroms, and the thickness of the second oxide layer 104 (Oxide2) after deposition and before the Dip process was measured to be 58.5 angstroms.
[0060] According to step 1, the measured values of the thickness of each layer are obtained.
[0061] According to step 2, the equivalent oxide thickness of the silicon nitride layer 103 is calculated: t_SiN_equivalent=t_SiN_measured*K_factor=65.6 Å*0.47≈30.832 Å.
[0062] According to step 3, the target thickness of the second oxide layer 104 is calculated: t_Ox2_target=EOT_ONO_target−t_Ox1_measured−t_SiN_equivalent=141 Å−52.7 Å−30.832 Å=57.468 Å.
[0063] According to step 4, the difference between the measured value and the target value after the deposition of the second oxide layer 104 is calculated: Δ_Ox2=t_Ox2_measured value after deposition-t_Ox2_target=58.5 Å-57.468 Å≈1.032 Å.
[0064] According to step 5, since the difference Δ_Ox2≈1.032 angstroms, the value is within the range of (0, 2] angstroms. Therefore, the first Dip level (eg, Dip 1A, designed to remove about 1 angstrom) is selected for APC Dip treatment.
[0065] After the treatment, the thickness of the second oxide layer 104 (Oxide 2) is theoretically about 58.5 Å - 1 Å = 57.5 Å.
[0066] At this time, the electrical thickness of the ONO stack after treatment is verified: EOT_ONO_actual=t_Ox1_measured+t_Ox2_after treatment+t_SiN_equivalent=52.7 Å+57.5 Å+30.832 Å≈141.032 Å.
[0067] It can be seen that the actual electrical thickness after treatment, 141.032 angstroms, is very close to the target electrical thickness of 141 angstroms. This proves that the method of the present invention can effectively calculate the equivalent thickness and the difference based on the actual measurement value and the target electrical thickness, and select the appropriate Dip gear for compensation, thereby accurately controlling the electrical thickness of the ONO stack, stabilizing it near the target value, and significantly improving the stability of the electrical thickness. In contrast, if only the total physical thickness is controlled, when the SiN layer thickness fluctuates, the electrical thickness may deviate significantly even if the total physical thickness meets the standard.
[0068] As attached Figure 3 and attached Figure 4 The simulation verification results shown show that the new control method proposed by the present invention (NEW, i.e., APC Dip is performed based on the Oxide2 target value calculated according to the electrical thickness), compared to the benchmark control method (BSL, i.e., APC Dip is performed based on the total physical thickness THKSUM of ONO), the overall fluctuation (standard deviation STD) of the ONO electrical thickness (characterized by ONO_Tinv_40_100) is significantly reduced (e.g., reduced from 0.85 to 0.54), and the average value (Mean) is closer to the target value (e.g., from 142.05 closer to the target of 141 to 140.52). This intuitively proves the significant advantages of the present invention in improving the stability of the ONO electrical thickness. The fundamental reason is that the present invention directly incorporates the key factors affecting electrical thickness - the dielectric constant difference and thickness fluctuation of the silicon nitride layer 103 - into the core calculation of the APC control loop by means of equivalent oxide thickness, thereby achieving a more direct and accurate regulation of the ONO electrical thickness. This method can more effectively compensate for disturbances from the preceding process (such as the deposition of the silicon nitride layer 103 ), thereby ensuring the consistency and reliability of the performance of the memory device.
[0069] In summary, the present invention improves the original method of performing APC Dip to correct the Oxide2 thickness based on the total physical thickness of the ONO to performing APC Dip based on the difference between the Oxide2 target value calculated based on the target electrical thickness of the ONO and taking into account the equivalent oxide thickness of the silicon nitride layer 103 and the actual measured value after Oxide2 deposition, thereby achieving more precise control and higher stability of the ONO electrical thickness. This not only solves the problem of inaccurate electrical thickness control caused by focusing only on physical thickness and ignoring differences in material dielectric constants in the prior art, but also provides an effective way to maintain the stability of the ONO electrical thickness in the face of fluctuations in the thickness of the silicon nitride layer 103, which has important practical application value for improving the performance, yield, and reliability of memory devices.
[0070] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.
[0071] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A method for improving the electrical thickness stability of an ONO stack in a memory device, wherein the ONO stack comprises a first oxide layer, a silicon nitride layer, and a second oxide layer stacked in sequence, characterized in that: At least: Step 1, obtaining a measured value of the thickness of the first oxide layer (t_Ox1_measured), a measured value of the thickness of the silicon nitride layer (t_SiN_measured), and a measured value of the thickness of the second oxide layer after deposition of the second oxide layer and before wet immersion treatment (t_Ox2_after-deposition-measured); Step 2: multiplying the measured thickness value of the silicon nitride layer (t_SiN_measured) by a preset conversion coefficient (K_coefficient) to obtain the equivalent oxide thickness of the silicon nitride layer (t_SiN_equivalent); Step 3: Calculate the target thickness of the second oxide layer (t_Ox2_target) based on the preset target electrical thickness of the ONO stack (EOT_ONO_target), the measured thickness of the first oxide layer (t_Ox1_measured), and the equivalent oxide thickness of the silicon nitride layer (t_SiN_equivalent); Step 4: Calculate the difference (Δ_Ox2) between the measured thickness of the second oxide layer after deposition (t_Ox2_measured after deposition) and the target thickness of the second oxide layer (t_Ox2_target); Step 5: Performing an advanced process control wet soak treatment on the second oxide layer based on the difference (Δ_Ox2) to adjust the thickness of the second oxide layer so that the actual electrical thickness of the ONO stack after the wet soak treatment is close to the target electrical thickness.
2. The method for improving the electrical thickness stability of an ONO stack in a memory device according to claim 1, wherein: In step 2, the conversion coefficient (K_coefficient) is 0.
47.
3. The method for improving the electrical thickness stability of an ONO stack in a memory device according to claim 1, wherein: In step three, the target thickness of the second oxide layer (t_Ox2_target) is calculated by the following formula: t_Ox2_target=EOT_ONO_target-t_Ox1_measured-t_SiN_equivalent.
4. The method for improving the electrical thickness stability of an ONO stack in a memory device according to claim 1, wherein: In step five, performing the APC wet immersion treatment on the second oxide layer based on the difference (Δ_Ox2) includes: selecting a corresponding wet immersion gear to perform the wet immersion according to the size of the difference (Δ_Ox2).
5. The method for improving the electrical thickness stability of an ONO stack in a memory device according to claim 4, wherein: In step 5, selecting the corresponding wet soaking gear for wet soaking includes: If the difference (Δ_Ox2) is greater than -10 angstroms and less than or equal to 0 angstroms, no wet soaking treatment is performed; If the difference (Δ_Ox2) is greater than 0 angstroms and less than or equal to 2 angstroms, selecting a first wet soaking gear to perform a wet soaking treatment to remove the second oxide layer of a preset first thickness; If the difference (Δ_Ox2) is greater than 2 angstroms and less than or equal to 4 angstroms, selecting a second wet soaking gear to perform wet soaking treatment to remove the second oxide layer of a preset second thickness; If the difference (Δ_Ox2) is greater than 4 angstroms and less than or equal to 10 angstroms, a third wet immersion level is selected to perform wet immersion treatment to remove the second oxide layer having a preset third thickness.
6. The method for improving the electrical thickness stability of an ONO stack in a memory device according to claim 5, wherein: The first wet immersion gear removes the second oxide layer with a thickness of 1 angstrom, the second wet immersion gear removes the second oxide layer with a thickness of 3 angstroms, and the third wet immersion gear removes the second oxide layer with a thickness of 5 angstroms.
7. The method for improving the electrical thickness stability of an ONO stack in a memory device according to claim 1, wherein: The preset target electrical thickness of the ONO stack (EOT_ONO_target) is 141 angstroms.
8. The method for improving the electrical thickness stability of an ONO stack in a memory device according to claim 1, wherein: The first oxide layer and the second oxide layer are both silicon dioxide layers.
9. The method for improving the electrical thickness stability of an ONO stack in a memory device according to claim 1, wherein: The storage device is a flash memory device.
10. The method for improving the electrical thickness stability of an ONO stack in a memory device according to claim 1, wherein: The conversion coefficient (K_coefficient) is the ratio of the dielectric constant of the silicon dioxide material to the dielectric constant of the silicon nitride material.