Semiconductor packages with spherical bond interconnect structures

Abstract

A semiconductor package includes: a substrate; a plurality of leads; a semiconductor die attached to the substrate at a first side of the semiconductor die, the semiconductor die having a bond pad at a second side of the semiconductor die opposite the first side; and a spherical bond interconnect structure connecting the bond pad to a first lead of the plurality of leads. The present invention relates to a spherical bond interconnect structure comprising at least two levels of spherical bond wire loops stacked on each other and attached to each other at opposite ends of the stacked spherical bond wire loops such that the at least two levels of stacked spherical bond wire loops are electrically connected in parallel. Methods of manufacturing the semiconductor package are also described.

Description

Background Art

[0001] Advances in SiC (silicon carbide) and GaN (gallium nitride) technologies have resulted in smaller bond pad sizes, up to 30% smaller for higher current densities, compared to Si (silicon) technology. Such small bond pads require high power density interconnects within a small pad / lead area.

[0002] Therefore, there is a need for an improved interconnect structure for a semiconductor package having a small bond pad size. Summary of the Invention

[0003] According to an embodiment of a semiconductor package, the semiconductor package includes: a substrate; a plurality of leads; a semiconductor die attached to the substrate at a first side of the semiconductor die, the semiconductor die having a bonding pad at a second side of the semiconductor die opposite to the first side; and a ball bond interconnect structure connecting the bonding pad to a first lead of the plurality of leads, wherein the ball bond interconnect structure includes at least two levels of ball bond wire loops, the at least two levels of ball bond wire loops being stacked on each other and attached to each other at opposite ends of the stacked ball bond wire loops such that the at least two levels of stacked ball bond wire loops are electrically connected in parallel, wherein the at least two levels of stacked ball bond wire loops include a first ball bond wire loop connected between the bond pad and the first lead, the first ball bond wire loop including a ball end attached to one of the bond pad or the first lead, a tail end attached to the other of the bond pad or the first lead, and a wire portion compressed into the ball end of the first ball bond wire loop and flattened; and a second ball bond wire loop stacked on the first ball bond wire loop, the second ball bond wire loop including a ball end attached to the tail end of the first ball bond wire loop, a tail end attached to the ball end of the first ball bond wire loop, and a wire portion compressed into the ball end of the second ball bond wire loop and flattened.

[0004] According to an embodiment of a method of manufacturing a semiconductor package, the method includes: attaching a first side of a semiconductor die to a substrate, the semiconductor die having a bonding pad at a second side of the semiconductor die opposite to the first side; and forming a ball bond interconnect structure connecting the bonding pad to a first lead, the ball bond interconnect structure including at least two levels of ball bond wire loops, the at least two levels of ball bond wire loops being stacked on each other and attached to each other at opposite ends of the stacked ball bond wire loops such that the at least two levels of stacked ball bond wire loops are electrically connected in parallel, wherein forming the ball bond interconnect structure includes: connecting a first ball bond wire loop to the first lead; wherein the first ball bond wire loop includes a ball end attached to one of the bond pad and the first lead, a tail end attached to the other of the bond pad and the first lead, and a wire portion compressed into the ball end of the first ball bond wire loop and flattened; and a second ball bond wire loop is vertically stacked on the first ball bond wire loop, the second ball bond wire loop includes a ball end attached to the tail end of the first ball bond wire loop, a tail end attached to the ball end of the first ball bond wire loop, and a wire portion compressed into the ball end of the second ball bond wire loop and flattened.

[0005] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The elements of the drawings are not necessarily to scale with respect to each other. The same reference numerals denote corresponding similar components. The features of the various illustrated embodiments may be combined unless they exclude each other. The embodiments are illustrated in the drawings and described in detail in the following description.

[0007] Figure 1 A top plan view of a semiconductor package is shown that includes a multi-level ball bond interconnect structure for connecting bond pads of a die to leads of a package that includes the die.

[0008] Figure 2A and Figure 2B Respective side perspective views of a multi-level ball bond interconnect structure during different stages of fabrication are shown.

[0009] Figure 3 An embodiment of forming a ball bond wire loop included in a ball bond wire loop at a bottommost level of a multi-level ball bond interconnect structure is shown.

[0010] Figure 4An embodiment is shown in which the ball end of an upper ball bond wire loop is attached to the tail end of a lower ball bond wire loop of a multi-level ball bond interconnect structure.

[0011] Figure 5 An embodiment is shown in which bond wires extending from the stitches of an upper ball bond wire loop are attached to the ball ends of a lower ball bond wire loop. DETAILED DESCRIPTION

[0012] Embodiments described herein provide a multi-level ball bond interconnect structure for connecting the bonding pads of a semiconductor die (chip) to the leads of a package that includes the semiconductor die. The multi-level ball bond interconnect structure has at least two levels of ball bond wire loops stacked on each other in a direction perpendicular to the die bonding pads. The at least two levels of ball bond wire loops are attached to each other at opposite ends of the stacked ball bond wire loops so that the at least two levels of stacked ball bond wire loops are electrically connected in parallel. The multi-level ball bond interconnect structure supports higher current density for smaller bonding pad footprints and accommodates a wide range of wire size diameters (e.g., 25 to 75 μm or larger) and materials (e.g., Cu, Au, etc.). Multi-level ball bond interconnect structures have several advantages over stacked wedge bonding, including higher throughput (e.g., 2-3 times faster units per hour), no need for thicker bond pads, lower cost (e.g., 3 times more cost-effective), and wider applicability as ball bond technology is used in over 90% of semiconductor packages compared to wedge bond technology.

[0013] Exemplary embodiments of a multi-level ball bond interconnect structure and related manufacturing methods are described below with reference to the accompanying drawings.

[0014] Figure 1 A top view of semiconductor package 100 prior to molding is shown. Semiconductor package 100 includes substrate 102, leads 104, and semiconductor die 106 attached to substrate 102 at a backside of semiconductor die 106. Semiconductor die 106 has first bond pads 108 at a front side of semiconductor die 106 opposite the backside.

[0015] Semiconductor die 106 can be a logic die (such as a processor die, a memory die, etc.), a power semiconductor die (such as a power transistor die, a power diode die, a half-bridge die, etc.), or a die that combines logic devices and power devices on the same semiconductor substrate. In one embodiment, semiconductor die 106 is a vertical semiconductor die having a main current path between bonding pads 108 at the front side of the die and bonding pads at the back side of the die (not shown). Examples of vertical power semiconductor dies include, but are not limited to, power Si MOSFETs (metal oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), SiC MOSFETs, GaN HEMTs (high electron mobility transistors), etc.

[0016] More than one semiconductor die 106 can be attached to the same or different substrates 102, so that the semiconductor package 100 can include one or more semiconductor dies 106. For example, the semiconductor package 100 can be discrete in that the package 100 includes a single semiconductor die 106, such as a low-side or high-side power transistor die. In another example, the semiconductor package 100 can include one or more low-side power transistor dies connected in parallel and one or more high-side power transistor dies connected in parallel to form a half-bridge. A gate driver (not shown) for each semiconductor die 106 can also be included in the semiconductor package 100.

[0017] The substrate 102 to which the at least one semiconductor die 106 is attached may be a lead frame. For example, the semiconductor die 106 may be attached to a paddle 110 of the lead frame, and the package leads 104 may be part of the lead frame. The lead frame features (e.g., the leads 104, the paddle 110, etc.) may be defined by etching, stamping, etc., of a metal sheet such as a Cu (copper) sheet.

[0018] Semiconductor package 100 also includes a multi-level ball bond interconnect structure 112 that connects a first bond pad 108 of semiconductor die 106 to a first lead 104_1 of package leads 104. For example, in the case of a vertical power transistor die, first bond pad 108 can be a source pad, and multi-level ball bond interconnect structure 112 can connect source pad 108 to source lead 104_1 of the package. Furthermore, in the case of a vertical power transistor die, gate pad 114 can be disposed on the same side of semiconductor die 106 as source pad 108 and can be electrically connected to another lead 104_2, for example, via at least a bond wire 116. In the case of a leadframe as substrate 102, die paddle 110 can form one of package leads 104_3.

[0019] The ball bond interconnect structure 112 is multi-level because the ball bond interconnect structure 112 includes a plurality of balls in a direction perpendicular to the front surface of the semiconductor die 106 ( Figure 1 At least two levels of ball bond wire loops 118 are stacked on top of each other in the z-direction (in the z-direction). The at least two levels of ball bond wire loops 118 are attached to each other at opposite ends 120, 122 of the stacked ball bond wire loops 118 so that the at least two levels of stacked ball bond wire loops 118 are electrically connected in parallel to support higher current density. The multi-level ball bond interconnect structure 112 can be particularly advantageous for smaller bond pad footprints with relatively high current density (e.g., where the semiconductor die 106 is a SiC or GaN die). In the case of SiC or GaN, the semiconductor die 106 can have a footprint of less than 2 mm 2 area and / or greater than 4.5A / mm 2 The multi-level ball bond interconnect structure 112 may also be used with larger bond pad footprints, for example, where the semiconductor die 106 is made of Si.

[0020] Figure 2A and Figure 2B Respective side perspective views of the multi-level ball bond interconnect structure 112 during different stages of fabrication are shown.

[0021] Figure 2A The multi-level ball bond interconnect structure 112 is shown after forming the first (lowest) level 200 of the ball bond wire loop 118, and Figure 2B The ball bond interconnect structure 112 is shown after a second level 202 of ball bond wire loops 118 is vertically stacked on the bottom-most level 200 of ball bond wire loops 118 .

[0022] The bottommost level 200 of the ball bond wire loops 118 includes a plurality of first ball bond wire loops 118_1 connected in parallel between the die bond pads 108 and the corresponding package leads 104_1. The three (3) first ball bond wire loops 118_1 are connected in parallel between the die bond pads 108 and the corresponding package leads 104_1. Figure 2A and Figure 2B1. However, the lowest level 200 of ball bond wire loops 118 may include two (2), three (3), or more first ball bond wire loops 118_1 connected in parallel between the die bond pads 108 and corresponding package leads 104_1. Each first ball bond wire loop 118_1 has a ball end 202 attached to one of the die bond pads 108 or the package leads 104_1, a tail (stitch) end 204 attached to the other of the die bond pads 108 or the package leads 104_1, and a wire portion 216 compressed into the ball end 202 and flattened.

[0023] The second level 202 of ball bond wire loops 118 includes a plurality of second ball bond wire loops 118_2 stacked on the plurality of first ball bond wire loops 118_1. The three (3) second ball bond wire loops 118_2 are stacked on top of each other. Figure 2B 1. However, the second level 202 of ball bond wire loops 118 may include two (2), three (3), or more second ball bond wire loops 118_2 stacked on the plurality of first ball bond wire loops 118_1. In one embodiment, the second level 202 of ball bond wire loops 118 includes the same number of ball bond wire loops 118 as the first level 200 of ball bond wire loops 118. However, the second level 202 of ball bond wire loops 118 may include fewer ball bond wire loops 118 than the first level 200 of ball bond wire loops 118, such as one-half, one-third, etc.

[0024] Each second ball bond wire loop 118_2 has a ball end 208 attached to the tail end 204 of a corresponding one of the first ball bond wire loops 118_1 and a tail end 210 attached to the ball end 202 of the corresponding first ball bond wire loop 118_1. Each second ball bond wire loop 118_2 also has a wire portion 212 that is folded in the lateral (e.g., x) direction and extends between the ball end 208 and the tail end 210 of the second ball bond wire loop 118_2.

[0025] like Figure 2A As shown, the ball end 202 of each first ball bond wire loop 118_1 has a ball bump 214 attached to one of the die bond pad 108 or the package lead 104_1 and a wire portion 216 that is compressed into the ball bump 214 and flattened as part of the wire folding process. Figure 2BAs shown, the ball end 208 of each second ball bond wire loop 118_2 has a ball bump 218 attached to the tail end 204 of the corresponding first ball bond wire loop 118_1 and a stitch 220 on the ball bump 218 of the second ball bond wire loop 118_2. The ball bump 218 of each second ball bond wire loop 118_2 is first bonded to the tail end 204 of the corresponding first ball bond wire loop 118_1, and then the stitch 220 is formed on top of the ball bump 218 as part of the wire folding process. The tail end 210 of each second ball bond wire loop 118_2 is attached to the stitch 216 and ball bump 214 of the corresponding first ball bond wire loop 118_1.

[0026] In one embodiment, the outermost layer 124 of the die bond pad 108 to which the multi-level ball bond interconnect structure 112 is attached comprises copper, and the plurality of first ball bond wire loops 118_1 and the plurality of second ball bond wire loops 118_2 each comprise copper. In another embodiment, the outermost layer 124 of the die bond pad 108 to which the multi-level ball bond interconnect structure 112 is attached comprises gold, and the plurality of first ball bond wire loops 118_1 and the plurality of second ball bond wire loops 118_2 each comprise gold. Other single metal systems or dual metal systems may be used.

[0027] The plurality of first ball bond wire loops 118_1 and the plurality of second ball bond wire loops 118_2, either individually or in combination, each have a diameter in the range of 25 μm to 75 μm. Alternatively or in combination, the plurality of first ball bond wire loops 118_1 have a first diameter, and the plurality of second ball bond wire loops 118_2 have a second diameter different from the first diameter, such that the plurality of first ball bond wire loops 118_1 can be thinner or thicker than the plurality of second ball bond wire loops 118_2.

[0028] Figure 2B 1. Two (2) levels 200, 202 of stacked ball bond wire loops 118 are shown in FIG. However, this is merely an example. The multi-level ball bond interconnect structure 112 may have more than two (2) levels of ball bond wire loops 118 stacked vertically on top of each other, wherein the ball bond wire loops 118 of each overlying level extend in an opposite direction to the ball bond wire loops 118 of the underlying level, such that a staggered stack of ball end bonds and tail end bonds is formed at both ends of the multi-level ball bond interconnect structure 112. For example, a plurality of third ball bond wire loops ( Figure 2A and Figure 2B18_2) can be stacked on a plurality of second ball bond wire loops 118_2, wherein each third ball bond wire loop has a ball end attached to the tail end 210 of a corresponding one of the second ball bond wire loops 118_2, a tail end attached to the ball end 208 of the corresponding second ball bond wire loop 118_2, and a wire portion compressed into the ball end of the wire loop and flattened.

[0029] Figure 3 An embodiment of forming one of the first ball bond wire loops 118_1 included in the bottom-most level 200 of the ball bond wire loops 118 is shown. Figure 3 The process shown in can be repeated one or more times to form two (2) or more first ball bond wire loops 118_1 connected in parallel between two (2) bonding sites.

[0030] exist Figure 3 In step (a), an electrical flame off (EFO) process is performed using a capillary 300 through which a bonding wire 302 is passed, so as to form a free air ball 304 at an end of the bonding wire 302 .

[0031] exist Figure 3 In step (b), the capillary 300 captures the free air ball 304 with the capillary holder 306 released and moves in the z-direction to a first bonding site, which may be the die bond pad 108 or the corresponding package lead 104_1.

[0032] exist Figure 3 In step (c), force and / or ultrasonic energy is applied to form a ball bump 214 of the first ball bond wire loop 118_1 at a first bonding site, such that the ball bump 214 is attached to one of the die bond pad 108 or the corresponding package lead 104_1. The second bonding site is the other of the die bond pad 108 or the package lead 104_1, and the ball bump 214 is not attached to the other.

[0033] Figure 3 Steps (d) and (e) involve a wire folding process during which the capillary 300 moves in the z direction away from the first bond site and changes lateral (eg, x or y) direction, as indicated by the angled arrows, to fold the bond wire 302.

[0034] exist Figure 3In step (f), the clamp 306 is closed and the capillary 300 is moved downward in the z-direction toward the first bonding site, compressing the folded portion (e.g., z- or s-shaped fold) in the bond wire 302 onto the previously formed ball bump 214. This folding and compression creates a flattened area that allows for the stacking of multiple wire loops while mitigating bonding-related issues. For example, if the capillary were pressed directly onto the round ball bump without using the folding and compression steps to create a flattened bonding area on the ball bump 304, the pins of a second ball bond wire loop stacked on the first ball bond wire loop could be misshapen.

[0035] exist Figure 3 In step (g), as part of the wire looping process, the capillary 300 is moved in the z-direction away from the first bond site with the clamp 306 released. The flattening of the wire loop also enables a lower loop angle and, therefore, enables stacking of multiple wire loop layers. The wire looping process also involves moving the capillary 300 in the lateral (e.g., x-) direction to the second bond site with the clamp 306 released, folding the bond wire 302 in the lateral direction and defining the length of the folded wire portion 206 extending between the ball end 202 and the tail end 204 of the first ball bond wire loop 118_1.

[0036] exist Figure 3 In step (h), the clamp 306 is engaged and the capillary 300 is moved in the z-direction to the second engagement site.

[0037] exist Figure 3 In step (i), the clamp 306 is released, and force and / or ultrasonic energy is applied to attach the bond wire 302 extending from the stitch 216 to the second bond site.

[0038] exist Figure 3 In step (j), the capillary 300 is moved away from the second engagement site in the z direction with the clamp 306 released.

[0039] exist Figure 3 In step (k), the clamp 306 is engaged and the capillary 300 continues to move in the z-direction away from the second bonding site, thereby severing the bond wire 302 to form the tail (stitch) end 204 of the first ball bond wire loop 118_1 and completing the first ball bond wire loop 118_1.

[0040] Figure 4 An embodiment is shown in which the ball end 208 of the second ball bond wire loop 118_2 is attached to the tail end 204 of one of the first ball bond wire loops 118_1 . Figure 4The process shown in can be repeated for each first ball bond wire loop 118_1 in the bottommost level 200 of ball bond wire loops 118 . Figure 4 The process shown in can be repeated for each additional level of stacked ball bond wire loops 118, but with the direction changed for each additional level so that the ball end of each new ball bond wire loop 118 being formed is bonded to the tail end of the previously formed ball bond wire loop 118.

[0041] exist Figure 4 In step (a), the free air ball 400 has been formed at the end of the bonding wire 402 passing through the capillary 300, and the capillary 300 moves in the z direction toward the tail end 204 of the corresponding first ball bond wire loop 118_1 when the clamp 306 is released. Figure 3 The method is formed as explained in step (a).

[0042] exist Figure 4 In step (b), force and / or ultrasonic energy is applied to form the ball bumps 218 of the second ball bond wire loop 118_2. The ball bumps 218 of the second ball bond wire loop 118_2 are attached to the tail ends 204 of the corresponding first ball bond wire loop 118_1.

[0043] exist Figure 4 In step (c), the bonding wire 402 is folded in the lateral (eg, x) direction, and force and / or ultrasonic energy is applied to form stitches 220 on the ball bumps 218 of the second ball bond wire loop 118_2, for example, as described above in conjunction with Figure 3 The capillary 300 is then moved as part of the wire looping process, which involves vertical and lateral movement to bend or loop the bonding wire 402 to the second bonding site, for example, as described above in conjunction with Figure 3 as explained in steps (g) and (h).

[0044] Figure 5 An embodiment is shown in which a bond wire 402 extending from a stitch 220 of a second ball bond wire loop 118_2 is attached to a corresponding ball end 202 of a first ball bond wire loop 118_1 . Figure 5 The process shown in can be repeated for each first ball bond wire loop 118_1 in the bottommost level 200 of ball bond wire loops 118 . Figure 5 The process shown in can be repeated for each additional level of stacked ball bond wire loops 118, but with the direction changed for each additional level so that the tail end of each ball bond wire loop 118 being formed is bonded to the ball end of the underlying ball bond wire loop 118.

[0045] exist Figure 5 In step (a), the capillary 300 is moved so that the capillary 300 is moved in the longitudinal direction (longitudinal direction) of the ball bond interconnect structure 112. Figure 5 In the x-direction (in the x-direction), the center point 500 of the tail end 210 of the second ball bond wire loop 118_2 is longitudinally offset from the center point 504 of the corresponding ball bump 214 of the first ball bond wire loop 118_1. This longitudinal offset allows for a flatter stack at the ends 202, 210 of the stacked wire loops 118_1, 118_2. The positioning of the capillary 300 also defines the length of the folded wire portion 212 extending between the ball end 208 and the tail end 210 of the second ball bond wire loop 118_2.

[0046] exist Figure 5 In step (b), the capillary clamp 306 is released, and force and / or ultrasonic energy is applied to attach the bonding wire 402 extending from the stitch 220 of the second ball bond wire loop 118_2 to the corresponding ball end 202 of the first ball bond wire loop 118_1.

[0047] exist Figure 5 In step (c), the bonding wire 402 is cut to form the tail end 210 of the second ball bond wire loop 118_2 and complete the second ball bond wire loop 118_2. The tail end 210 of the second ball bond wire loop 118_2 is attached to the corresponding ball end 202 of the first ball bond wire loop 118_1.

[0048] Figure 4 and Figure 5 The process shown in FIG can be repeated for each additional level of ball bond wire loops 118 forming the ball bond interconnect structure 112 by stacking a desired number of ball bond wire loops 118 on the next lowest level of ball bond wire loops 118. Each ball bond wire loop 118 in the latest level has a ball end attached to a tail end of a corresponding ball bond wire loop 118 in the next lowest level of ball bond wire loops 118, a tail end attached to the ball end of the corresponding ball bond wire loop, and a wire portion that is compressed into the ball end of the new ball bond wire loop and flattened.

[0049] Although the present disclosure is not limited in this regard, the following numbered examples illustrate one or more aspects of the present disclosure.

[0050] Example 1: A semiconductor package comprising: a substrate; a plurality of leads; a semiconductor die attached to the substrate at a first side of the semiconductor die, the semiconductor die having a bonding pad at a second side of the semiconductor die opposite to the first side; and a ball bond interconnect structure connecting the bonding pad to a first lead of the plurality of leads, wherein the ball bond interconnect structure comprises at least two levels of ball bond wire loops, the at least two levels of ball bond wire loops being stacked on one another and attached to one another at opposite ends of the stacked ball bond wire loops such that the at least two levels of stacked ball bond wire loops are electrically connected in parallel, wherein the at least two levels of stacked ball bond wire loops comprise: a first ball bond wire loop; a ball bond wire loop connected between the bond pad and the first lead, the first ball bond wire loop including a ball end attached to one of the bond pad or the first lead, a tail end attached to the other of the bond pad or the first lead, and a wire portion compressed into the ball end of the first ball bond wire loop and flattened; and a second ball bond wire loop stacked on the first ball bond wire loop, the second ball bond wire loop including a ball end attached to the tail end of the first ball bond wire loop, a tail end attached to the ball end of the first ball bond wire loop, and a wire portion compressed into the ball end of the second ball bond wire loop and flattened.

[0051] Example 2: A semiconductor package according to Example 1, wherein the ball end of the first ball bond wire loop includes a ball bump attached to one of the bonding pad or the first lead and a stitch on the ball bump, wherein the ball end of the second ball bond wire loop includes a ball bump attached to the tail end of the first ball bond wire loop and a stitch on the ball bump of the second ball bond wire loop, and wherein the tail end of the second ball bond wire loop is attached to the stitch and the ball bump of the first ball bond wire loop.

[0052] Example 3: A semiconductor package according to Example 1 or 2, wherein the at least two levels of stacked ball-bonded wire loops include: a third ball-bonded wire loop stacked on the second ball-bonded wire loop, the third ball-bonded wire loop including a ball end attached to the tail end of the second ball-bonded wire loop, a tail end attached to the ball end of the second ball-bonded wire loop, and a wire portion compressed into the ball end of the third ball-bonded wire loop and flattened.

[0053] Example 4: The semiconductor package of any of Examples 1 to 3, wherein the semiconductor die is a SiC or GaN die.

[0054] Example 5: The semiconductor package of Example 4, wherein an outermost layer of the bond pad comprises copper, and wherein both the first ball bond wire loop and the second ball bond wire loop comprise copper.

[0055] Example 6: The semiconductor package of Example 5, wherein the first ball bond wire loop and the second ball bond wire loop both have a diameter in a range of 25 μm to 75 μm.

[0056] Example 7: The semiconductor package of Example 5 or 6, wherein the first ball bond wire loop has a first diameter, and wherein the second ball bond wire loop has a second diameter different from the first diameter.

[0057] Example 8: The semiconductor package of any of Examples 5 to 7, wherein the semiconductor die is attached to the substrate by lead-free solder.

[0058] Example 9: The semiconductor package of any of Examples 4 to 8, wherein the area of ​​the semiconductor die is less than 2 mm 2 .

[0059] Example 10: The semiconductor package of Example 9, wherein the semiconductor die has a thermal conductivity greater than 4.5 A / mm 2 current density.

[0060] Example 11: A method of manufacturing a semiconductor package, the method comprising: attaching a first side of a semiconductor die to a substrate, the semiconductor die having a bonding pad at a second side of the semiconductor die opposite to the first side; and forming a ball bond interconnect structure connecting the bonding pad to a first lead, the ball bond interconnect structure comprising at least two levels of ball bond wire loops, the at least two levels of ball bond wire loops being stacked on one another and attached to one another at opposite ends of the stacked ball bond wire loops such that the at least two levels of stacked ball bond wire loops are electrically connected in parallel, wherein forming the ball bond interconnect structure comprises: connecting a first ball bond wire loop to the bonding pad; a first ball bond wire loop between the bonding pad and the first lead, the first ball bond wire loop including a ball end attached to one of the bonding pad or the first lead, a tail end attached to the other of the bonding pad or the first lead, and a wire portion compressed into the ball end of the first ball bond wire loop and flattened; and a second ball bond wire loop vertically stacked on the first ball bond wire loop, the second ball bond wire loop including a ball end attached to the tail end of the first ball bond wire loop, a tail end attached to the ball end of the first ball bond wire loop, and a wire portion compressed into the ball end of the second ball bond wire loop and flattened.

[0061] Example 12: The method of Example 11, wherein connecting the first ball bond wire loop between the bonding pad and the first lead includes: attaching a first ball bump to one of the bonding pad or the first lead; forming a first stitch on the first ball bump; attaching a first wire extending from the first stitch to the other of the bonding pad or the first lead; and cutting the first wire to form the tail end of the first ball bond wire loop, wherein vertically stacking the second ball bond wire loop on the first ball bond wire loop includes: attaching a second ball bump to the tail end of the first ball bond wire loop; forming a second stitch on the second ball bump; attaching a second wire extending from the second stitch to the ball end of the first ball bond wire loop; and cutting the second wire to form the tail end of the second ball bond wire loop.

[0062] Example 13: The method of Example 12, wherein attaching the second wire extending from the second pin of the second ball-bonding wire loop to the spherical end of the first ball-bonding wire loop includes offsetting a center point of the tail end of the second ball-bonding wire loop from a center point of the first spherical bump of the first ball-bonding wire loop in a longitudinal direction of the ball-bonding interconnect structure.

[0063] Example 14: A method according to any one of Examples 11 to 13, wherein forming the ball bond interconnect structure includes: stacking a third ball bond wire loop on the second ball bond wire loop, the third ball bond wire loop including a ball end attached to the tail end of the second ball bond wire loop, a tail end attached to the ball end of the second ball bond wire loop, and a wire portion that is compressed into the ball end of the third ball bond wire loop and is flattened.

[0064] Example 15: The method of any one of Examples 11 to 14, wherein the semiconductor die is a SiC or GaN die.

[0065] Example 16: The method of Example 15, wherein an outermost layer of the bond pad comprises copper, and wherein both the first ball bond wire loop and the second ball bond wire loop comprise copper.

[0066] Example 17: The method of Example 16, wherein the first ball bond wire loop and the second ball bond wire loop both have a diameter in a range of 25 μm to 75 μm.

[0067] Example 18: The method of any of Examples 15 to 17, wherein attaching the first side of the semiconductor die to the substrate comprises soldering the first side of the semiconductor die to the substrate using lead-free solder.

[0068] Terms such as "first", "second", etc. are used to describe various elements, regions, parts, etc., and are not intended to be limiting. Throughout the description, the same terms refer to the same elements.

[0069] As used herein, the terms "having," "comprising," "including," "comprising," and the like are open-ended terms indicating the presence of stated elements or features, but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular unless the context clearly indicates otherwise.

[0070] Unless expressly stated otherwise, the expression "and / or" should be interpreted as including all possible combinations and disjunctions. For example, the expression "A and / or B" should be interpreted as meaning only A, only B, or both A and B. Unless expressly stated otherwise, the expression "at least one" should be interpreted in the same manner as "and / or." For example, the expression "at least one of A and B" should be interpreted as meaning only A, only B, or both A and B.

[0071] It will be understood that the features of the various embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0072] Although specific embodiments have been shown and described herein, it will be understood by those skilled in the art that various alternative and / or equivalent embodiments may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Accordingly, the present invention is intended to be limited only by the claims and their equivalents.

Claims

1. A semiconductor package, comprising: substrate; Multiple leads; a semiconductor die attached to the substrate at a first side of the semiconductor die, the semiconductor die having bond pads at a second side of the semiconductor die opposite the first side; as well as a ball bond interconnect structure connecting the bond pad to a first lead of the plurality of leads, wherein the ball bond interconnect structure includes at least two levels of ball bond wire loops stacked on one another and attached to one another at opposite ends of the stacked ball bond wire loops such that the at least two levels of stacked ball bond wire loops are electrically connected in parallel, The at least two levels of stacked ball bond wire loops include: a first ball bond wire loop connected between the bond pad and the first lead, the first ball bond wire loop including a ball end attached to one of the bond pad or the first lead, a tail end attached to the other of the bond pad or the first lead, and a wire portion compressed into the ball end of the first ball bond wire loop and flattened; and a second ball bond wire loop stacked on the first ball bond wire loop, the second ball bond wire loop including a ball end attached to the tail end of the first ball bond wire loop, a tail end attached to the ball end of the first ball bond wire loop, and a wire portion compressed into the ball end of the second ball bond wire loop and flattened.

2. The semiconductor package according to claim 1, in, the ball end of the first ball bond wire loop includes a ball bump attached to one of the bond pad or the first lead and a stitch on the ball bump, wherein the ball end of the second ball bond wire loop includes a ball bump attached to the tail end of the first ball bond wire loop and a stitch on the ball bump of the second ball bond wire loop, and wherein the tail end of the second ball bond wire loop is attached to the stitches and the ball bumps of the first ball bond wire loop.

3. The semiconductor package according to claim 1, wherein The at least two levels of stacked ball bond wire loops include: a third ball bond wire loop stacked on the second ball bond wire loop, the third ball bond wire loop including a ball end attached to the tail end of the second ball bond wire loop, a tail end attached to the ball end of the second ball bond wire loop, and a wire portion compressed into the ball end of the third ball bond wire loop and flattened.

4. The semiconductor package according to claim 1, wherein The semiconductor die is a SiC or GaN die.

5. The semiconductor package according to claim 4, wherein An outermost layer of the bond pad comprises copper, and wherein both the first ball bond wire loop and the second ball bond wire loop comprise copper. The semiconductor package according to claim 5 , wherein: The first ball bond wire loop and the second ball bond wire loop both have a diameter in a range of 25 μm to 75 μm.

7. The semiconductor package according to claim 5, wherein The first ball bond wire loop has a first diameter, and wherein the second ball bond wire loop has a second diameter different than the first diameter.

8. The semiconductor package according to claim 5, wherein The semiconductor die is attached to the substrate by lead-free solder.

9. The semiconductor package according to claim 4, wherein The area of ​​the semiconductor die is less than 2 mm 2 .

10. The semiconductor package according to claim 9, wherein The semiconductor die has a thermal conductivity greater than 4.5A / mm 2 current density.

11. A method for manufacturing a semiconductor package, the method comprising: attaching a first side of a semiconductor die to a substrate, the semiconductor die having bond pads at a second side of the semiconductor die opposite the first side; as well as forming a ball bond interconnect structure connecting the bond pad to the first lead, the ball bond interconnect structure comprising at least two levels of ball bond wire loops stacked on one another and attached to one another at opposite ends of the stacked ball bond wire loops such that the at least two levels of stacked ball bond wire loops are electrically connected in parallel; Wherein, forming the spherical joint interconnection structure comprises: connecting a first ball bond wire loop between the bond pad and the first lead, the first ball bond wire loop including a ball end attached to one of the bond pad or the first lead, a tail end attached to the other of the bond pad or the first lead, and a wire portion compressed into the ball end of the first ball bond wire loop and flattened; and A second ball bond wire loop is stacked vertically on the first ball bond wire loop, the second ball bond wire loop including a ball end attached to the tail end of the first ball bond wire loop, a tail end attached to the ball end of the first ball bond wire loop, and a wire portion compressed into the ball end of the second ball bond wire loop and flattened.

12. The method according to claim 11, in, Connecting the first ball bond wire loop between the bond pad and the first lead includes: attaching a first ball bump to one of the bond pad or the first lead; forming a first stitch on the first spherical bump; attaching a first wire extending from the first stitch to the other of the bond pad or the first lead; and cutting the first wire to form the tail end of the first ball bond wire loop, wherein vertically stacking the second ball bond wire loop on the first ball bond wire loop comprises: attaching a second ball bump to the tail end of the first ball bond wire loop; forming a second stitch on the second spherical bump; attaching a second wire extending from the second stitch to the ball end of the first ball bond wire loop; and The second wire is cut to form the tail end of the second ball bond wire loop.

13. The method according to claim 12, wherein: Attaching the second wire extending from the second stitch of the second ball bond wire loop to the ball end of the first ball bond wire loop includes: A center point of the tail end of the second ball bond wire loop is offset from a center point of the first ball bump of the first ball bond wire loop in a longitudinal direction of the ball bond interconnect structure.

14. The method according to claim 11, wherein Forming the ball bond interconnect structure includes: A third ball bond wire loop is stacked on the second ball bond wire loop, the third ball bond wire loop including a ball end attached to the tail end of the second ball bond wire loop, a tail end attached to the ball end of the second ball bond wire loop, and a wire portion compressed into the ball end of the third ball bond wire loop and flattened.

15. The method according to claim 11, wherein The semiconductor die is a SiC or GaN die.

16. The method according to claim 15, wherein An outermost layer of the bond pad comprises copper, and wherein both the first ball bond wire loop and the second ball bond wire loop comprise copper.

17. The method according to claim 16, wherein The first ball bond wire loop and the second ball bond wire loop both have a diameter in a range of 25 μm to 75 μm.

18. The method according to claim 15, wherein Attaching the first side of the semiconductor die to the substrate includes: The first side of the semiconductor die is soldered to the substrate using lead-free solder.

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