Data transmission method between core particles, chip, medium and program product

Abstract

The invention provides a data transmission method between core particles, which is applied to a first core particle and comprises the following steps: encrypting plaintext data to obtain ciphertext data; and sending the ciphertext data to a second core grain. The invention further provides a data transmission method applied to the second core particle, a chip, a computer readable medium and a computer program product.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular to a method for data transmission between chips, a chip, a computer-readable medium, and a computer program product. Background Art

[0002] With the downward evolution of semiconductor manufacturing processes, the characteristic size of transistors is gradually approaching the physical limit, and the development of logic chips has entered the "post-Moore era". The emergence of chiplet technology has effectively alleviated many problems such as chip yield, power consumption, and area under advanced processes.

[0003] However, the result is that the interconnection of chips results in data being transmitted between chips in plain text. Even the transmission over ultra-short distances on the order of millimeters still faces the risk of information leakage, that is, the lack of protection for data confidentiality between chips. Summary of the Invention

[0004] The present disclosure provides a data transmission method between core particles, a chip, a computer-readable medium, and a computer program product.

[0005] In a first aspect, an embodiment of the present disclosure provides a method for data transmission between chiplets, which is applied to a first chiplet and includes:

[0006] Encrypt plaintext data to obtain ciphertext data;

[0007] The encrypted data is sent to the second core particle.

[0008] In a second aspect, an embodiment of the present disclosure provides a method for data transmission between corelets, which is applied to a second corelet and includes:

[0009] Receiving the ciphertext data sent by the first chip;

[0010] Decrypt the ciphertext data to obtain plaintext data.

[0011] In a third aspect, an embodiment of the present disclosure provides a chip comprising a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, the data transmission method between core particles described in the first aspect or the second aspect is implemented.

[0012] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the method for transmitting data between core particles according to the first aspect or the second aspect is implemented.

[0013] In a fifth aspect, an embodiment of the present disclosure provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the data transmission method between core particles described in the first aspect or the second aspect.

[0014] In the embodiment of the present disclosure, the plaintext data of the first core particle is encrypted and then sent to the second core particle, and the second core particle decrypts the received ciphertext data, thereby ensuring secure transmission of data between core particles. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In the accompanying drawings of the embodiments of the present disclosure:

[0016] Figure 1 A schematic diagram of the structure of the chiplet interconnection provided in an embodiment of the present disclosure;

[0017] Figure 2 A schematic flow chart of a method for transmitting data between core particles applied to a first core particle according to an embodiment of the present disclosure;

[0018] Figure 3 A schematic diagram of an application scenario of a data transmission method between chiplets provided in an embodiment of the present disclosure;

[0019] Figure 4 A schematic diagram of an application scenario of another method for data transmission between core particles provided by an embodiment of the present disclosure;

[0020] Figure 5 A schematic diagram of an application scenario of another method for data transmission between chiplets provided in an embodiment of the present disclosure;

[0021] Figure 6 A schematic diagram of the process of encrypting plaintext data in the first working mode provided by an embodiment of the present disclosure;

[0022] Figure 7 A schematic diagram of a process for encrypting plaintext data in a first working mode provided by an embodiment of the present disclosure;

[0023] Figure 8 A schematic diagram of the structure of an exemplary first encryption algorithm provided in an embodiment of the present disclosure;

[0024] Figure 9 A schematic diagram of another process flow for encrypting plaintext data in a first working mode provided by an embodiment of the present disclosure;

[0025] Figure 10 A schematic diagram of the structure of an exemplary second encryption algorithm provided in an embodiment of the present disclosure;

[0026] Figure 11 A schematic diagram of a forward round operation in an exemplary second encryption algorithm provided in an embodiment of the present disclosure;

[0027] Figure 12 A schematic diagram of a backward round operation in an exemplary second encryption algorithm provided in an embodiment of the present disclosure;

[0028] Figure 13 A schematic diagram of the process of encrypting plaintext data in the second working mode provided by an embodiment of the present disclosure;

[0029] Figure 14 A schematic diagram of a process for encrypting plaintext data in a second working mode provided by an embodiment of the present disclosure;

[0030] Figure 15 A schematic diagram of a process for encrypting plaintext data in another second working mode provided by an embodiment of the present disclosure;

[0031] Figure 16 A schematic flow chart of a data transmission method between core particles applied to a second core particle provided by an embodiment of the present disclosure;

[0032] Figure 17 A schematic diagram of the process of decrypting ciphertext data in the first working mode provided by an embodiment of the present disclosure;

[0033] Figure 18 A schematic diagram of a process for decrypting ciphertext data in a first working mode provided by an embodiment of the present disclosure;

[0034] Figure 19 A schematic diagram of a process for decrypting ciphertext data in another first working mode provided by an embodiment of the present disclosure;

[0035] Figure 20 A schematic diagram of the process of decrypting ciphertext data in the second working mode provided by an embodiment of the present disclosure;

[0036] Figure 21 A schematic diagram of a process for decrypting ciphertext data in a second working mode provided by an embodiment of the present disclosure;

[0037] Figure 22 A schematic diagram of a process for decrypting ciphertext data in another second working mode provided by an embodiment of the present disclosure;

[0038] Figure 23 A hierarchical schematic diagram of an exemplary chip provided for an embodiment of the present disclosure;

[0039] Figure 24 A schematic diagram of the logical structure of an exemplary hardware security module provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0041] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully understand the scope of the present disclosure to those skilled in the art.

[0042] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the detailed embodiments, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed embodiments with reference to the accompanying drawings.

[0043] The present disclosure may be described with reference to plan views and / or cross-sectional views by way of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0044] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0045] The terms used in this disclosure are only used to describe specific embodiments and are not intended to limit the disclosure. As used in this disclosure, the term "and / or" includes any and all combinations of one or more related enumerated items. As used in this disclosure, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. As used in this disclosure, the terms "comprising" and "made of" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meanings as those commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined in this disclosure.

[0047] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0048] like Figure 1As shown, in some related technologies, in a standard 2D package, chiplets A, B, and C are interconnected, and data between the chiplets is transmitted in plain text, posing a security risk. An attacker could monitor the signals at the chip pins, for example, by using an analyzer to decode the monitored differential signal and restore it to a digital signal, thereby stealing the user's critical information.

[0049] In some other related technologies, data security is ensured by defining encryption and decryption modules in standard high-speed interface protocols. For example, the GCM-AES algorithm is defined as an encryption and authentication algorithm in PCIe Gen6 (Peripheral Component Interconnect Express Generation 6, the sixth generation peripheral component high-speed interconnect standard). However, due to the complex logic of AES, additional chip area, delay and power consumption overhead need to be added between chiplets for the GCM-AES algorithm, which will cause transmission delay problems in data transmission. Some chiplet application scenarios (for example, data transfer between computing chiplets and storage chiplets, interaction between computing chiplets, and cross-chiplet data or instruction transfer) are very sensitive to data transmission delays and therefore cannot meet the chiplet interconnection delay requirements. In addition, since the GCM-AES algorithm needs to instantiate multiple sets of chiplet interconnection modules when implementing encryption and authentication functions, the increase in the area of ​​a single encryption and decryption algorithm will also cause the entire chip area to increase exponentially, occupying too much chip space.

[0050] Therefore, there is an urgent need for a solution that can encrypt data between core particles and ensure low latency, low resources, and low power consumption during data transmission.

[0051] like Figure 2 As shown, in a first aspect, an embodiment of the present disclosure provides a data transmission method between chiplets, which is applied to a first chiplet and includes:

[0052] S11. Encrypt the plaintext data to obtain ciphertext data;

[0053] S12: Send the encrypted data to the second core particle.

[0054] In the embodiment of the present disclosure, the plaintext data of the first core is encrypted and then sent to the second core, and the second core decrypts the received ciphertext data, thereby ensuring secure transmission of data between cores.

[0055] The embodiment of the present disclosure does not impose any special restrictions on the types of the first core-particle and the second core-particle, which may be a computing core-particle, an interface core-particle, a storage core-particle, etc.

[0056] It is worth noting that, in some embodiments, the algorithm for encrypting plaintext data in the embodiments of the present disclosure is a symmetric encryption algorithm.

[0057] Furthermore, it should be noted that, before data is transmitted between the first and second core particles, symmetric keys, encryption and decryption parameters, and other configuration processes need to be performed. In some embodiments, this configuration can be performed using an independent hardware security module. Symmetric keys can be generated using asymmetric algorithms, such as RSA (Rivest-Shamir-Adleman), DH (Diffie-Hel lman Key Exchange), or ECDH (Elliptic Curve Diffie-Hel lman) for encrypted key transmission or exchange. Of course, other methods can also be used to configure pre-shared keys.

[0058] In order to enable those skilled in the art to more clearly understand the technical solutions provided by the embodiments of the present disclosure, the application scenarios of the technical solutions provided by the embodiments of the present disclosure are described below:

[0059] like Figure 3 As shown, the embodiments of the present disclosure can be applied to scenarios where multiple chiplets are interconnected, for example, chiplet A is interconnected with chiplet B and chiplet C, and chiplet D is interconnected with chiplet B and chiplet C; an encryption and decryption module is set between the interconnection interfaces of the two interconnected chiplets to ensure the security of data transmission.

[0060] In some embodiments, the encryption and decryption module used to implement the data transmission method between core particles in the embodiment of the present disclosure can be set in the hierarchical structure of the core particle interconnection. The hierarchical structure includes: a protocol layer, a die-to-die (core particle interconnection) adapter, and a physical layer. Among them, the protocol layer includes PCIe, CXL (Compute Express Link, computing high-speed link standard) and user-defined stream protocols; the die-to-die adapter is set between the protocol layer and the physical layer to implement multiplexing, interface conversion, cyclic redundancy check, etc.; the physical layer can be used to implement link training, data scrambling and descrambling, and high-speed SerDes (Serializer / Deserializer) and other functions.

[0061] like Figure 4 and Figure 5 As shown, the encryption and decryption module can be set at the boundary between the custom stream protocol layer and the die-to-die adapter, or it can be set inside the die-to-die adapter. The die-to-die adapter is unaware of whether the data is plaintext or ciphertext. When the encryption and decryption module is set inside the die-to-die adapter, the die-to-die adapter encrypts the data at each protocol layer.

[0062] like Figure 6 As shown, in some embodiments, step S11 includes:

[0063] S111. When the working mode of the first core is the first working mode, group the plaintext data according to a preset number to obtain the preset number of first data groups;

[0064] S112: Encrypt each of the first data groups using a first encryption algorithm and a preset first key to obtain ciphertext data.

[0065] In the embodiment of the present disclosure, the first working mode is ECB (Electronic Codebook). The plaintext data is grouped according to a preset number to obtain a preset number of first data groups, and each first data group is encrypted using a preset first key through a first encryption algorithm to obtain ciphertext data. That is, C j =PRINCE K (P j ) for j = 1...n, where K is the first key, P j is the first data group, j is the number of the first data group, PRINCE K (P j ) represents the use of the first key K to lock the first data group P j Perform encryption operation to obtain the encrypted first data group C j .

[0066] The first key is pre-negotiated between the first core that sends the ciphertext data and the second core that receives the ciphertext data. The present embodiment does not impose any specific restrictions on the configuration of the first key. If the first key is not leaked, ciphertext data can be transmitted between the first core and the second core, thereby enhancing data security. The present embodiment does not impose any specific restrictions on the number of pre-set keys, which may be determined based on actual circumstances.

[0067] The key length of the first key is 128 bits, and the group length of the first data group is 64 bits.

[0068] like Figure 7 As shown, in some embodiments, the first encryption algorithm is the PRINCE algorithm. Each first data group is input as plain text into the PRINCE algorithm and encrypted using the first key to obtain the encrypted first data group (i.e., ciphertext). The PRINCE algorithm is a symmetric encryption algorithm. The middle two rounds (i.e., S' and S -1 ) process, the first 5 rounds (i.e. R1, R2, R3, R4, R5) and the last 5 rounds (i.e. R6, R7, R8, R9, R 10) are inverse transformations except for the different round constants. The FX structure is used, with a block length of 64 bits, a key length of 128 bits, and 12 rounds of iteration. The round constant satisfies 0≤i≤11, where α is the round constant P i Related fixed constants.

[0069] like Figure 8 As shown in FIG. 1 , as one embodiment of the present disclosure, a first data group is encrypted using a first encryption algorithm according to a preset first key (k1 and k0). Where k0 is the first 64-bit subkey in the preset 128-bit first key, k1 is the last 64-bit subkey in the preset 128-bit first key, RC0 is the round constant of the first round, RC1 is the round constant of the first round, ..., RC 12 is the round constant of the 11th round, S is the S-box replacement operation, S -1 is the inverse operation of the S-box replacement operation, M' is the diffusion operation, SR is the row shift forward transformation operation, SR -1 It is the row shift inverse transform operation.

[0070] For the first data group that needs to be encrypted:

[0071] First, the first data group is XORed with k0, k1, and the round constant RC1 of the first round in sequence;

[0072] Then, the first encryption process of rounds 2 to 6 is performed in sequence. In each round of the first encryption process, an S-box replacement operation, a diffusion operation, a row shift forward transformation operation, an XOR operation with the round constant of the current round, and an XOR operation with k1 are sequentially performed.

[0073] After completing the first encryption process of the sixth round, an S-box replacement operation, a diffusion operation, and an inverse operation of the S-box replacement operation are performed in sequence.

[0074] Then, the second encryption process of rounds 7 to 11 is performed. In each round of the second encryption process, the XOR operation with k1, the XOR operation with the round constant of the current round, the reverse row shift transformation operation, the diffusion operation, and the inverse operation of the S-box replacement operation are sequentially performed.

[0075] After completing the second encryption process of the 11th round, the round constant RC 11 , k1, and k0' are XORed to obtain the encrypted first data group.

[0076] like Figure 6 As shown, in some embodiments, after step S111, the method further includes:

[0077] S113. Encrypt each of the first data groups using a second encryption algorithm according to a preset first key and a preset first adjustable value to obtain ciphertext data; the first adjustable value includes a first initialization vector and a first count;

[0078] S114: Increment the first count by one.

[0079] In the embodiment of the present disclosure, the first working mode is ECB with a first adjustable value, namely TECB (Tweakable Electronic Ciphertext Book). The plaintext data is grouped according to a preset number to obtain a preset number of first data groups. Each first data group is encrypted using a preset first key and a preset first adjustable value using a second encryption algorithm to obtain ciphertext data. j =MANTIS K ,T(P j ) for j = 1...n, where K is the first key, P j is the first data group, j is the count value (first count) of the first data group in the encryption order, T is the first adjustable value, MANTIS K ,T(P j ) represents the use of the first key K and the first adjustable value T to perform the first data set P j Perform encryption operation to obtain the encrypted first data group C j .

[0080] As a method of an embodiment of the present disclosure, since the number of first data groups is a preset number, according to the encryption order of each first data group, after the first first data group is encrypted with the first adjustable value (T=IV+1), the next first data group is encrypted with the first adjustable value (T=IV+2), and the next first data group is encrypted with the first adjustable value (T=IV+3), and so on, the difficulty of deciphering the ciphertext data can be significantly improved.

[0081] The first adjustable value T = IV + j, where IV is the first initialization vector (IV), which can be pre-set, and j is the count value of the first data group in the encryption order, i.e., the first count. The first key is pre-negotiated between the first core-particle that sends the ciphertext data and the second core-particle that receives the ciphertext data. The disclosed embodiments do not impose any specific restrictions on the configuration of the first key. If the first key and / or the first adjustable value are not leaked, ciphertext data can be transmitted between the first core-particle and the second core-particle, thereby enhancing data security.

[0082] like Figure 9As shown, in some embodiments, the second encryption algorithm is the MANTIS algorithm. Each first data group is input into the MANTIS algorithm as plain text, and is encrypted using the first key and the first adjustable value T including the first initial vector to obtain the encrypted first data group (i.e., ciphertext). The MANTIS algorithm is also a symmetric encryption algorithm with a block length of 64 bits, an adjustable value (i.e., the first adjustable value) length of 64 bits, and a key length of 128 bits. The number of iterative rounds includes 5 forward rounds and 5 backward rounds. The forward round function is The backward round function is Among them, M is a linear transformation, such as column mixing; P is a permutation operation, that is, rearranging the position of the data block, P -1 is the inverse operation of P; ATK is the XOR operation of the first adjustable value and the result of the previous operation; AC is the current round constant RC i XOR with the result of the previous operation; S is the S-box replacement operation, which divides the result of the previous operation into 16 half-bytes from high to low, and uses 16 4-bit S-boxes to replace them respectively. Symbol Indicates that the output of the previous operation is used as the input of the next operation. h is the update function of the first adjustable value, which is a shift function.

[0083] like Figure 10 As shown in FIG. 1 , as one embodiment of the present disclosure, the first data group is encrypted using the second encryption algorithm according to the preset first key (k1 and k0). Wherein, k0 is the first 64-bit subkey in the preset 128-bit first key, k1 is the last 64-bit subkey in the preset 128-bit first key, and R1, R2, ..., R5 are 5 rounds of forward round operations, respectively. These are 5 rounds of backward wheel operations respectively; T is the first adjustable value, and h is the update function (displacement function) of the first adjustable value.

[0084] like Figure 10 As shown, for the first data group that needs to be encrypted:

[0085] Performing an XOR operation on the first data group and k0 to obtain a first processing result; performing an XOR operation on the first adjustable value T and k1 to obtain a second processing result; and then performing an XOR operation on the first processing result and the second processing result to obtain a third processing result;

[0086] like Figure 11 As shown, the third processing result is sequentially subjected to 5 rounds of forward round operations, each round of forward round operations sequentially including S box replacement operation, XOR with the current round constant, and XOR with the current TK i Perform XOR, permutation and linear transformation operations; TK i It is an updated value obtained by updating the first adjustable value through the update function h of the first adjustable value.

[0087] like Figure 12 As shown, the results of the five rounds of forward round operations are sequentially subjected to S-box replacement operation, linear transformation and S-box replacement operation, and then five rounds of backward round operations are sequentially performed. Each round of backward round operation includes linear transformation, inverse operation of replacement operation, XOR with the current round constant, and XOR with the current TK i Perform XOR and S-box replacement operations.

[0088] Then the results of the 5 rounds of backward wheel operation are compared with Perform XOR processing to obtain a fourth processing result; perform XOR processing on the fourth processing result and k0' to obtain the encrypted first data group; wherein, It is the inverse of k1, and k0' is the same as k0.

[0089] like Figure 13 As shown, in some embodiments, step S11 includes:

[0090] S115. When the working mode of the first chip is the second working mode, determine a first counting vector according to a preset second initial vector;

[0091] S116. Encrypt the first count vector using a first encryption algorithm and a preset second key to obtain first intermediate ciphertext data.

[0092] S117. Determine ciphertext data according to the first intermediate ciphertext data and the plaintext data.

[0093] In the embodiment of the present disclosure, the second working mode is CTR (counter), in which the packet length of input data is 32 or 64 bits, the length of the second key is 128 bits, and the length of the first count vector is 64 bits.

[0094] The first counting vector includes a preset second initialization vector and a counter for plaintext data. The second initialization vector is preset, and the counter for plaintext data is used to increment the counter in the first counting vector corresponding to the next plaintext data to be encrypted by 1 each time the encryption of the plaintext data is completed. For example, the upper 32 bits of the 64-bit first counting vector are the second initialization vector, and the lower 32 bits are a counter starting from 1. If the plaintext data is the first encrypted data, the upper 32 bits of its first counting vector are the second initialization vector, and the lower 32 bits are a count of 1.

[0095] like Figure 14 As shown, the first counting vector is encrypted using the second key to obtain first intermediate ciphertext data, and then the ciphertext data is determined according to the first intermediate ciphertext data and the plaintext data.

[0096] In some embodiments, the first encryption algorithm may be a PRINCE algorithm.

[0097] In some embodiments, step S117 includes:

[0098] Grouping the first intermediate ciphertext data according to a specified group length to obtain first intermediate groups, and grouping the plaintext data to obtain second intermediate groups;

[0099] Ciphertext data is determined according to the first intermediate group and the second intermediate group.

[0100] The designated block length may be 32 or 64 bits, and the present disclosure is not limited thereto. The first intermediate ciphertext data and the plaintext data are grouped separately to obtain a first intermediate block and a second intermediate block, and the first intermediate block (ciphertext) is subjected to bitwise XOR with the second intermediate block (plaintext) to obtain the ciphertext data. If the block length of the first intermediate block is 64 bits, the high 32 bits thereof may be XORed with the second intermediate block, or the data of the full block length (i.e., 64 bits) may be XORed with the second intermediate block.

[0101] like Figure 13 As shown, in some embodiments, after step S115, the method further includes:

[0102] S118. Encrypt the first count vector using a second encryption algorithm, using a preset second key and a preset unique value, to obtain second intermediate ciphertext data.

[0103] S119. Obtain ciphertext data according to the second intermediate ciphertext data and the plaintext data.

[0104] In the disclosed embodiment, the second operating mode is extended CTR, or ECTR (extended counter). In the second operating mode, the input data packet length is 32 or 64 bits, the second key length is 128 bits, the first count vector length is 64 bits, and the unique value length is 64 bits.

[0105] like Figure 15 As shown, the first count vector is encrypted using the second key and the unique value to obtain second intermediate ciphertext data, and then the ciphertext data is determined based on the second intermediate ciphertext data and the plaintext data. In some embodiments, step S119 includes: grouping the second intermediate ciphertext data according to a specified group length to obtain group one, and grouping the plaintext data to obtain group two; and performing a bitwise exclusive OR operation on group one and group two to determine the ciphertext data.

[0106] In some embodiments, the second encryption algorithm is a MANTIS encryption algorithm, wherein the unique value is an adjustable value in the MANTIS algorithm.

[0107] The above-described embodiments of the present disclosure improve data transmission security by encrypting data transmitted between chiplets. The use of lightweight first and second encryption algorithms enables low-latency and low-power data transmission between chiplets. Confidentiality is enhanced by introducing adjustable and unique values ​​in the first and second encryption algorithms.

[0108] In addition, the operations used in the algorithm structures of the first encryption algorithm and the second encryption algorithm are similar or close, and modules can be reused during hardware implementation, thereby reducing the cost of chip development and implementation and improving the utilization efficiency of hardware resources.

[0109] like Figure 16 As shown, in a second aspect, an embodiment of the present disclosure provides a data transmission method between chiplets, which is applied to a second chiplet and includes:

[0110] S21, receiving the ciphertext data sent by the first chip;

[0111] S22. Decrypt the ciphertext data to obtain plaintext data.

[0112] In the embodiment of the present disclosure, the second core particle decrypts the ciphertext data sent by the first core particle, thereby obtaining the data to be transmitted by the first core particle, thereby ensuring the secure transmission of data between core particles.

[0113] The embodiment of the present disclosure does not impose any special restrictions on the types of the first core-particle and the second core-particle, which may be a computing core-particle, an interface core-particle, a storage core-particle, etc.

[0114] It is worth noting that, in some embodiments, the algorithm for encrypting plaintext data in the embodiments of the present disclosure is a symmetric encryption algorithm.

[0115] like Figure 17 As shown, in some embodiments, step S22 includes:

[0116] S221: When the working mode of the second core is the first working mode, group the ciphertext data according to a preset number to obtain the preset number of second data groups;

[0117] S222: Decrypt each of the second data groups using a first decryption algorithm according to a preset first key to obtain plaintext data.

[0118] In the embodiment of the present disclosure, the first working mode is ECB. The ciphertext data is grouped according to a preset number to obtain a preset number of second data groups, and each second data group is decrypted using a preset first key through a first decryption algorithm to obtain plaintext data. Among them, K is the first key, C j is the second data group, j is the number of the second data group, Indicates that the second data group C is encrypted with the first key K. j Perform a decryption operation to obtain the decrypted second data group P j Then the decrypted second data group P j XOR with the address to get the plaintext data.

[0119] The first key is pre-negotiated between the first core that sends the ciphertext data and the second core that receives the ciphertext data. The present embodiment does not impose any specific restrictions on the configuration of the first key. If the first key is not leaked, ciphertext data can be transmitted between the first core and the second core, thereby enhancing data security. The present embodiment does not impose any specific restrictions on the number of pre-set keys, which may be determined based on actual circumstances.

[0120] like Figure 18 As shown, in some embodiments, the first encryption algorithm is the PRINCE algorithm, and each second data group is input into the PRINCE algorithm as a ciphertext, and is decrypted using the first key to obtain a decrypted second data group (ie, plaintext).

[0121] like Figure 17 As shown, in some embodiments, after step S221, the method further includes:

[0122] S223, obtaining a preset second adjustable value; the adjustable value includes a preset third initial vector and a second count;

[0123] S224: Decrypt each of the second data groups using a second decryption algorithm according to a preset first key and the second adjustable value to obtain ciphertext data, and increase the second count in the second adjustable value by one.

[0124] In the embodiment of the present disclosure, the first working mode is ECB with a first adjustable value. The ciphertext data is grouped according to a preset number to obtain a preset number of second data groups. Each second data group is encrypted using a preset first key and a preset second adjustable value through a second decryption algorithm to obtain plaintext data. T(C j ) for j = 1...n, where K is the first key, C j is the second data group, j is the count value (second count) of the second data group in the encryption order, T is the second adjustable value, T(C j ) represents the use of the first key K and the second adjustable value T to perform the calculation on the second data group C j Perform a decryption operation to obtain the decrypted second data group P j .

[0125] like Figure 19 As shown, in some embodiments, the second decryption algorithm is the MANTIS algorithm, and each second data group is input into the MANTIS algorithm as a ciphertext, and is decrypted using the first key and the second adjustable value T including the third initial vector to obtain the decrypted second data group (i.e., plaintext).

[0126] like Figure 20 As shown, in some embodiments, step S22 includes:

[0127] S225: When the operating mode of the second chiplet is the second operating mode, determine a second counting vector according to a preset fourth initial vector;

[0128] S226. Decrypt the second count vector using the first decryption algorithm and the preset second key to obtain first intermediate plaintext data.

[0129] S227. Obtain plaintext data according to the first intermediate plaintext data and the ciphertext data.

[0130] In the disclosed embodiment, the second operating mode is CTR. In the second operating mode, the input data packet length is 32 or 64 bits, the second key length is 128 bits, and the second count vector length is 64 bits. In some embodiments, the first encryption algorithm may be the PRINCE algorithm.

[0131] The second counting vector includes a preset fourth initialization vector and a counter for the ciphertext data. The fourth initialization vector is preset, and the counter for the ciphertext data is used to increment the counter in the second counting vector corresponding to the next ciphertext data to be decrypted by 1 each time the ciphertext data is decrypted. For example, the upper 32 bits of the 64-bit second counting vector are the fourth initialization vector, and the lower 32 bits are a counter starting at 1. If the ciphertext data is the first decrypted data, the upper 32 bits of its second counting vector are the fourth initialization vector, and the lower 32 bits are a counter starting at 1.

[0132] like Figure 21 As shown, the second count vector is decrypted using the second key to obtain first intermediate plaintext data, and then the plaintext data is determined based on the first intermediate plaintext data and the ciphertext data.

[0133] In some embodiments, step S227 includes:

[0134] Grouping the first intermediate plaintext data according to a specified group length to obtain a third intermediate group, and grouping the ciphertext data to obtain a fourth intermediate group;

[0135] Plaintext data is determined based on the third intermediate group and the fourth intermediate group.

[0136] The designated block length may be 32 or 64 bits, and this disclosure is not limited thereto. The first intermediate plaintext data and the ciphertext data are grouped separately to obtain a third intermediate block and a fourth intermediate block. The third intermediate block (plaintext) is subjected to bitwise XOR with the fourth intermediate block (ciphertext) to obtain the plaintext data. If the block length of the third intermediate block is 64 bits, the high 32 bits of the block may be XORed with the fourth intermediate block, or the data of the full block length (i.e., 64 bits) may be XORed with the fourth intermediate block.

[0137] like Figure 20 As shown, in some embodiments, after step S225, the method further includes:

[0138] S228. Obtain a preset unique value;

[0139] S229: Decrypt the second count vector using a second decryption algorithm, using a preset second key and the unique value, to obtain second intermediate plaintext data;

[0140] S2210. Obtain plaintext data according to the second intermediate plaintext data and the ciphertext data.

[0141] In the embodiment of the present disclosure, the second working mode is extended CTR. In the second working mode, the input data packet length is 32 or 64 bits, the second key length is 128 bits, the second count vector length is 64 bits, and the unique value length is 64 bits.

[0142] like Figure 22 As shown, the second counting vector is decrypted using the second key and the unique value to obtain second intermediate plaintext data, and then the plaintext data is determined based on the second intermediate plaintext data and the ciphertext data. In some embodiments, step S2210 includes: grouping the second intermediate plaintext data according to a specified group length to obtain group three, and grouping the ciphertext data to obtain group four; and performing a bitwise exclusive OR on group three and group four to determine the plaintext data.

[0143] In some embodiments, the second encryption algorithm is a MANTIS encryption algorithm, wherein the unique value is an adjustable value in the MANTIS algorithm.

[0144] The above-disclosed embodiments improve data transmission security by decrypting data transmitted between chiplets. The use of lightweight first and second decryption algorithms enables low-latency and low-power data transmission between chiplets. Confidentiality is enhanced by introducing adjustable and unique values ​​into the first and second encryption algorithms.

[0145] In addition, the operations used in the algorithm structures of the first decryption algorithm and the second decryption algorithm are similar or close, and modules can be reused during hardware implementation, thereby reducing chip development and implementation costs and improving hardware resource utilization efficiency.

[0146] In a third aspect, an embodiment of the present disclosure provides a chip comprising a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, the data transmission method between core particles described in the first aspect or the second aspect is implemented.

[0147] It is worth noting that the chip provided by the embodiment of the present disclosure can be applied to any scenario where encryption and decryption, low power consumption, and low latency are required, such as radio frequency tags, wearable devices, etc.

[0148] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the method for transmitting data between core particles according to the first aspect or the second aspect is implemented.

[0149] In a fifth aspect, an embodiment of the present disclosure provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the data transmission method between core particles described in the first aspect or the second aspect.

[0150] In order to enable those skilled in the art to more clearly understand the technical solutions provided by the embodiments of the present disclosure, the technical solutions provided by the embodiments of the present disclosure are described in detail below through specific examples:

[0151] Example 1:

[0152] For example, Figure 23 As shown, as a specific form of an embodiment of the present disclosure, the encryption and decryption modules are set at the boundary between the custom stream protocol layer and the die-to-die adapter in core particles A and B. When core particle A sends data to core particle B, the data stream is first sent from the internet module of core particle A to the lightweight encryption and decryption module. This lightweight encryption and decryption module can be used to implement the method described in the first or second aspect. The data stream is encrypted in the lightweight encryption and decryption module using the PRINCE algorithm or the MANTIS algorithm and then sent to the DTD adapter.

[0153] The encrypted data stream is sent from the DTD adapter of core particle A to the DTD adapter of core particle B, and then the lightweight encryption and decryption module in core particle B decrypts the encrypted data stream, obtains the plaintext data and sends it to the Internet module in core particle B.

[0154] Among them, the keys of the lightweight encryption and decryption modules in core particles A and B and the parameters involved in encryption and decryption (such as initialization vectors, adjustable values, etc.) can be configured through the hardware security module.

[0155] Example 2:

[0156] For example, Figure 24 As shown, as a specific form of an embodiment of the present disclosure, the hardware security module configures the keys or parameters involved in the encryption and decryption process for the lightweight encryption and decryption module. The interface module of the lightweight encryption and decryption module receives data sent from the Internet (or DTD adapter) of core A, and can determine the working mode of the encryption algorithm or decryption algorithm through the input mode signal. After encryption or decryption processing by the algorithm core, the encrypted ciphertext data or decrypted plaintext data is output to the Internet (or DTD adapter) of core B through the interface module close to core B.

[0157] Reference Figure 8 、 10 ,11,12,The PRINCE algorithm and the MANTIS algorithm have similar structures, and can reuse registers and combinational logic elements. Integrating these reusable registers and combinational logic elements into the same module and implementing interface bit width adaptation through parameterized configuration can reduce chip development and implementation costs and improve hardware resource utilization. The PRINCE algorithm and the MANTIS algorithm can be dynamically switched based on actual needs, optimizing chip performance, power consumption, and area.

[0158] Among them, the processor is a device with data processing capabilities, including but not limited to the central processing unit (CPU); the memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically such as SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read-write interface) is connected between the processor and the memory, which can realize information exchange between the memory and the processor, including but not limited to the data bus (Bus), etc.

[0159] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the apparatus disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0160] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0161] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; compact disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cassettes, tapes, disk storage or other magnetic storage; any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0162] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A data transmission method between chiplets, applied to a first chiplet, comprising: Encrypt plaintext data to obtain ciphertext data; The encrypted data is sent to the second core particle.

2. The method according to claim 1, wherein The encrypting of the plaintext data to obtain the ciphertext data includes: When the working mode of the first core particle is the first working mode, the plaintext data is grouped according to a preset number to obtain the preset number of first data groups; Each of the first data groups is encrypted using a first encryption algorithm and a preset first key to obtain ciphertext data.

3. The method according to claim 2, wherein: After grouping the plaintext data according to a preset number to obtain the preset number of first data groups, the method further includes: Encrypting each of the first data groups using a second encryption algorithm according to a preset first key and a preset first adjustable value to obtain ciphertext data; the first adjustable value includes a first initialization vector and a first count; The first count is incremented by one.

4. The method according to claim 1, wherein The encrypting of the plaintext data to obtain the ciphertext data includes: When the working mode of the first chip is the second working mode, determining a first counting vector according to a preset second initial vector; Encrypting the first count vector using a first encryption algorithm and a preset second key to obtain first intermediate ciphertext data; Ciphertext data is determined according to the first intermediate ciphertext data and the plaintext data.

5. The method according to claim 4, wherein The determining of the ciphertext data according to the first intermediate ciphertext data and the plaintext data includes: Grouping the first intermediate ciphertext data according to a specified group length to obtain first intermediate groups, and grouping the plaintext data to obtain second intermediate groups; Ciphertext data is determined according to the first intermediate group and the second intermediate group.

6. The method according to claim 4, wherein: When the working mode of the first chiplet is the second working mode, after determining the first counting vector according to the preset second initial vector, the method further includes: Encrypting the first count vector using a second encryption algorithm, a preset second key and a preset unique value, to obtain second intermediate ciphertext data; Ciphertext data is obtained according to the second intermediate ciphertext data and the plaintext data.

7. A data transmission method between core particles, applied to a second core particle, comprising: Receiving the ciphertext data sent by the first chip; Decrypt the ciphertext data to obtain plaintext data.

8. The method according to claim 7, wherein: Decrypting the ciphertext data to obtain plaintext data includes: When the working mode of the second core particle is the first working mode, the ciphertext data is grouped according to a preset number to obtain the preset number of second data groups; The first decryption algorithm is used to decrypt each of the second data groups according to a preset first key to obtain plaintext data.

9. The method according to claim 8, wherein After grouping the ciphertext data according to a preset number to obtain the preset number of second data groups, the method further includes: Obtaining a preset second adjustable value; the adjustable value includes a preset third initial vector and a second count; Each of the second data groups is decrypted using a second decryption algorithm according to a preset first key and the second adjustable value to obtain ciphertext data, and the second count in the second adjustable value is increased by one.

10. The method according to claim 7, wherein: Decrypting the ciphertext data to obtain plaintext data includes: When the working mode of the second chiplet is the second working mode, determining a second counting vector according to a preset fourth initial vector; Decrypting the second count vector using a first decryption algorithm and a preset second key to obtain first intermediate plaintext data; Obtain plaintext data according to the first intermediate plaintext data and the ciphertext data.

11. The method according to claim 10, wherein: The obtaining of plaintext data according to the first intermediate plaintext data and the ciphertext data includes: Grouping the first intermediate plaintext data according to a specified group length to obtain a third intermediate group, and grouping the ciphertext data to obtain a fourth intermediate group; Plaintext data is determined based on the third intermediate group and the fourth intermediate group.

12. The method according to claim 10, wherein: After determining the second counting vector according to the preset fourth initial vector, the method further includes: Get the preset unique value; Decrypting the second count vector using a second decryption algorithm, using a preset second key and the unique value, to obtain second intermediate plaintext data; Obtain plaintext data according to the second intermediate plaintext data and the ciphertext data.

13. A chip comprising a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements the data transmission method between core particles according to any one of claims 1 to 12.

14. A computer-readable medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the method for transmitting data between core particles according to any one of claims 1 to 12 is implemented.

15. A computer program product comprising a computer program, wherein when the computer program is executed by a processor, the method for transmitting data between core particles according to any one of claims 1 to 12 is implemented.

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