An arbitrary resolution HDMI prototype verification device and method

Abstract

The application provides an arbitrary resolution HDMI prototype verification device and method, wherein a frame analysis unit analyzes received data packets and stores analyzed image data into a storage unit at a limited clock frequency, a frame extraction unit sequentially extracts each frame image data from the storage unit at a clock frequency corresponding to a corresponding resolution, when the frame extraction unit sequentially extracts previous frame image data, it is judged whether next frame image data is stored in the storage unit; if the next frame image data has been stored, the frame extraction unit extracts the next frame image data; if the next frame image data has not been stored, the frame extraction unit repeatedly extracts the previous frame image data until the next frame image data is stored; the frame extraction unit outputs the extracted image data and performs image display; through the above method, the clock frequency required by any resolution is matched with the limited clock frequency, and corresponding verification is completed.

Description

Technical Field

[0001] This invention relates to the field of signal transmission technology, and in particular to an HDMI prototype verification device and method with arbitrary resolution. Background Technology

[0002] When prototyping High Definition Multimedia Interface (HDMI) at different resolutions, the conventional process is to encapsulate the received audio and video data into data packets according to the HDMI protocol. The Field Programmable Gate Array (FPGA) logic parses the data packets at a certain clock frequency to obtain image data, and then extracts and encodes the image data at the same clock frequency to achieve the corresponding resolution. According to the Video Electronics Standards Association (VESA), different resolutions of image data require different clock frequencies; the higher the resolution, the higher the clock frequency required for image data extraction and imaging.

[0003] However, the existing problem is that different FPGAs have different hardware performance. In the case of poor hardware, the clock frequency is limited, resulting in a lower clock frequency for parsing data packets. This makes it impossible to reach the clock frequency required for most resolutions, and thus FPGAs with poor hardware performance cannot meet the prototype verification requirements for most resolutions.

[0004] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0005] The technical problem this invention aims to solve is how to meet the prototype verification requirements for most resolutions when hardware performance is limited.

[0006] The present invention adopts the following technical solution:

[0007] In a first aspect, an HDMI prototype verification device of arbitrary resolution is provided, comprising: a frame parsing unit, a storage unit, and a frame extraction unit, wherein:

[0008] The frame parsing unit, storage unit, and frame extraction unit are connected in sequence;

[0009] The frame parsing unit is used to parse the received data packets at a first preset clock frequency, obtain each frame of image data in sequence, and store each frame of image data in the storage unit in sequence at the first preset clock frequency.

[0010] The frame extraction unit is configured to determine a second preset clock frequency according to the preset resolution, and sequentially extract each frame of image data from the storage unit at the second preset clock frequency; when the frame extraction unit has sequentially extracted a previous frame of image data, it is determined whether a next frame of image data has been completely stored in the storage unit; if the next frame of image data has been completely stored in the storage unit, the frame extraction unit extracts the next frame of image data; if the next frame of image data has not been completely stored in the storage unit, the frame extraction unit repeatedly extracts the previous frame of image data until the next frame of image data has been completely stored in the storage unit.

[0011] The frame extraction unit is further configured to transmit the extracted image data to a port physical layer, and the port physical layer encodes the image data and displays the image data on a display screen at the preset resolution.

[0012] Preferably, the storage unit comprises at least three storage areas, wherein:

[0013] The at least three storage areas are configured to sequentially store the parsed image data at a first preset clock frequency, and each storage area is configured to store one frame of image data.

[0014] When the image data in the at least three storage areas has been completely stored, the latest frame of image data is overwritten into a storage area corresponding to the last frame of image data in sequence.

[0015] The frame extraction unit is configured to sequentially extract the completely stored image data from the at least three storage areas at a corresponding second preset clock frequency.

[0016] Preferably, the second preset clock frequency is greater than the first preset clock frequency.

[0017] Preferably, the frame parsing unit is configured to parse the received data packet at a first preset clock frequency to sequentially obtain each frame of image data, and specifically comprises:

[0018] The frame parsing unit is configured to obtain binary codes in the data packet, convert positions with a conversion number of 0 and 1 in the binary codes greater than or equal to a first preset number as control islands, and obtain a position of a start code of each frame of image data according to the control islands.

[0019] The frame parsing unit is configured to obtain an encoding length corresponding to the corresponding frame of image data according to the start code of the corresponding frame of image data, so as to obtain a tail code of the corresponding frame of image data.

[0020] The frame parsing unit is configured to parse the corresponding frame of image data from the data packet according to the start code and the tail code of the corresponding frame of image data.

[0021] Preferably, the storing each frame of image data in the storage unit in sequence at the first preset clock frequency comprises:

[0022] The frame parsing unit is configured to acquire the start code and code length of the first frame of image data according to the extracted first frame of image data, store the start code of the first frame of image data to the initial base address in the storage unit, and acquire the tail address of the first frame of image data in the storage unit and the start address of the second frame of image data in the storage unit according to the code length of the first frame of image data.

[0023] The frame parsing unit is configured to acquire the start code and code length of the nth frame of image data according to the extracted nth frame of image data, store the start code of the nth frame of image data to a position after the tail address of the (n-1)th frame of image data, and acquire the tail address of the nth frame of image data in the storage unit and the start address of the (n+1)th frame of image data in the storage unit according to the code length of the nth frame of image data.

[0024] Wherein, n≥2.

[0025] Preferably, the storing each frame of image data in the storage unit in sequence at the first preset clock frequency comprises:

[0026] When the corresponding frame of image data is completely stored in the storage unit, the storage unit is configured to send a storage completion flag corresponding to the corresponding frame of image data to the frame extraction unit.

[0027] The storage completion flag comprises the start address and code length of the corresponding frame of image data.

[0028] Preferably, the frame extraction unit is configured to determine the second preset clock frequency according to the preset resolution, and extract each frame of image data from the storage unit in sequence at the second preset clock frequency, and the determining the second preset clock frequency according to the preset resolution comprises:

[0029] The frame extraction unit is configured to acquire the start address and code length of the corresponding frame of image data according to the received storage completion flag, and the frame extraction unit is also configured to reply a corresponding handshake signal to the storage unit to indicate that the handshake is successful.

[0030] The frame extraction unit is configured to adjust the second preset clock frequency according to the preset resolution, and extract the corresponding frame of image data according to the start address and code length of the corresponding frame of image data at the second preset clock frequency.

[0031] Preferably, the arbitrary resolution HDMI prototype verification device further comprises an HDMI controller, a port physical layer and a display, wherein:

[0032] The HDMI controller is connected with the frame analysis unit, the port physical layer is connected with the frame extraction unit, and the display is connected with the port physical layer;

[0033] The HDMI controller is used for receiving video source data and encapsulating the video source data to obtain data packets, and transmitting the data packets to the frame analysis unit;

[0034] The port physical layer is used for receiving image data from the frame extraction unit, encoding and processing the received image data, and converting the image data into a corresponding video signal, and transmitting the video signal to the display;

[0035] The display is used for decoding the received video signal and displaying the decoded video signal in a corresponding resolution.

[0036] In a second aspect, an arbitrary resolution HDMI prototype verification method is provided, which is used in the arbitrary resolution HDMI prototype verification device and includes the following steps:

[0037] The frame analysis unit analyzes the received data packets at a first preset clock frequency, sequentially obtains each frame of image data, and sequentially stores each frame of image data in the storage unit at the first preset clock frequency;

[0038] The frame extraction unit determines a second preset clock frequency according to a preset resolution, sequentially extracts each frame of image data from the storage unit at the second preset clock frequency, and judges whether the next frame of image data is stored in the storage unit when the frame extraction unit sequentially extracts the previous frame of image data; if the next frame of image data is stored in the storage unit, the frame extraction unit extracts the next frame of image data; if the next frame of image data is not stored in the storage unit, the frame extraction unit repeatedly extracts the previous frame of image data until the next frame of image data is stored in the storage unit;

[0039] The frame extraction unit transmits the extracted image data to the port physical layer, the port physical layer encodes and processes the image data, and displays the image data on the display screen in the preset resolution.

[0040] Preferably, the step of sequentially storing each frame of image data in the storage unit at the first preset clock frequency specifically includes the following steps:

[0041] The storage unit includes at least three storage areas, and the at least three storage areas sequentially store the analyzed image data at the first preset clock frequency, each storage area being used for storing one frame of image data;

[0042] When the image data in the at least three storage areas are all stored, the last frame of image data in all the storage areas is deleted, and the latest frame of image data is overwritten into the storage area corresponding to the last frame of image data in all the storage areas;

[0043] The frame extraction unit extracts the stored image data from the at least three storage areas in sequence at the corresponding second preset clock frequency;

[0044] The second preset clock frequency is greater than the first preset clock frequency.

[0045] Preferably, the frame analysis unit analyzes the received data packet at the first preset clock frequency to obtain each frame of image data in sequence, specifically including:

[0046] The frame analysis unit obtains the binary code in the data packet, and converts the positions with a conversion frequency of 0 and 1 in the binary code being greater than or equal to a first preset frequency as the start code of each frame of image data;

[0047] The frame analysis unit obtains the resolution corresponding to the corresponding frame of image data according to the start code of the corresponding frame of image data, and obtains the encoding length corresponding to the corresponding frame of image data according to the resolution corresponding to the corresponding frame of image data, so as to obtain the tail code of the corresponding frame of image data.

[0048] The frame analysis unit analyzes the corresponding frame of image data from the data packet according to the start code and the tail code of the corresponding frame of image data.

[0049] The application provides an HDMI prototype verification device and method with any resolution, wherein: a frame analysis unit analyzes a received data packet, and stores the analyzed image data into a storage unit at a limited clock frequency; a frame extraction unit extracts each frame of image data from the storage unit in sequence at a clock frequency corresponding to the resolution; when the frame extraction unit extracts a previous frame of image data in sequence, it is determined whether a next frame of image data is stored in the storage unit; if the next frame of image data is stored, the frame extraction unit extracts the next frame of image data; if the next frame of image data is not stored, the frame extraction unit repeatedly extracts the previous frame of image data until the next frame of image data is stored; the frame extraction unit outputs the extracted image data and performs image display; through the above method, the clock frequency required by any resolution is matched with the limited clock frequency, and the corresponding verification is completed. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0051] Figure 1 is a device schematic diagram of an arbitrary resolution HDMI prototype verification device provided by the embodiments of the present application;

[0052] Figure 2 is another device schematic diagram of an arbitrary resolution HDMI prototype verification device provided by the embodiments of the present application;

[0053] Figure 3 is a timing diagram of signal interaction in an arbitrary resolution HDMI prototype verification device provided by the embodiments of the present application;

[0054] Figure 4 is still another device schematic diagram of an arbitrary resolution HDMI prototype verification device provided by the embodiments of the present application;

[0055] Figure 5 is a method flowchart of an arbitrary resolution HDMI prototype verification method provided by the embodiments of the present application;

[0056] Figure 6 is a storage flowchart of a storage unit in an arbitrary resolution HDMI prototype verification method provided by the embodiments of the present application;

[0057] Figure 7 is a method flowchart of image data analysis in an arbitrary resolution HDMI prototype verification method provided by the embodiments of the present application. DETAILED DESCRIPTION

[0058] In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not used to limit the present application.

[0059] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present disclosure and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present disclosure.

[0060] In the description of the present application, the terms "first", "second" are only for descriptive purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality of" is two or more. In addition, for example, in the description, the same type of nouns can also be described as two independent particles by adding "A", "B" at the end, in which case the features defined with "A", "B" are only used for the purpose of distinguishing the same type of particle description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated.

[0061] The "about", "approximately" or "approximately" used in the present application includes the value stated and the average value within the acceptable deviation range of the specific value, wherein the acceptable deviation range is determined by the person skilled in the art considering the measurement being discussed and the error related to the measurement of the specific quantity, i.e. the limitation of the measurement system.

[0062] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is interpreted to mean "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" are intended to mean that the specific feature, structure, material or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner, i.e. although they can be carried by the embodiments or examples of the above terms due to the order of appearance and position, they are not limited to being carried by one embodiment or example in a combined manner.

[0063] In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as there is no conflict.

[0064] The embodiments of the present application provide an arbitrary resolution HDMI prototype verification device, as shown in Figure 1 The frame analysis unit, the storage unit and the frame extraction unit are connected in sequence.

[0065] The frame analysis unit, the storage unit and the frame extraction unit are connected in sequence.

[0066] The frame analyzing unit is configured to analyze the received data packet at a first preset clock frequency, sequentially obtain each frame of image data, and sequentially store each frame of image data in the storage unit at the first preset clock frequency.

[0067] In this embodiment, the data packet is obtained by a High Definition Multimedia Interface (HDMI) controller after receiving video source data, encapsulating audio data and a video data stream in the video source data according to an HDMI protocol, and the image data is in a binary coded form in the data packet. The frame analyzing unit is configured to analyze a frame header, a frame tail and a coding length of a binary code of each frame of image data, so as to analyze each frame of image data from the data packet. The storage unit is configured to temporarily store each analyzed frame of image data, and the stored frame of image data is extracted in a subsequent process. The storage unit can be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR).

[0068] The first preset clock frequency is determined by the performance of hardware in actual conditions, and can be understood as the amount of data that can be processed per second. In the case of excellent hardware performance, the upper limit of the first preset clock frequency is relatively larger, and in the case of poor hardware performance, the upper limit of the first preset clock frequency is relatively smaller. In this embodiment, when poor performance hardware is selected, the frame analyzing unit analyzes the image data in the data packet slowly, and the storage unit stores the analyzed image data at a relatively slow speed.

[0069] In this embodiment, the order is the order in which each frame of image data in the data packet needs to be finally imaged. The image data in the front order needs to be analyzed and extracted first and then imaged and displayed, and the image data in the rear order needs to be analyzed and extracted relatively later and then imaged and displayed.

[0070] The frame extracting unit is configured to determine a second preset clock frequency according to a preset resolution, and sequentially extract each frame of image data from the storage unit at the second preset clock frequency. When the frame extracting unit extracts a previous frame of image data according to the order, it is determined whether a next frame of image data is stored in the storage unit. If the next frame of image data has been stored in the storage unit, the frame extracting unit extracts the next frame of image data. If the next frame of image data has not been stored in the storage unit, the frame extracting unit repeatedly extracts the previous frame of image data until the next frame of image data is stored in the storage unit.

[0071] The frame extraction unit is further configured to transmit the extracted image data to a port physical layer, and the port physical layer encodes the image data and displays the image data on a display screen at the preset resolution.

[0072] The port physical layer is specifically an HDMI physical layer (PHY), and the image data is transmitted on a physical medium.

[0073] In the embodiment, the second preset clock frequency is determined by the preset resolution, and the preset resolution is set by a person skilled in the art according to requirements. When HDMI prototype verification is required for different resolutions, it can be known from Video Electronics Standards Association (VESA) that the clock frequencies required by image data of different resolutions are different, and the formula of the clock frequency is as follows:

[0074] Pixel Clock = Total Pixels per Line × Total Lines per Frame × Frame Rate.

[0075] Pixel Clock is the clock frequency, Total Pixels per Line is the total number of pixels per line in a frame of image data (including the horizontal blanking area), Total Lines per Frame is the total number of lines in a frame of image data (including the vertical blanking area), and Frame Rate is the number of frames transmitted per second (i.e., frame rate).

[0076] It can be known from the above formula that when the frame rate is constant, the greater the resolution, the greater the required clock frequency. For example, when the frame rate is 60, the clock frequency corresponding to the resolution of 640 × 480 is 25.175 MHz, the clock frequency corresponding to the resolution of 800 × 600 is 37.38 MHz, the clock frequency corresponding to the resolution of 1024 × 768 is 64.19 MHz, the clock frequency corresponding to the resolution of 1280 × 720 is 74.25 MHz, the clock frequency corresponding to the resolution of 1920 × 1080 is 148.5 MHz, the clock frequency corresponding to the resolution of 3840 × 2160 is 594 MHz, and the clock frequency corresponding to the resolution of 7680 × 4320 is 2131.2 MHz.

[0077] In summary, in the embodiment, when HDMI prototype verification needs to be performed in scenes with different resolutions, the clock frequency at which the frame extraction unit extracts image data from the storage unit needs to be adjusted accordingly. The frame extraction unit then uploads the extracted image data at the corresponding clock frequency, and after decoding, the image data is displayed on the display screen at the corresponding clock frequency, thereby ensuring that the requirements of the corresponding resolution are met.

[0078] However, a problem exists in that, in conventional image display, the resolution speed of image data needs to be greater than or equal to the extraction speed and imaging speed of image data, so as to ensure the continuity of the final imaging. When the hardware performance is insufficient and the required resolution is high, the clock frequency (which can be understood as the speed) at which the image data is resolved from the data packet is lower than the clock frequency required for imaging at the corresponding resolution, which causes the speed of resolving image data to be unable to keep up with the imaging speed.

[0079] To solve the above problem, in the embodiment, when the frame extraction unit extracts a previous frame of image data each time, it is determined whether a next frame of image data has been completely stored in the storage unit. If the next frame of image data has not been completely stored in the storage unit, the previous frame of image data is repeatedly extracted at a second preset clock frequency until the next frame of image data is completely stored, and then the next frame of image data is extracted at the second preset clock frequency. In this way, the continuous extraction and imaging of image data at the second preset clock frequency is ensured, and the data processing amount per second (i.e., the clock frequency) meets the requirements of the preset resolution. In terms of the imaging perception of the display screen, since the image data is still imaged in the original order, only the duration of each frame of image data is slightly extended, so the overall perception is not greatly affected, and the HDMI prototype verification is not affected. In summary, the embodiment can achieve HDMI prototype verification under different resolutions of image data with poor hardware configuration.

[0080] Further, in the embodiment, due to the limited capacity of the storage unit, the least space is occupied to achieve the corresponding function for performance considerations.

[0081] In the prior process, if the resolution clock frequency of the data image and the extraction clock frequency of the data image are consistent, two areas in the storage unit are divided, which can store two different image data at the same time, for example, after the first area stores the first frame of data image, the second area starts to store the second frame of data image, and the first frame of data image stored in the first area is extracted and imaged. Since the resolution clock frequency of the data image and the extraction imaging frequency of the data image are consistent, when the first frame of data image is extracted and imaged, the storage of the second frame of data image in the second area is completed, and the extraction and imaging of the second frame of data image stored in the second area can be started. At the same time, the third frame of image is overlaid on the first frame of data image in the first area, and the process is repeated. In the case that the resolution clock frequency of the data image and the extraction clock frequency of the data image are consistent, the storage unit can store at least two different image data at the same time to realize the recycling storage and extraction imaging process, and the corresponding process is realized under the premise of occupying the least storage space.

[0082] In the embodiment, considering that the second preset clock frequency of the frame extraction unit is much greater than the first preset clock frequency of the storage unit for storing image data, in this case, the frame extraction unit will extract the previous frame of image data stored completely, but the next frame of image data has not been stored completely in the storage unit. In this case, the frame extraction unit will repeatedly extract the previous frame of image data stored completely, and wait for the next frame of image data to be stored completely in the storage unit. Further, in this process, the next frame of image data may be stored completely, but the frame extraction unit has not extracted the repeatedly extracted previous frame of image data completely. At this time, the storage unit needs to continue to store the third frame of image data (i.e. the next frame of image data). If the storage unit is provided with only two areas for storing different image data at the same time as in the prior process, the third frame of image data can only be overlaid on the area of the previous frame of image data. However, since the frame extraction unit is still extracting the previous frame of image data at this time, the currently extracted previous frame of image data may be contaminated by the third frame of image data, resulting in imaging error. Therefore, in order to avoid the above problems, the embodiment also relates to the following design:

[0083] As Figure 2As shown, the storage unit includes at least three storage areas, wherein: the at least three storage areas are used to sequentially store the parsed image data in order at a first preset clock frequency, and each storage area is used to store one frame of image data. When the image data in the at least three storage areas is all stored, the latest one frame of image data is overwritten into the storage area corresponding to the last one frame of image data in order in all storage areas. The frame extraction unit is used to sequentially extract the stored image data from the at least three storage areas in order at a corresponding second preset clock frequency. The second preset clock frequency is greater than the first preset clock frequency.

[0084] In this embodiment, the last one frame of image data in order in all storage areas is the last one frame of image data stored in the three areas in terms of storage order; if the storage unit is divided into three storage areas (i.e., storage area A, storage area B and storage area C in Figure 2 The storage and extraction of the first frame of data image, the second frame of data image and the third frame of data image in the case of setting three storage areas are described below:

[0085] When the frame extraction unit has completed the extraction of the first frame of image data that has been stored, but the second frame of image data has not been stored in the storage unit, the frame extraction unit repeatedly extracts the first frame of image data that has been stored in this case, waits for the second frame of image data to be stored in the storage unit, and further, in this process, the second frame of image data may be stored, but the frame extraction unit has not completed the extraction of the repeatedly extracted first frame of image data, at this time, the storage unit needs to continue to store the third frame of image data, and since there are three storage areas, the third frame of image data can be stored in the third storage area without overwriting the first image data. After the frame extraction unit completes the extraction of the repeatedly extracted first frame of image data, the frame extraction unit extracts the second frame of image data, avoiding the problem that the image data being extracted is overwritten due to insufficient storage area, and further causing the image to be contaminated.

[0086] Further, in this embodiment, when the frame analysis unit analyzes each frame of image data from the data packet, the frame header and the frame tail corresponding to each frame of image data need to be obtained, i.e., the start code and the tail code of the binary code of each frame of image data in the data packet, so as to determine the position of each frame of image data in the data packet, so as to analyze and subsequently store each frame of image data. Therefore, the present embodiment also relates to the following design:

[0087] The frame analysis unit is used to analyze the received data packet at a first preset clock frequency to sequentially obtain each frame of image data, specifically including:

[0088] The frame analysis unit is configured to obtain the binary code in the data packet, and convert the positions where the number of times of conversion between 0 and 1 in the binary code is greater than or equal to a first preset number as control islands, and obtain the position of the start code of each frame image data according to the control islands.

[0089] In this embodiment, the number of times of conversion between 0 and 1 in the binary code of the data in the video data island (Video Data Period) and the data island (Data Island Period) is less than or equal to 5, and the number of times of conversion between 0 and 1 in the binary code of the data in the control island is greater than or equal to 7. The control island is analyzed by the number of times of conversion between 0 and 1, and the control island contains a horizontal synchronization signal (Horizontal Synchronization, abbreviated as HSYNC) and a vertical synchronization signal (Vertical Synchronization, abbreviated as VSYNC). When the VSYNC in the control island is detected as a falling edge and the control island is 1000 (binary), the control island is marked as the position of the start code of the current frame image data.

[0090] In this embodiment, the first preset number is set by a person skilled in the art according to actual conditions, and in this embodiment, the first preset number can be 7. The binary code of the data content part in each frame image data has the feature that the number of times of conversion between 0 and 1 in the binary code is less than or equal to 5. Therefore, according to the number of times of conversion between 0 and 1 in the binary code, the start code position of each frame image and the position of the data content can be determined.

[0091] The frame analysis unit is configured to obtain the corresponding code length of the corresponding frame image data according to the start code of the corresponding frame image data, so as to obtain the tail code of the corresponding frame image data. The frame analysis unit is configured to parse the corresponding frame image data from the data packet according to the start code and the tail code of the corresponding frame image data.

[0092] Further, the start code of each frame image data also contains information of the code length of the image data. Therefore, after the start code of each frame image data is parsed, the code length of the image data can be known. According to the start code and the code length, the tail code of the image data can be calculated, the coding positioning of the image data is realized, the complete parsing of the frame image data is recovered from the data packet, and the corresponding code of the frame image data is stored in the storage unit.

[0093] Further, after the frame analysis unit analyzes the image data, the corresponding image data needs to be stored in the storage unit. During the storage process, the starting code and tail code of each frame of image data in the storage unit need to be found to ensure that each frame of image data is stored in the specified position in the storage unit in order to ensure the correlation before and after the process. Therefore, the embodiment also relates to the following design:

[0094] The first preset clock frequency is used to store each frame of image data in the storage unit in order, and specifically includes:

[0095] The frame analysis unit is used to obtain the starting code and code length of the first frame of image data according to the extracted first frame of image data, store the starting code of the first frame of image data in the initial base address in the storage unit, and obtain the tail address of the first frame of image data in the storage unit and the starting address of the second frame of image data in the storage unit according to the code length of the first frame of image data.

[0096] The frame analysis unit is used to obtain the starting code and code length of the nth frame of image data according to the extracted nth frame of image data, store the starting code of the nth frame of image data in the position after the tail address of the (n-1)th frame of image data in the storage unit, and obtain the tail address of the nth frame of image data in the storage unit and the starting address of the (n+1)th frame of image data in the storage unit according to the code length of the nth frame of image data; wherein n≥2.

[0097] The first frame of image data is the image data ranked first in the data packet, and the frame of image data is the first image data analyzed, stored, extracted, and decoded into an imaging image data in the data packet. After the frame analysis unit analyzes the first frame of image data, the storage unit obtains the starting code, code length, and tail code of the first frame of image data. The initial base address is an address set by the storage unit before the entire process starts and is initialized, and is used as the storage position of the starting code of the first frame of image data analyzed in the entire process. After the starting address of the first frame of image data in the storage unit is determined, the tail address of the first frame of image data in the storage unit can be calculated according to the starting address and the code length of the first frame of image data. Since the storage position of the next frame of image data in the storage unit is immediately after the previous frame of image data, the starting address of the next frame of image data is after the tail address of the previous frame of image data. Therefore, the starting address of the second frame of image data in the storage unit can be obtained according to the tail address of the first frame of image data.

[0098] Further, since the frame extraction unit needs to ensure that the frame image data has been completely stored in the storage unit before extracting the frame image data, the frame extraction unit needs to be informed whenever a frame image data has been completely stored in the storage unit, so that the frame extraction unit extracts the corresponding frame image data based on the information. Therefore, the embodiment also relates to the following design:

[0099] As shown in Figure 1 , the storage unit stores each frame image data in the storage unit in sequence at the first preset clock frequency, and further includes that when the corresponding frame image data has been completely stored in the storage unit, the storage unit sends a storage completion flag corresponding to the corresponding frame image data to the frame extraction unit, and the storage completion flag includes the starting address and the encoding length of the corresponding frame image data.

[0100] The frame extraction unit acquires the starting address and the encoding length of the corresponding frame image data according to the received storage completion flag, and further sends a corresponding handshake signal to the storage unit to indicate that the handshake is successful. The frame extraction unit adjusts the second preset clock frequency according to the preset resolution, and extracts the corresponding frame image data according to the starting address and the encoding length of the corresponding frame image data at the second preset clock frequency.

[0101] In the embodiment, the frame extraction unit judges whether the current frame image has been completely stored according to the storage completion flag corresponding to each frame image sent by the storage unit, as shown in the timing diagram in Figure 3 . When the storage completion flag of the corresponding image data (i.e. VALID in Figure 3 ) is pulled high, it represents that the frame image data has been completely stored, and the frame extraction unit sends a high-level handshake signal (i.e. READY in Figure 3 ) to the storage unit to inform the storage unit that the corresponding image data has been started to be extracted. After the handshake signal is received by the storage unit (i.e. the handshake signal is pulled low), the storage unit pulls the storage completion flag of the corresponding image data low, and then the frame extraction unit extracts the corresponding image data from the storage unit and sends it to the subsequent port physical layer. The starting address and the encoding length in the storage completion flag can be used by the frame extraction unit to find the position of the corresponding image data in the storage unit. Figure 3 For example, at T0, the storage unit sends the storage completion flag to the frame extraction unit, and the frame extraction unit receives the storage completion flag at T5. At this time, the frame extraction unit sends a high-level handshake signal to the storage unit, so that the handshake signal becomes high at T5, and the storage unit receives the handshake signal at T6, so that the storage completion flag is restored to low.

[0102] When the frame extraction unit finishes extracting a frame of image data, it will re-determine whether the current storage completion flag is pulled high. If it is not pulled high, the frame extraction unit will repeat the extraction operation of the previous frame of image data until the storage completion flag of the next frame is pulled high.

[0103] It should be noted that, as shown in Figure 3 , the storage completion flag (i.e. VALID in Figure 3 ) and the handshake signal (i.e. READY in Figure 3 ) in the embodiment are single-bit signals, and the start address (i.e. ADDR in the figure) and the encoding length (i.e. LENGTH in the figure) of the corresponding frame of image data in the storage completion flag are multi-bit signals.

[0104] Further, in the embodiment, to implement HDMI prototype verification at different resolutions, other necessary devices are also needed, as follows:

[0105] As shown in Figure 4 , the HDMI prototype verification device at any resolution further comprises an HDMI controller, a port physical layer, and a display, wherein:

[0106] The HDMI controller is connected to the frame parsing unit, the port physical layer is connected to the frame extraction unit, and the display is connected to the port physical layer; the HDMI controller is configured to receive video source data, encapsulate the video source data to obtain a data packet, and send the data packet to the frame parsing unit; the port physical layer is configured to receive image data from the frame extraction unit, encode and format-convert the received image data to obtain a corresponding video signal, and transmit the video signal to the display; and the display is configured to decode the received video signal and display the decoded video signal at a corresponding resolution.

[0107] In the embodiment, the HDMI controller is configured to receive audio and video data transmitted from a host, such as video in red-green-blue / luminance-chrominance density format and pulse code modulation audio, compress and format-convert the audio and video data, such as converting to 8-bit or 10-bit encoding and color space conversion, encapsulate the audio and video data into a data packet according to the HDMI protocol, such as including a video data period and a data packet period, and generate a control signal, such as a vertical synchronization signal and a horizontal synchronization signal, in addition to the audio and video data, including auxiliary signals, such as extended display identification data reading and consumer electronics control.

[0108] The port physical layer is used to convert the data packet or the extracted frame image data from digital signal to analog signal suitable for transmission on physical media, such as Transition Minimized Differential Signaling (TMDS), and the port physical layer transmits the analog signal to the display through the cable, and the display images the analog signal.

[0109] Specifically, the port physical layer encodes the received image data according to the requirements of the HDMI protocol, converts the processed video signal into TMDS format, and transmits it in the form of differential signal, that is, outputs it to the display through a pair of differential lines. After receiving the TMDS signal, the display decodes it. The decoded video signal is sent to the internal processing unit of the display, such as an image processing chip. The internal processing unit further processes the video signal, such as color correction, contrast adjustment, resolution adaptation, etc.; finally, clear and smooth images are presented on the screen.

[0110] On the basis of the above-mentioned device, before the entire method flow begins, the configuration of each device needs to be initialized in advance, including:

[0111] The configuration register, working mode and display subsystem of the HDMI controller are initialized; the storage unit is verified by accurately configuring the power supply, timing and signal calibration functions to ensure that the memory subsystem operates in the best state; the initialization of the frame parsing unit and the frame extraction unit includes configuring the initial base address and register initialization; the initialization of the port physical layer includes configuring the register, performing link training, setting the power management state and link state management.

[0112] The embodiment further provides an arbitrary resolution HDMI prototype verification method based on the arbitrary resolution HDMI prototype verification device, which is applied to the arbitrary resolution HDMI prototype verification device, as shown in the figure, including: Figure 5

[0113] In step 101, the frame parsing unit parses the received data packet at a first preset clock frequency, sequentially obtains each frame of image data, and stores each frame of image data in the storage unit in order at the first preset clock frequency.

[0114] ​In step 102, the frame extraction unit determines a second preset clock frequency according to the preset resolution, and sequentially extracts each frame image data from the storage unit at the second preset clock frequency. When the frame extraction unit extracts the previous frame image data in sequence, it is determined whether the next frame image data is stored in the storage unit. If the next frame image data has been stored in the storage unit, the frame extraction unit extracts the next frame image data. If the next frame image data has not been stored in the storage unit, the frame extraction unit repeatedly extracts the previous frame image data until the next frame image data is stored in the storage unit.

[0115] In step 103, the frame extraction unit transmits the extracted image data to the port physical layer, and the port physical layer encodes and processes the image data and displays the image on the display screen at the preset resolution.

[0116] In this embodiment, considering that the clock frequency of the frame extraction unit is much greater than the clock frequency of the storage unit for storing image data, in this case, the frame extraction unit will inevitably extract the previous frame image data that has been stored, but the next frame image data has not been stored in the storage unit. In this case, the frame extraction unit repeatedly extracts the previous frame image data that has been stored, and waits for the next frame image data to be stored in the storage unit. Further, in this process, the next frame image data may be stored, but the frame extraction unit has not yet extracted the repeatedly extracted previous frame image data. At this time, the storage unit needs to continue to store the third frame image data (i.e., the next next frame image data). If the storage unit is only provided with two areas for simultaneously storing different image data as in the existing process, the third frame image data can only be overlaid on the area of the previous frame image data. However, since the frame extraction unit is still extracting the previous frame image data at this time, it may cause the currently extracted previous frame image data to be contaminated by the third frame image data, resulting in imaging errors. Therefore, in order to avoid the above problems, as shown in the figure, the present embodiment also relates to the following design: Figure 6

[0117] In step 201, the storage unit includes at least three storage areas, and the at least three storage areas sequentially store the parsed image data at a first preset clock frequency. Each storage area is used to store one frame of image data.

[0118] In step 202, when the image data in the at least three storage areas is stored, the latest frame of image data is overlaid in the storage area corresponding to the last frame of image data in sequence.

[0119] ​In step 203, the frame extraction unit extracts the stored image data from the at least three storage areas in sequence according to a corresponding second preset clock frequency; wherein the second preset clock frequency is greater than the first preset clock frequency.

[0120] Further, in the embodiment, when the frame analysis unit analyzes each frame image data from the data packet, the frame head and the frame tail corresponding to each frame image data, i.e. the start code and the tail code of the binary code of each frame image data in the data packet, are needed to be obtained, so as to determine the position of each frame image data in the data packet, so as to analyze and subsequently store each frame image data. Therefore, the embodiment also relates to the following design, as shown in Figure 7

[0121] In step 301, the frame analysis unit obtains the binary code in the data packet, and converts the positions with the conversion times of 0 and 1 in the binary code greater than or equal to a first preset number as control islands, and obtains the position of the start code of each frame image data according to the control islands.

[0122] Wherein, the first preset number can be 7.

[0123] In step 302, the frame analysis unit obtains the resolution corresponding to the corresponding frame image data according to the start code of the corresponding frame image data, and obtains the encoding length corresponding to the corresponding frame image data according to the resolution corresponding to the corresponding frame image data, so as to obtain the tail code of the corresponding frame image data.

[0124] In step 303, the frame analysis unit analyzes the corresponding frame image data from the data packet according to the start code and the tail code of the corresponding frame image data.

[0125] The above only describes the preferred embodiments of the present application and is not used to limit the present application, and any modification, equivalent replacement and improvement within the spirit and principle of the present application should be included in the protection scope of the present application.​

Claims

1. An arbitrary resolution HDMI prototype verification device, comprising: The application relates to a frame analysis unit, a storage unit and a frame extraction unit, wherein the frame analysis unit, the storage unit and the frame extraction unit are sequentially connected; the frame analysis unit is used for analyzing received data packets at a first preset clock frequency to sequentially obtain each frame of image data and sequentially storing each frame of image data in the storage unit at the first preset clock frequency; the frame extraction unit is used for determining a second preset clock frequency according to a preset resolution and sequentially extracting each frame of image data from the storage unit at the second preset clock frequency; when the frame extraction unit sequentially extracts a previous frame of image data, it is judged whether a next frame of image data is stored in the storage unit; if the next frame of image data has been stored in the storage unit, the frame extraction unit extracts the next frame of image data; if the next frame of image data has not been stored in the storage unit, the frame extraction unit repeatedly extracts the previous frame of image data until the next frame of image data is stored in the storage unit; the frame extraction unit is further used for transmitting the extracted image data to a port physical layer, and the port physical layer encodes the image data and displays the image data on a display screen at the preset resolution; the storage unit comprises at least three storage areas, wherein the at least three storage areas are used for sequentially storing the analyzed image data at the first preset clock frequency, each storage area is used for storing one frame of image data, when the image data in the at least three storage areas are all stored, the latest frame of image data is overwritten into a storage area corresponding to the last frame of image data in sequence in all the storage areas, and the frame extraction unit is used for sequentially extracting the stored image data from the at least three storage areas at the corresponding second preset clock frequency; and the second preset clock frequency is greater than the first preset clock frequency. The frame analysis unit is used for analyzing received data packets at a first preset clock frequency to sequentially obtain each frame of image data, which comprises the following steps: the frame analysis unit is used for obtaining binary codes in the data packets, converting positions with a conversion frequency of 0 and 1 in the binary codes which is greater than or equal to a first preset frequency as control islands, and obtaining the position of the starting code of each frame of image data according to the control islands; the frame analysis unit is further used for obtaining the encoding length corresponding to the corresponding frame of image data according to the starting code of the corresponding frame of image data, so as to obtain the tail code of the corresponding frame of image data; and the frame analysis unit is further used for analyzing the corresponding frame of image data from the data packets according to the starting code and the tail code of the corresponding frame of image data. The frame analysis unit is used for obtaining the starting code and the encoding length of the first frame of image data according to the extracted first frame of image data, storing the starting code of the first frame of image data into an initial base address in the storage unit, and obtaining the tail address of the first frame of image data in the storage unit and the starting address of the second frame of image data in the storage unit according to the encoding length of the first frame of image data. ​ ​ ​ ​ 2. The arbitrary resolution HDMI prototype verification apparatus of claim 1, wherein, ​ ​ ​ ​ 3. The arbitrary resolution HDMI prototype verification apparatus of claim 2, wherein, ​ ​ The frame analyzing unit is further configured to obtain a start code and a code length of the nth frame of image data according to the extracted nth frame of image data, store the start code of the nth frame of image data to a position after a tail address of the (n-1)th frame of image data, and obtain a tail address of the nth frame of image data in the storage unit and a start address of the (n+1)th frame of image data in the storage unit according to the code length of the nth frame of image data. Wherein, n≥2.

4. The arbitrary resolution HDMI prototype verification apparatus of claim 3, wherein, The storage of each frame of image data in the storage unit in sequence at the first preset clock frequency further comprises: When the corresponding frame of image data is completely stored in the storage unit, the storage unit is configured to send a storage completion flag corresponding to the corresponding frame of image data to the frame extracting unit, wherein the storage completion flag comprises a start address and a code length of the corresponding frame of image data.

5. The arbitrary resolution HDMI prototype verification apparatus of claim 4, wherein, The frame extracting unit is configured to determine a second preset clock frequency according to the preset resolution, and extract each frame of image data from the storage unit in sequence at the second preset clock frequency, which comprises: The frame extracting unit is configured to obtain the start address and the code length of the corresponding frame of image data according to the received storage completion flag, and the frame extracting unit is further configured to return a corresponding handshake signal to the storage unit to indicate that the handshake is successful. The frame extracting unit is configured to adjust the second preset clock frequency according to the preset resolution, and extract the corresponding frame of image data according to the start address and the code length of the corresponding frame of image data at the second preset clock frequency.

6. The arbitrary resolution HDMI prototype verification apparatus of any of claims 1 to 5, wherein, Further comprising: An HDMI controller, a port physical layer and a display, wherein: The HDMI controller is connected with the frame analyzing unit, the port physical layer is connected with the frame extracting unit, and the display is connected with the port physical layer; The HDMI controller is configured to receive video source data and encapsulate the video source data to obtain a data packet, and send the data packet to the frame analyzing unit; The port physical layer is configured to receive image data from the frame extracting unit, encode and format-convert the received image data to obtain a corresponding video signal, and transmit the video signal to the display; The display is configured to decode the received video signal and display the decoded video signal in a corresponding resolution.

7. An arbitrary resolution HDMI prototype verification method for use on an arbitrary resolution HDMI prototype verification device as claimed in any one of claims 1 to 6, characterized by, Comprising: The frame analyzing unit analyzes the received data packet at a first preset clock frequency, obtains each frame of image data in sequence, and stores each frame of image data in the storage unit in sequence at the first preset clock frequency; The frame extracting unit determines a second preset clock frequency according to the preset resolution, and extracts each frame of image data from the storage unit in sequence at the second preset clock frequency, and when the frame extracting unit extracts a previous frame of image data in sequence, judges whether a next frame of image data is completely stored in the storage unit; If the next frame of image data is completely stored in the storage unit, the frame extracting unit extracts the next frame of image data; If the next frame of image data is not completely stored in the storage unit, the frame extracting unit repeatedly extracts the previous frame of image data until the next frame of image data is completely stored in the storage unit; The frame extraction unit transmits the extracted image data to a port physical layer, and the port physical layer encodes the image data and displays the image data on a display screen at the preset resolution.

8. The arbitrary resolution HDMI prototype verification method of claim 7, wherein, The storing of each frame of image data in the storage unit in sequence at the first preset clock frequency comprises: The storage unit comprises at least three storage areas, and the at least three storage areas sequentially store the parsed image data in sequence at the first preset clock frequency, each storage area being used for storing one frame of image data; When the image data in the at least three storage areas are all stored, the latest frame of image data is overwritten into the storage area corresponding to the last frame of image data in sequence in all the storage areas; The frame extraction unit sequentially extracts the stored image data from the at least three storage areas in sequence at the corresponding second preset clock frequency. The second preset clock frequency is greater than the first preset clock frequency.

9. The arbitrary resolution HDMI prototype verification method of claim 7, wherein, The frame parsing unit parses the received data packet at the first preset clock frequency to sequentially obtain each frame of image data, which comprises: The frame parsing unit obtains the binary code in the data packet, converts the 0 and 1 in the binary code, and takes the position at which the conversion times are greater than or equal to a first preset number of times as a control island, and obtains the position of the start code of each frame of image data according to the control island; The frame parsing unit obtains the resolution corresponding to the corresponding frame of image data according to the start code of the corresponding frame of image data, obtains the encoding length corresponding to the corresponding frame of image data according to the resolution corresponding to the corresponding frame of image data, and thus obtains the tail code of the corresponding frame of image data; The frame parsing unit parses the corresponding frame of image data from the data packet according to the start code and the tail code of the corresponding frame of image data.

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