Double-decoupling parallel random number generator and random computing system

Abstract

The invention relates to a dual-decoupling parallel random number generator and a random computing system, which are characterized in that a unique dual-decoupling architecture is designed by adopting a basic architecture of a binary sampler, and the random number generator can be used for generating parallel random numbers on the basis of a dual-decoupling mechanism on the premise of not introducing complex generation logic and huge hardware overhead. High-quality and low-correlation random bit streams are generated through cooperative work of the random number generation core and the parallel comparison core. Due to the characteristics of low correlation and low cost, the method is particularly suitable for an SC system needing large-scale parallel computing, computing errors caused by correlation can be remarkably reduced, the contradictory requirements of simple hardware implementation, low expenditure and high-quality low-correlation bit stream generation are met, and the precision and reliability of the whole system are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a doubly decoupled parallel random number generator and a random computing system. Background Art

[0002] In stochastic computing (SC) systems, the random number generator (SNG) is the most fundamental core functional unit, responsible for converting deterministic binary values ​​into random bit streams for probabilistic operations. In high-performance parallel SC hardware architectures (such as systolic arrays), to conserve significant hardware resources, multiple computing units often need to share the same set of random number generators. However, this sharing mechanism also introduces new technical challenges, such as bitstream correlation. When random bit streams for different operands (such as activation values ​​and weights in neural networks) are generated by the same or similarly structured random number generators, these random bit streams exhibit a high degree of statistical correlation. This correlation seriously violates the fundamental mathematical assumption of probabilistic independence underlying SC multiplication operations, leading to large, unpredictable computational errors and severely impacting the accuracy of the entire SC system.

[0003] To address this correlation issue, existing technologies use simple, shared linear feedback shift registers (LFSRs) as randomness sources. While this approach offers extremely low hardware cost, the highly structured sequences it generates result in extremely high correlation, failing to meet accuracy requirements. Furthermore, existing technologies employ complex sequences from cryptography or quasi-Monte Carlo methods, such as low-discrepancy sequences (LDS). While these sequences can achieve good low correlation, their generation logic is complex and the hardware overhead is significant, making them impractical for large-scale parallel deployment in resource-constrained edge devices. Therefore, a new random number generator solution is urgently needed that meets the conflicting requirements of simple hardware implementation and low overhead while generating high-quality, low-correlation bitstreams. Summary of the Invention

[0004] Based on this, it is necessary to provide a doubly decoupled parallel random number generator and a random computing system that can simultaneously meet the contradictory requirements of simple and low-overhead hardware implementation and the generation of high-quality low-correlation bit streams.

[0005] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a double-decoupled parallel random number generator is provided, including a random number generation core and a parallel comparison core, the parallel comparison core includes 128 parallel calculation logics, each calculation logic is composed of cascaded XOR gates and comparators; The random number generation core is used to generate a 7-bit random number in each working cycle. The parallel comparison core is used to perform XOR operations on the random number with 128 deterministic constants in parallel within a single working cycle to obtain 128 randomization thresholds. The input 7-bit unsigned binary value is compared with each randomization threshold to generate a 128-bit random bit stream. Among them, if the 7-bit unsigned binary value is greater than the randomization threshold, the corresponding bit value in the generated random bit stream is 1, otherwise it is 0. A double decoupling mechanism is used between two parallel random number generators to generate heterogeneous random sources and calculate orthogonal thresholds; the double decoupling mechanism includes decoupling at the random source level and decoupling at the deterministic comparison framework level.

[0006] In one embodiment, when two parallel random number generators are used, the first parallel random number generator generates a random bit stream corresponding to a first operand and the second parallel random number generator generates a random bit stream corresponding to a second operand: The first primitive polynomial used by the first parallel random number generator is: P1= x 7 + x 6 +1 The second primitive polynomial used by the second parallel random number generator is: P2= x 7 + x 3 +1 in, x A 7-bit unsigned integer representing the input. Two parallel random number generators are initialized with different non-zero seeds.

[0007] In one embodiment, in two parallel random number generators, the 128 deterministic constants used by the parallel comparison core of the first parallel random number generator are a forward linear sequence, and the 128 deterministic constants used by the parallel comparison core of the second parallel random number generator are a bit-flipped linear sequence.

[0008] In another aspect, a random computing system is provided, comprising a parallel computing array and at least one doubly decoupled parallel random number generator, wherein the doubly decoupled parallel random number generator is configured to provide a random bit stream to each computing unit in the parallel computing array in a resource-sharing manner, and the parallel computing array is configured to perform random computing tasks based on the random bit stream; wherein the doubly decoupled parallel random number generator comprises a random number generation core and a parallel comparison core, wherein the parallel comparison core comprises 128 parallel computing logics, each of which is composed of a cascaded XOR gate and a comparator; The random number generation core is used to generate a 7-bit random number in each working cycle. The parallel comparison core is used to perform XOR operations on the random number with 128 deterministic constants in parallel within a single working cycle to obtain 128 randomization thresholds. The input 7-bit unsigned binary value is compared with each randomization threshold to generate a 128-bit random bit stream. Among them, if the 7-bit unsigned binary value is greater than the randomization threshold, the corresponding bit value in the generated random bit stream is 1, otherwise it is 0. A double decoupling mechanism is used between two parallel random number generators to generate heterogeneous random sources and calculate orthogonal thresholds; the double decoupling mechanism includes decoupling at the random source level and decoupling at the deterministic comparison framework level.

[0009] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned doubly decoupled parallel random number generator and random computation system utilizes a unique dual-decoupling architecture based on a "binary sampler" infrastructure. This dual-decoupling mechanism allows the random number generation core and parallel comparison core to work together to generate high-quality, low-correlation random bit streams, without introducing complex generation logic and significant hardware overhead. This low-correlation, low-cost feature is particularly well-suited for SC systems requiring large-scale parallel computing, significantly reducing computational errors caused by correlation. This addresses the conflicting requirements of simple and low-overhead hardware implementation and the generation of high-quality, low-correlation bit streams, thereby improving the accuracy and reliability of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings constituting a part of this application are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 The figure is a block diagram of the overall structure of a double-decoupled parallel random number generator in one embodiment; Figure 2 Schematic diagram of a dual decoupling strategy in one embodiment; Figure 3 A schematic diagram of a shared application of DD-SNG in a parallel computing system such as a systolic array according to an embodiment; Figure 4FIG2 is a schematic diagram showing a comparison between DD-SNG and the prior art in terms of bitstream correlation and hardware overhead in one embodiment; Figure 4 (a) is the bit stream correlation analysis, Figure 4 (b) is the hardware cost and performance analysis. DETAILED DESCRIPTION

[0013] To make the above-mentioned objects, features, and advantages of the present invention more readily apparent, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following description sets forth numerous specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0014] The following describes the implementation of the present invention in detail with reference to the accompanying drawings in the embodiments of the present invention.

[0015] In one embodiment, see Figure 1 , provides a double-decoupled parallel random number generator 100, including a random number generation core 110 and a parallel comparison core 120, the parallel comparison core 120 includes 128 parallel calculation logics, each of which is composed of cascaded XOR gates and comparators. The random number generation core 110 is used to generate a 7-bit random number in each working cycle, and the parallel comparison core 120 is used to perform XOR operations on the random number with 128 deterministic constants in parallel within a single working cycle to obtain 128 randomization thresholds, and compare the input 7-bit unsigned binary value with each randomization threshold to generate a 128-bit random bit stream. Among them, if the 7-bit unsigned binary value is greater than the randomization threshold, the value of the corresponding bit in the generated random bit stream is 1, otherwise it is 0. A double decoupling mechanism is used between the two parallel random number generators 100 to generate heterogeneous random sources and orthogonal threshold calculations; the double decoupling mechanism includes decoupling at the random source level and decoupling at the deterministic comparison framework level.

[0016] It can be understood that this embodiment designs the above-mentioned doubly decoupled parallel random number generator (which can be abbreviated as DD-SNG) based on the basic architecture of "binary sampler". Its core innovation lies in: by systematically and asymmetric configuring the bitstream generation process for different operands (for example, the first operand "activation value" and the second operand "weight") at two independent and orthogonal levels, the structural relationship between bitstreams is fundamentally destroyed at a very low hardware resource cost.

[0017] The overall architecture and working principle of the double-decoupled parallel random number generator 100 are as follows: like Figure 1As shown, the dual decoupled parallel random number generator 100 adopts a "binary sampler" infrastructure, which includes a random number generation (RNG) core 110 and a parallel comparison core 120. The dual decoupled parallel random number generator 100 works to convert an input 7-bit unsigned binary value into value , converted into a 128-bit random bit stream SN .

[0018] The random number generation core 110 is, for example, a pseudo-random number generator, which is used to generate a 7-bit random number (denoted as r_t ), Figure 1 In the embodiment, the random number generation core 110 can be a linear feedback shift register (LFSR), which includes an XOR gate and flip-flops. R1 to R7 represent seven flip-flops connected in series, respectively, to form a 7-bit shift register. The XOR gate is used to implement feedback logic, and its input is connected to a specific tap of the shift register (e.g., Figure 1 The output of the 7-bit shift register is connected to the input of the first-stage flip-flop R1. The current state value of the entire 7-bit shift register is used as a 7-bit random number. r_t Output.

[0019] The parallel comparison core 120 includes a set of (for example, 128) 7-bit deterministic constants (denoted as D [ i ],in i =0, 1, ..., 127) and corresponding calculation logic. When working, the first i The calculation logic (composed of XOR gates and comparators) first converts the random number r_t With the i deterministic constant D [ i ]After an XOR operation is performed through an XOR gate, a randomized threshold is obtained (denoted as Threshold_i = D [ i ] XOR r_t ). Then, a comparator CMP is used to input the 7-bit unsigned binary value. value With the randomization threshold Threshold_i Compare. If the 7-bit unsigned binary value value Greater than the randomization threshold Threshold_i , then the generated random bit stream is i Bit SN [ i ] is 1; otherwise, the first i Bit SN [i ] is 0. Since the parallel comparison core 120 includes 128 parallel calculation logics, the complete 128-bit random bit stream SN Can be generated in parallel within a single work cycle.

[0020] Regarding the double decoupling mechanism: Figure 2 As shown, the mechanism is implemented through a structured, step-by-step process, ensuring that the first operand (such as the activation value X ) and the second operand (such as weight W ) has a high degree of independence between the random bit streams generated by the two operands; wherein, a doubly decoupled parallel random number generator 100a (which can be denoted as X-SNG) is used to perform bit stream generation of the first operand, and another doubly decoupled parallel random number generator 100b (which can be denoted as W-SNG) is used to perform bit stream generation of the second operand.

[0021] The dual-decoupled parallel random number generator 100 utilizes a unique dual-decoupling architecture based on the "binary sampler" architecture. Based on this dual-decoupling mechanism, the random number generation core and parallel comparison core work together to generate high-quality, low-correlation random bit streams without introducing complex generation logic and significant hardware overhead. This low-correlation, low-cost feature is particularly suitable for SC systems requiring large-scale parallel computing. It significantly reduces computational errors caused by correlation, meeting the conflicting requirements of simple and low-cost hardware implementation and generating high-quality, low-correlation bit streams, thereby improving the accuracy and reliability of the entire system.

[0022] Specifically, in a complete random bit stream generation process, the core logical steps are as follows: Step 1: Generate heterogeneous random sources.

[0023] This step realizes the first level of decoupling, i.e., decoupling at the random source (RNG) level; the doubly decoupled parallel random number generator 110a processes the first operand, and the doubly decoupled parallel random number generator 110b processes the second operand. The doubly decoupled parallel random number generator 110a and the doubly decoupled parallel random number generator 110b are driven respectively to generate the first random number (denoted as r_t_x ) and the second random number (denoted as r_t_w To achieve the first level of decoupling, the doubly decoupled parallel random number generator 110 a and the doubly decoupled parallel random number generator 110 b are respectively configured to have different mathematical properties.

[0024] In one embodiment, in two parallel random number generators, the first parallel random number generator is used to generate a random bit stream corresponding to the first operand, and the second parallel random number generator is used to generate a random bit stream corresponding to the second operand: Optionally, the first primitive polynomial used by the doubly decoupled parallel random number generator 110a (i.e., the first parallel random number generator) is P1= x 7 + x 6 +1, and the second primitive polynomial used by the doubly decoupled parallel random number generator 110b (i.e., the second parallel random number generator) is P2= x 7 + x 3 +1, and configure different non-zero seeds (i.e., S1 and S2) during initialization, where the polynomial x A 7-bit unsigned integer representing the input.

[0025] It should be noted that the first primitive polynomial and the second primitive polynomial in this embodiment are only one of the preferred methods. Those skilled in the art can adopt other primitive polynomial combinations with different mathematical properties according to the corresponding usage requirements of the above primitive polynomials, as long as the decoupling of the random source can be achieved.

[0026] Step 2: Orthogonal threshold calculation.

[0027] This step implements the second level of decoupling, that is, the decoupling at the level of the deterministic comparison framework. This step is done in parallel for each bit in the 128-bit bit stream to be generated. i Calculate the randomization threshold: Furthermore, for the bit stream of the first operand (denoted as SN_X ) Generate: First, from the first deterministic sequence D_x Take out the i deterministic constant D_x [ i ], according to i deterministic constant D_x [ i ] calculate the first randomization threshold (denoted as Threshold_x_i = D_x [ i ] XOR r_t_x ).in, D_x is a forward linear sequence, that is D_x = [0, 1, 2,..., 127].

[0028] For the bit stream of the second operand (denoted as SN_W ) is generated by first generating the second deterministic sequence D_w Take out thei deterministic constant D_w [ i ], according to i deterministic constant [ i ] calculate the second randomization threshold (denoted as D_w = Threshold_w_i [ i ] XOR D_w ).in, r_t_w is a bit flip linear sequence, that is D_w = [0, 64, 32,96, ...], which is consistent with the first deterministic sequence D_w They are structurally orthogonal or lowly correlated with each other.

[0029] The mutually orthogonal or low-correlated deterministic constant sequences serve to break similarity in sequence structure. In this embodiment, a forward linear sequence and a bit-flipped linear sequence with a mathematically mirror-symmetric relationship can be used to achieve a high degree of structural orthogonality. Those skilled in the art will appreciate that other sequence combinations that can achieve similar effects, such as, but not limited to, a combination of a Gray code sequence and a linear sequence, also fall within the scope of protection of the present invention.

[0030] Step 3: Parallel comparison and bit stream output.

[0031] Parallel processing of each bit i Perform comparison operations separately: If the 7-bit unsigned binary value corresponding to the first operand D_x Greater than the first randomization threshold value_x , then the first operand's bit stream is i Bit Threshold_x_i [ i ] output is 1, otherwise the output is 0; if the second operand corresponds to a 7-bit unsigned binary value SN_X Greater than the second randomization threshold value_w , then the bit stream of the second operand is i Bit Threshold_w_i [ i ]The output is 1, otherwise the output is 0.

[0032] Through the three steps described above, including double decoupling, two random bit streams can be efficiently generated within a single cycle. Because the random sources and deterministic sequences used to generate these two random bit streams are significantly different, the structural correlation between the random bit streams is fundamentally broken, laying the foundation for high-precision random computation.

[0033] For a random variable that is uniformly distributed within a given range, when it is XORed with any constant, the result remains uniformly distributed within that range. Based on this core lemma, it can be mathematically proven that the expected number of bits with the value '1' in the random bit stream generated by the doubly decoupled parallel random number generator is strictly equal to the input binary value. This means that the generated random bit stream is statistically unbiased, ensuring the accuracy of the calculation.

[0034] The specific working principle of the above-mentioned doubly decoupled parallel random number generator 100 can be mathematically described as follows: Assume the input 7-bit unsigned integer is x , where 0≤ x ≤127. Let the generated 128-bit random bit stream be SN_W , among which, i The bits are denoted as SN According to the above steps 2 and 3, i bit by bit b_i =1 condition is: x >( D [ i ] XOR r )(1) in, r is a random integer uniformly distributed in the range [0,127], D [ i ] is the first i According to the expected linear property of probability theory, the generated 128-bit random bit stream b_i The total number of '1' N_ The expected value of 1 is: E [ N_ 1]= E [Σ ] =Σ E [ SN ] =Σ P [ b_i =1]( i Sum from 0 to 127) (2) The core principle is: for a random variable uniformly distributed in the range [0, 127] r , and any constant in this range D [ i ],Depend on y = D [ i ] XOR r The new random variable obtained by transformation yIt still maintains a uniform distribution in the range [0, 127]. A simple proof can be as follows: Because of the reversibility of the XOR operation, we know y and i The only way to determine r .now that r There are 128 equally probable values, then y There must also be 128 equally probable values, so y is also uniformly distributed. Therefore, P [ b_i =1] can be simplified to P ( x > y ).because y Take any integer in {0, 1, ..., 127} with equal probability, so that the inequality x > y Established, y Can only take {0, 1, ..., x -1}This x Therefore, its probability is: P ( x > y ) = x / 128 (3) Finally, substituting this probability (3) into the expected value formula (2), we can get: E [ N_ 1] = Σ( x / 128)=128×( x / 128) = x (4) This result proves that the proposed doubly decoupled parallel random number generator 100 can accurately map binary values ​​to expected values ​​of random bit streams, ensuring the unbiasedness of the calculation.

[0035] In some embodiments, the application example of the double decoupled parallel random number generator 100 is as follows: b_iAs shown, the DD-SNG is well-suited for resource-sharing deployment in a parallel computing system 200, such as a systolic array. Optionally, the system can instantiate an X-SNG 100a and a W-SNG 100b. The output (X11-SN) of the X-SNG 100a is fed into the first column of the parallel computing array 210 and pipelined with each clock cycle. Similarly, the output (W11-SN) of the W-SNG 100b is fed into the first row of the parallel computing array 210 and passed down the stack. PEs represent the computational units of the parallel computing array 210. This approach allows only two SNG modules to serve the entire large-scale parallel computing array, significantly conserving hardware resources while ensuring low computational dependencies and high computational accuracy.

[0036] In some embodiments, the correlation and performance analysis of the doubly decoupled parallel random number generator 100 is as follows: b_i As shown in Figure 3, this can be illustrated by comparing it with other existing SNG schemes (such as Independent, Shared, and Sobol) in terms of two key dimensions: correlation and hardware overhead.

[0037] Figure 3 (a) shows the bitstream correlation of different SNG schemes, with the vertical axis representing random cross-correlation and the horizontal axis representing the SNG scheme. Experimental data shows that the average correlation coefficient (SCC) of the traditional single LFSR shared scheme (Shared) is as high as 0.217. In contrast, the average SCC of the DD-SNG scheme proposed in this invention (i.e., Our DD-SNG) is effectively suppressed to 0.041, which is comparable to the scheme using the Sobol sequence (0.039) and the theoretically optimal independent random source scheme (0.031), demonstrating the effectiveness of our dual decoupling mechanism.

[0038] Figure 4 Figure 4 Figure 4 (b) shows the hardware cost and performance of different SNG schemes. The vertical axis represents the SNG scheme, and the horizontal axis represents resource cost and generation cycle (logarithmic scale). The caption "Flip–Flops (Cost)" represents flip-flops (cost), and the caption "Cycles (Performance)" represents cycles (performance). In terms of hardware cost, the core of our DD-SNG scheme requires only two LFSRs (approximately 14 flip-flops), which is comparable to the lowest-cost shared scheme (1 LFSR), and significantly lower than the independent random source scheme (256 LFSRs) and the logically complex Sobol scheme. In terms of performance, our DD-SNG is consistent with the independent random source and Sobol schemes, generating a complete bitstream in parallel within a single cycle, far exceeding the 128 cycles required by the shared scheme.

[0039] In summary, our DD-SNG solution achieves the same level of low correlation as state-of-the-art solutions while maintaining extremely low hardware resource costs and high generation performance. This effectively meets the conflicting demands of simple and low-overhead hardware implementation on the one hand, and high-quality, low-correlation bitstream generation on the other.

[0040] The doubly decoupled parallel random number generator 100 is designed to be doubly decoupled at both the random source level (for example, configuring pseudo-random number sequences with different mathematical properties for different bit streams) and the deterministic comparison framework level (for example, configuring mutually orthogonal deterministic constant sequences). This can fundamentally break the structural associations between different random bit streams without significantly increasing hardware resource overhead, thereby effectively improving the computational accuracy and reliability of the SC system.

[0041] In one embodiment, a random computing system is provided, comprising a parallel computing array and at least one doubly decoupled parallel random number generator. The doubly decoupled parallel random number generator is configured to provide a random bit stream to each computing unit in the parallel computing array in a resource-sharing manner, and the parallel computing array is used to perform random computing tasks based on the random bit stream. The doubly decoupled parallel random number generator includes a random number generation core and a parallel comparison core, and the parallel comparison core includes 128 parallel computing logics, each of which is composed of a cascaded XOR gate and a comparator.

[0042] The random number generation core is used to generate a 7-bit random number in each working cycle. The parallel comparison core is used to perform XOR operations on the random number with 128 deterministic constants in parallel within a single working cycle to obtain 128 randomization thresholds. The input 7-bit unsigned binary value is compared with each randomization threshold to generate a 128-bit random bit stream. If the 7-bit unsigned binary value is greater than the randomization threshold, the value of the corresponding bit in the generated random bit stream is 1, otherwise it is 0. A dual decoupling mechanism is used between the two parallel random number generators to generate heterogeneous random sources and calculate orthogonal thresholds; the dual decoupling mechanism includes decoupling at the random source level and decoupling at the deterministic comparison framework level.

[0043] It can be understood that the random computing system of this embodiment includes one or more of the above-mentioned doubly decoupled parallel random number generators 100, and a parallel computing array composed of a plurality of computing units. The doubly decoupled parallel random number generator 100 is configured to provide a low-correlated random bit stream to each computing unit in the parallel computing array in a resource-sharing manner to perform high-precision random computing tasks. The computing units PE of the parallel computing array can be understood by referring to the structure and function of the specific computing units of the existing parallel computing arrays in the art, and will not be further elaborated in this specification.

[0044] Specifically, the first level of decoupling of the doubly decoupled parallel random number generator 100 is implemented at the random source (Random Number Generator, RNG) level. The first level of decoupling is achieved by respectively configuring pseudo-random number sequences with different mathematical properties during the generation of random bit streams of the first operand and the second operand. Optionally, it can be achieved by adopting a linear feedback shift register LFSR with different primitive polynomials and / or different initial seeds.

[0045] The second decoupling of the doubly decoupled parallel random number generator 100 is implemented at the deterministic comparison framework level. The second decoupling is achieved by configuring mutually orthogonal or low-correlated deterministic constant sequences in the bit stream generation process of the first operand and the second operand. Optionally, it can be achieved by configuring a forward linear sequence for one bit stream generation process and a bit flip linear sequence for the other bit stream generation process.

[0046] This random computing system utilizes a unique dual-decoupled parallel random number generator designed using a "binary sampler" infrastructure. This dual-decoupling mechanism allows the random number generation core and parallel comparison core to work together to produce a high-quality, low-correlation random bit stream, without introducing complex generation logic and significant hardware overhead. This low-correlation, low-cost feature is particularly well-suited for SC systems requiring large-scale parallel computing. It significantly reduces computational errors caused by correlation, meeting the conflicting requirements of simple and low-overhead hardware implementation and the generation of high-quality, low-correlation bit streams, thereby improving the accuracy and reliability of the entire system.

[0047] In one embodiment, when two parallel random number generators are used, the first parallel random number generator generates a random bit stream corresponding to a first operand and the second parallel random number generator generates a random bit stream corresponding to a second operand: The first primitive polynomial used by the first parallel random number generator is: P1= x 7 + x 6 +1 The second primitive polynomial used by the second parallel random number generator is: P2= x 7 + x 3 +1 in, x A 7-bit unsigned integer representing the input. Two parallel random number generators are initialized with different non-zero seeds.

[0048] In one embodiment, in two parallel random number generators, the 128 deterministic constants used by the parallel comparison core of the first parallel random number generator are a forward linear sequence, and the 128 deterministic constants used by the parallel comparison core of the second parallel random number generator are a bit-flipped linear sequence.

[0049] It can be understood that the explanation of the various components of the above-mentioned random computing system can be understood by referring to the corresponding features of the above-mentioned doubly decoupled parallel random number generator 100, and will not be repeated in this embodiment.

[0050] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0051] The above embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, and all such variations and improvements fall within the scope of protection of the present invention.

[0052] Furthermore, the terms "one" and "plurality" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature specified as "one" or "plurality" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

Claims

1. A doubly decoupled parallel random number generator, characterized in that: It includes a random number generation core and a parallel comparison core. The parallel comparison core includes 128 parallel calculation logics, each of which is composed of cascaded XOR gates and comparators. The random number generation core is used to generate a 7-bit random number in each working cycle. The parallel comparison core is used to perform XOR operations on the random number with 128 deterministic constants in parallel within a single working cycle to obtain 128 randomization thresholds. The input 7-bit unsigned binary value is compared with each randomization threshold to generate a 128-bit random bit stream. Among them, if the 7-bit unsigned binary value is greater than the randomization threshold, the corresponding bit value in the generated random bit stream is 1, otherwise it is 0. A double decoupling mechanism is used between two parallel random number generators to generate heterogeneous random sources and calculate orthogonal thresholds; the double decoupling mechanism includes decoupling at the random source level and decoupling at the deterministic comparison framework level.

2. The doubly decoupled parallel random number generator according to claim 1, characterized in that When two parallel random number generators are used, the first parallel random number generator generates a random bit stream corresponding to the first operand, and the second parallel random number generator generates a random bit stream corresponding to the second operand: The first primitive polynomial used by the first parallel random number generator is: P1= x 7 + x 6 +1 The second primitive polynomial used by the second parallel random number generator is: P2= x 7 + x 3 +1 in, x A 7-bit unsigned integer representing the input. Two parallel random number generators are initialized with different non-zero seeds.

3. The doubly decoupled parallel random number generator according to claim 1 or 2, characterized in that: In the two parallel random number generators, the 128 deterministic constants used by the parallel comparison core of the first parallel random number generator are a forward linear sequence, and the 128 deterministic constants used by the parallel comparison core of the second parallel random number generator are a bit-flipped linear sequence.

4. A random computing system, characterized in that The system comprises a parallel computing array and at least one doubly decoupled parallel random number generator, wherein the doubly decoupled parallel random number generator is configured to provide a random bit stream to each computing unit in the parallel computing array in a resource-sharing manner, and the parallel computing array is used to perform random computing tasks according to the random bit stream. The doubly decoupled parallel random number generator includes a random number generation core and a parallel comparison core, and the parallel comparison core includes 128 parallel computing logics, each of which is composed of a cascaded XOR gate and a comparator. The random number generation core is used to generate a 7-bit random number in each working cycle. The parallel comparison core is used to perform XOR operations on the random number with 128 deterministic constants in parallel within a single working cycle to obtain 128 randomization thresholds. The input 7-bit unsigned binary value is compared with each randomization threshold to generate a 128-bit random bit stream. Among them, if the 7-bit unsigned binary value is greater than the randomization threshold, the corresponding bit value in the generated random bit stream is 1, otherwise it is 0. A double decoupling mechanism is used between two parallel random number generators to generate heterogeneous random sources and calculate orthogonal thresholds; the double decoupling mechanism includes decoupling at the random source level and decoupling at the deterministic comparison framework level.

5. The random calculation system according to claim 4, characterized in that When two parallel random number generators are used, the first parallel random number generator generates a random bit stream corresponding to the first operand, and the second parallel random number generator generates a random bit stream corresponding to the second operand: The first primitive polynomial used by the first parallel random number generator is: P1= x 7 + x 6 +1 The second primitive polynomial used by the second parallel random number generator is: P2= x 7 + x 3 +1 in, x A 7-bit unsigned integer representing the input. Two parallel random number generators are initialized with different non-zero seeds.

6. The random computing system according to claim 4 or 5, wherein in the two parallel random number generators, the 128 deterministic constants used by the parallel comparison core of the first parallel random number generator are a forward linear sequence, and the 128 deterministic constants used by the parallel comparison core of the second parallel random number generator are a bit-flipped linear sequence.

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