Memristive neural network circuit for simulating memory forgetting characteristics of different age stages

Abstract

The invention discloses a memristor neural network circuit for simulating memory forgetting characteristics of different age stages. Three input modules in the circuit convert different input signal ends into pulse electric signals respectively; the three input modules are respectively connected to the voltage selection module, and signals are selected from three paths of pulse voltages to drive the memristor; the output of the voltage selection module is connected to the memristor synapse module, and the signal transmission function of the biological synapse is simulated through the resistance change of the memristor; the output of the memristive synapse module is connected to the memristive learning module, adjusts the weight based on the synapse signal, and outputs a memory to form a signal output end. The bionic memristive synapse array is established, the dynamic change process of neural synapses of children, young and old age groups during memory formation is quantitatively represented, and a new thought is provided for application of the memristive device in neuroscience and brain-like research.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit design and relates to a memristor neural network circuit that simulates memory forgetting characteristics at different age stages. Background Art

[0002] With the continuous innovation of nanoelectronics technology, memristors, as emerging two-terminal nanoelectronic devices, have demonstrated remarkable application potential in a wide range of fields, including logic operations, secure communications, and biological behavior simulation, thanks to their unique electrical properties. Their significant advantages lie in their ability to dynamically change resistance in response to external stimuli and their non-volatile memory properties. This closely aligns with the signal transmission and plasticity regulation functions of biological synapses, making them ideal components for building neuromorphic circuits and simulating biological learning and memory mechanisms.

[0003] Currently, in the technical field of simulating memory and forgetting characteristics, most studies use general computing models to simulate the memory and forgetting patterns of different age groups. This software-level computing method not only consumes computing resources, but also makes it difficult to truly restore the physical process of dynamic memory changes in biological nervous systems. When existing hardware circuits simulate memory functions, they are usually constructed using traditional electronic components. These circuits cannot effectively reflect the significant differences in memory storage and forgetting rates among people of different age groups - during childhood, the brain is in a rapid development stage, memory is formed quickly but forgotten quickly; during youth, memory ability is stronger and forgetting is relatively slow; in old age, memory declines and forgetting accelerates. The neural network circuit proposed in this invention solves these problems. Summary of the Invention

[0004] To address the above issues, the present invention proposes a memristor neural network circuit that simulates the memory and forgetting characteristics of different age groups. Specifically, it involves a biomimetic circuit built with memristors that conforms to the memory and forgetting rules of organisms at different ages. The specific technical solution is as follows:

[0005] A memristor neural network circuit that simulates the memory forgetting characteristics of different age stages, including an input signal terminal V child 、V old 、V young , input module I, input module II, input module III, voltage selection module, memristor synapse module, memristor learning module and memory formation signal output terminal V OUT .

[0006] Input module I (the input signal terminal V child Convert to pulse electrical signal), input module II (the input signal terminal V old Convert to pulse electrical signal), input module III (the input signal terminal V youngThe three pulse voltages are converted into pulse electrical signals) and are connected to the voltage selection module (selecting a specific signal from the three pulse voltages to drive the memristor). The output of the voltage selection module is connected to the memristor synapse module (simulating the signal transmission function of the biological synapse by changing the resistance of the memristor). The output of the memristor synapse module is connected to the memristor learning module (adjusting the weight based on the synaptic signal and outputting the memory formation signal output terminal V OUT ).

[0007] In the input module I, the tenth memristor M 10 The positive end of M is connected to the output end of the first adder SUM1, 10 The negative end of the second resistor R2 is connected to one end of the second resistor R2 and the IN end of the first absolute value operator ABS1, the other end of the second resistor R2 is connected to ground, the OUT end of the first absolute value operator ABS1 is connected to the gate of the first NMOS transistor N1, the drain of the first NMOS transistor N1 is connected to the voltage V2, the source of the first NMOS transistor N1 is connected to port 1 of the first logic OR gate D1, the gate of the first PMOS transistor P1, the gate of the second NMOS transistor N2 and one end of the third resistor R3, the other end of the third resistor R3 is connected to ground, the drain of the second NMOS transistor N2 is connected to the negative voltage -V1, the source of N2 is connected to port 1 of the first adder SUM1 and one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to ground, port 2 of the first adder SUM1 is connected to the source of the first PMOS transistor P1 and one end of the first resistor R1, the other end of the first resistor R1 is connected to ground, and the drain of the first PMOS transistor P1 is connected to the input signal terminal V child .

[0008] In the input module II, the eleventh memristor M 11 The positive end of M is connected to the output end of the second adder SUM2. 11 The negative end of the sixth resistor R6 is connected to one end of the sixth resistor R6 and the IN end of the second absolute value operator ABS2, the other end of the sixth resistor R6 is connected to ground, the OUT end of the second absolute value operator ABS2 is connected to the gate of the third NMOS transistor N3, the drain of the third NMOS transistor N3 is connected to the voltage V4, the source of the third NMOS transistor N3 is connected to port 2 of the first logic OR gate D1, the gate of the second PMOS transistor P2, the gate of the fourth NMOS transistor N4 and one end of the seventh resistor R7, the other end of the seventh resistor R7 is connected to ground, the drain of the fourth NMOS transistor N4 is connected to the negative voltage -V3, the source of N4 is connected to port 1 of the second adder SUM2 and one end of the eighth resistor R8, the other end of the eighth resistor R8 is connected to ground, port 2 of the second adder SUM2 is connected to the source of the second PMOS transistor P2 and one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to ground, and the drain of the second PMOS transistor P2 is connected to the input signal terminal V old .

[0009] In the input module III, the twelfth memristor M 12 The positive end of the M is connected to the output end of the third adder SUM3, 12 The negative end of the tenth resistor R 10 and the IN terminal of the third absolute value operator ABS3, the tenth resistor R 10 The other end of the third absolute value operator ABS3 is connected to the ground, the OUT end of the third absolute value operator ABS3 is connected to the gate of the fifth NMOS transistor N5, the drain of the fifth NMOS transistor N5 is connected to the voltage V6, and the source of the fifth NMOS transistor N5 is connected to the port 3 of the first logic OR gate D1, the gate of the third PMOS transistor P3, the gate of the sixth NMOS transistor N6, and the eleventh resistor R 11 One end of the eleventh resistor R 11 The other end is connected to the ground, the drain of the sixth NMOS tube N6 is connected to the negative voltage -V5, and the source of N6 is connected to the No. 1 port of the third adder SUM3 and the twelfth resistor R 12 One end of the twelfth resistor R 12 The other end of the third adder SUM3 is connected to the ground, the port 2 of the third adder SUM3 is connected to the source of the third PMOS tube P3 and one end of the ninth resistor R9, the other end of the ninth resistor R9 is connected to the ground, and the drain of the third PMOS tube P3 is connected to the input signal terminal V young .

[0010] In the voltage selection module, port 1 of the fifth adder SUM5 is connected to the output end of the first voltage-controlled switch S1, port 1 of the sixth adder SUM6, port 1 of the seventh adder SUM7, and the twenty-third resistor R 23 One end of the twenty-third resistor R 23 The other end of the SUM5 is connected to the ground, the port 2 of the SUM5 is connected to the output of the first logic OR gate D1 and the input of the second logic NOT gate D2, and the port 2 of the sixth adder SUM6 is connected to the port 2 of the first logic OR gate D1 and the output of the input module II V U2 The port 2 of the seventh adder SUM7 is connected to the port 3 of the first logic OR gate D1 and the output terminal V of the input module III. U3 The two input terminals of the first voltage-controlled switch S1 are connected to the output terminal of the second logic NOT gate D2 and the ground respectively, and the control terminal of S1 is connected to the negative voltage -V 10 .

[0011] In the memristor synapse module, the positive end of the first memristor M1 is connected to the output end of the fifth adder SUM5, the positive end of the fourth memristor M4 and the positive end of the seventh memristor M7, and the negative end of M1 is connected to the negative end of the fourth memristor M4, the negative end of the seventh memristor M7, the inverting input end of the first operational amplifier OP1 and the thirteenth resistor R 13The positive input terminal of the first operational amplifier OP1 is connected to the ground, and the output terminal of OP1 is connected to the thirteenth resistor R 13 The other end and the sixteenth resistor R 16 The positive end of the second memristor M2 is connected to the output end of the sixth adder SUM6, the positive end of the fifth memristor M5 and the positive end of the eighth memristor M8, and the negative end of the second memristor M2 is connected to the negative end of the fifth memristor M5, the negative end of the eighth memristor M8, the fourteenth resistor R 14 and the reverse input terminal of the second operational amplifier OP2, the positive input terminal of the second operational amplifier OP2 is connected to the ground, and the output terminal of OP2 is connected to the fourteenth resistor R 14 The other end of the 24th resistor R 24 The positive end of the third memristor M3 is connected to the output end of the seventh adder SUM7, the positive end of the sixth memristor M6 and the positive end of the ninth memristor M9, and the negative end of the third memristor M3 is connected to the negative end of the sixth memristor M6, the negative end of the ninth memristor M9, the negative end of the fifteenth resistor R 15 and the inverting input terminal of the third operational amplifier OP3, the positive input terminal of the third operational amplifier OP3 is connected to the ground, and the output terminal of OP3 is connected to the fifteenth resistor R 15 The other end of the 25th resistor R 25 one end.

[0012] In the memristor learning module, the thirteenth memristor M 13 The positive end of the thirteenth memristor M is connected to the output end of the fourth adder SUM4. 13 The negative terminal of the 22nd resistor R 22 and the IN terminal of the fifth absolute value operator ABS5, the twenty-second resistor R 22 The other end of the first comparator COM1 is connected to the ground, the positive input end of the first comparator COM1 is connected to the OUT end of the fifth absolute value operator ABS5, and the negative input end of the first comparator COM1 is connected to the comparison voltage V th The output terminal of the first comparator COM1 is connected to the memory formation signal output terminal V OUT The port 1 of the fourth adder SUM4 is connected to the port 1 of the third logic OR gate D3, the source of the seventh NMOS transistor N7, the eighteenth resistor R 18 and the input end of the fourth logic NOT gate D4, and port 2 of SUM4 is connected to the output end of the second voltage-controlled switch S2 and the twenty-first resistor R 21 One end of the twenty-first resistor R 21The other end of the second voltage-controlled switch S2 is connected to the ground, the two input ends of the second voltage-controlled switch S2 are connected to the output end of the fifth logic AND gate D5 and the ground respectively, the control end of S2 is connected to the negative voltage -V8, and the port 1 of the fifth logic AND gate D5 is connected to the output end of the third logic OR gate D3, the port 2 of the third logic OR gate D3 and the nineteenth resistor R 19 One end of D5, port 2 is connected to the output end of the fourth logic NOT gate D4 and the twentieth resistor R 20 One end of the 20th resistor R 20 The other end of the nineteenth resistor R 19 The other end of the seventh NMOS transistor N7 is connected to the ground, the gate of the seventh NMOS transistor N7 is connected to the OUT end of the fourth absolute value operator ABS4, the drain of N7 is connected to the voltage V7, and the eighteenth resistor R 18 The other end of the fourth operational amplifier OP4 is connected to the ground, and the output end of the fourth operational amplifier OP4 is connected to the IN end of the fourth absolute value operator ABS4 and the seventeenth resistor R 17 The positive input of OP4 is connected to the ground, and the negative input of OP4 is connected to the seventeenth resistor R 17 The other end of the sixteenth resistor R 16 One end of the twenty-fourth resistor R 24 One end of the twenty-fifth resistor R 25 one end.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] Based on the resistive switching characteristics of memristors, this invention constructs a biomimetic memristive synaptic array by regulating key parameters such as the threshold voltage and ion mobility of the memristors. As a new type of resistor element, the resistance change of the memristor can simulate the plasticity of biological synapses. When simulating the childhood stage, by setting a lower threshold voltage and a higher sensitivity to conductivity changes, the memristive synaptic array exhibits the characteristics of rapid memory formation and a high forgetting rate. For the youth stage, the memristor parameters are optimized to balance memory speed and stability. When simulating the elderly stage, the physiological characteristics of memory decline and accelerated forgetting are reproduced by increasing the resistance fluctuation range of the memristor and reducing the speed of conductivity update. This parameter-controlled memristive synaptic array can quantitatively characterize the dynamic changes in neural synapses during memory formation in children, young people, and the elderly, providing new insights for the application of memristors in neuroscience and brain-inspired research. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for describing the examples of the present invention.

[0016] Figure 1 The resistance-voltage variation curves of the memristors with different parameters according to the present invention;

[0017] Figure 2 This is a circuit diagram of a memristive neural network circuit for simulating the memory forgetting characteristics of different age stages according to the present invention;

[0018] Figure 3 This is a simulation result diagram of the childhood memristive memory forgetting circuit of the present invention;

[0019] Figure 4 This is a diagram showing the simulation results of the memristive memory forgetting circuit in the elderly period of the present invention;

[0020] Figure 5 This is a simulation result diagram of the youth-stage memristive memory forgetting circuit of the present invention. DETAILED DESCRIPTION

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0022] A memristor neural network circuit that simulates the memory forgetting characteristics of different age stages, including an input signal terminal V child 、V old 、V young , input module I, input module II, input module III, voltage selection module, memristor synapse module, memristor learning module and memory formation signal output terminal V OUT .

[0023] Input module I (the input signal terminal V child Convert to pulse electrical signal), input module II (the input signal terminal V old Convert to pulse electrical signal), input module III (the input signal terminal V young The three pulse voltages are converted into pulse electrical signals) and are connected to the voltage selection module (selecting a specific signal from the three pulse voltages to drive the memristor). The output of the voltage selection module is connected to the memristor synapse module (simulating the signal transmission function of the biological synapse by changing the resistance of the memristor). The output of the memristor synapse module is connected to the memristor learning module (adjusting the weight based on the synaptic signal and outputting the memory formation signal output terminal V OUT ).

[0024] In the input module I, the tenth memristor M 10 The positive end of M is connected to the output end of the first adder SUM1, 10The negative end of the first absolute value operator ABS1 is connected to one end of the second resistor R2 and the IN end of the first absolute value operator ABS1, the OUT end of the first absolute value operator ABS1 is connected to the gate of the first NMOS transistor N1, the drain of the first NMOS transistor N1 is connected to the voltage V2, the source of the first NMOS transistor N1 is connected to port 1 of the first logic OR gate D1, the gate of the first PMOS transistor P1, the gate of the second NMOS transistor N2 and one end of the third resistor R3, the drain of the second NMOS transistor N2 is connected to the negative voltage -V1, the source of N2 is connected to port 1 of the first adder SUM1 and one end of the fourth resistor R4, port 2 of the first adder SUM1 is connected to the source of the first PMOS transistor P1 and one end of the first resistor R1, and the drain of the first PMOS transistor P1 is connected to the input signal terminal V child The other end of the second resistor R2, the other end of the third resistor R3, the other end of the fourth resistor R4, and the other end of the first resistor R1 are all grounded.

[0025] In the input module II, the eleventh memristor M 11 The positive end of M is connected to the output end of the second adder SUM2. 11 The negative end of the sixth resistor R6 is connected to the IN end of the second absolute value operator ABS2, the OUT end of the second absolute value operator ABS2 is connected to the gate of the third NMOS transistor N3, the drain of the third NMOS transistor N3 is connected to the voltage V4, the source of the third NMOS transistor N3 is connected to port 2 of the first logic OR gate D1, the gate of the second PMOS transistor P2, the gate of the fourth NMOS transistor N4 and one end of the seventh resistor R7, the drain of the fourth NMOS transistor N4 is connected to the negative voltage -V3, the source of N4 is connected to port 1 of the second adder SUM2 and one end of the eighth resistor R8, port 2 of the second adder SUM2 is connected to the source of the second PMOS transistor P2 and one end of the fifth resistor R5, and the drain of the second PMOS transistor P2 is connected to the input signal terminal V old The other end of the sixth resistor R6, the other end of the seventh resistor R7, the other end of the eighth resistor R8, and the other end of the fifth resistor R5 are all grounded.

[0026] In the input module III, the twelfth memristor M 12 The positive end of the M is connected to the output end of the third adder SUM3, 12 The negative end of the tenth resistor R 10 The OUT terminal of the third absolute value operator ABS3 is connected to the gate of the fifth NMOS transistor N5, the drain of the fifth NMOS transistor N5 is connected to the voltage V6, and the source of the fifth NMOS transistor N5 is connected to the port 3 of the first logic OR gate D1, the gate of the third PMOS transistor P3, the gate of the sixth NMOS transistor N6, and the eleventh resistor R 11The drain of the sixth NMOS tube N6 is connected to the negative voltage -V5, and the source of N6 is connected to the No. 1 port of the third adder SUM3 and the twelfth resistor R 12 The first end of the third adder SUM3 is connected to the source of the third PMOS tube P3 and one end of the ninth resistor R9, and the drain of the third PMOS tube P3 is connected to the input signal terminal V young The tenth resistor R 10 The other end of the eleventh resistor R 11 The other end of the twelfth resistor R 12 The other end of the ninth resistor R9 and the other end of the ninth resistor R9 are grounded.

[0027] In the voltage selection module, port 1 of the fifth adder SUM5 is connected to the output end of the first voltage-controlled switch S1, port 1 of the sixth adder SUM6, port 1 of the seventh adder SUM7, and the twenty-third resistor R 23 One end of the twenty-third resistor R 23 The other end of the SUM5 is connected to the ground, the port 2 of the SUM5 is connected to the output of the first logic OR gate D1 and the input of the second logic NOT gate D2, and the port 2 of the sixth adder SUM6 is connected to the port 2 of the first logic OR gate D1 and the output of the input module II V U2 The port 2 of the seventh adder SUM7 is connected to the port 3 of the first logic OR gate D1 and the output terminal V of the input module III. U3 The two input terminals of the first voltage-controlled switch S1 are connected to the output terminal of the second logic NOT gate D2 and the ground respectively, and the control terminal of S1 is connected to the negative voltage -V 10 .

[0028] In the memristor synapse module, the positive end of the first memristor M1 is connected to the output end of the fifth adder SUM5, the positive end of the fourth memristor M4 and the positive end of the seventh memristor M7, and the negative end of M1 is connected to the negative end of the fourth memristor M4, the negative end of the seventh memristor M7, the inverting input end of the first operational amplifier OP1 and the thirteenth resistor R 13 The positive input terminal of the first operational amplifier OP1 is connected to the ground, and the output terminal of OP1 is connected to the thirteenth resistor R 13 The other end and the sixteenth resistor R 16 The positive end of the second memristor M2 is connected to the output end of the sixth adder SUM6, the positive end of the fifth memristor M5 and the positive end of the eighth memristor M8, and the negative end of the second memristor M2 is connected to the negative end of the fifth memristor M5, the negative end of the eighth memristor M8, the fourteenth resistor R 14 and the inverting input terminal of the second operational amplifier OP2, and the output terminal of OP2 is connected to the fourteenth resistor R 14 The other end of the 24th resistor R 24The positive end of the third memristor M3 is connected to the output end of the seventh adder SUM7, the positive end of the sixth memristor M6 and the positive end of the ninth memristor M9, and the negative end of the third memristor M3 is connected to the negative end of the sixth memristor M6, the negative end of the ninth memristor M9, the negative end of the fifteenth resistor R 15 and the inverting input terminal of the third operational amplifier OP3, the output terminal of OP3 is connected to the fifteenth resistor R 15 The other end of the 25th resistor R 25 The positive input terminal of the second operational amplifier OP2 and the positive input terminal of the third operational amplifier OP3 are both grounded.

[0029] In the memristor learning module, the thirteenth memristor M 13 The positive end of the thirteenth memristor M is connected to the output end of the fourth adder SUM4. 13 The negative terminal of the 22nd resistor R 22 and the IN terminal of the fifth absolute value operator ABS5, the positive input terminal of the first comparator COM1 is connected to the OUT terminal of the fifth absolute value operator ABS5, and the negative input terminal of the first comparator COM1 is connected to the comparison voltage V th The output terminal of the first comparator COM1 is connected to the memory formation signal output terminal V OUT The port 1 of the fourth adder SUM4 is connected to the port 1 of the third logic OR gate D3, the source of the seventh NMOS transistor N7, the eighteenth resistor R 18 and the input end of the fourth logic NOT gate D4, and port 2 of SUM4 is connected to the output end of the second voltage-controlled switch S2 and the twenty-first resistor R 21 The two input terminals of the second voltage-controlled switch S2 are connected to the output terminal of the fifth logic AND gate D5 and the ground respectively, the control terminal of S2 is connected to the negative voltage -V8, and the port 1 of the fifth logic AND gate D5 is connected to the output terminal of the third logic OR gate D3, the port 2 of the third logic OR gate D3 and the nineteenth resistor R 19 One end of D5, port 2 is connected to the output end of the fourth logic NOT gate D4 and the twentieth resistor R 20 The gate of the seventh NMOS transistor N7 is connected to the OUT terminal of the fourth absolute value operator ABS4, the drain of N7 is connected to the voltage V7, the output terminal of the fourth operational amplifier OP4 is connected to the IN terminal of the fourth absolute value operator ABS4 and the seventeenth resistor R 17 One end of OP4 is connected to the seventeenth resistor R 17 The other end of the sixteenth resistor R 16 One end of the twenty-fourth resistor R 24 One end of the twenty-fifth resistor R 25 The 22nd resistor R 22The other end of the twenty-first resistor R 21 The other end of the 20th resistor R 20 The other end of the nineteenth resistor R 19 The other end of the eighteenth resistor R 18 The other end of OP4 and the positive input end of OP4 are grounded.

[0030] Figure 1 The selected memristor has different parameters when the same voltage V S The resistance change curve below shows a memristor, a two-terminal device whose resistance is affected by the voltage applied across its two ends. Memristors with three different parameters are used to build neural synapses at different age stages.

[0031] Figure 2 A memristor neural network circuit is built with the selected memristor as the core to simulate the memory forgetting characteristics of different age stages. The initial value of the memristor is set to R OFF , the circuit includes an input signal terminal V child , V old , V young , input module I, input module II, input module III, voltage selection module, memristor synapse module, memristor learning module, memory formation signal output terminal V OUT . Represents the childhood memory signal input terminal V child Connected to input module I, representing the memory signal input terminal V during old age old Connected to input module II, representing the youth memory signal input terminal V young Connected to input module III, input module I, input module II, and input module III are all connected to the voltage selection module, the voltage selection module is connected to the memristor synapse module, the memristor synapse module is connected to the memristor learning module, and the output end of the memristor learning module is the memory formation signal output end V OUT . Figure 3 、 Figure 4 、 Figure 5 V child 、V old 、V young Different memristive memory forgetting simulation results obtained by inputting at three different age periods.

[0032] Input modules I, II, and III convert external stimulation signals into pulse electrical signals that can be received by the human brain. The voltage selection module is used to control and adjust the memory voltage and forgetting voltage. The memristor synapse module is used to select memristor synapses with different parameters when remembering at different ages, so as to achieve different synaptic connection strengths at different ages. The memristor learning module is used to realize memory formation and output memory formation signals.

[0033] In the input module I, when the input terminal V child When the voltage is high, the first PMOS tube P1 is turned on, and V child is transmitted to port 2 of the first adder SUM1. At this time, the output voltage V SUM1 =V child , so that the tenth memristor M 10 The resistance value R M10 The output value of the first absolute value operator ABS1 is V ABS1 =|(R2 / R M10 )*V SUM1 |, the first NMOS tube N1 is turned on by the memristor M 10 Determine that when the tenth memristor M 10 When the resistance drops to a certain value, V ABS1 is greater than the threshold voltage of the first NMOS tube N1, N1 is turned on, and the output V U1 is high, since V U1 is greater than the threshold voltage of the second NMOS tube N2, N2 is turned on, and the negative voltage -V1 is transmitted to port 1 of the first adder SUM1. At this time, the output V SUM1 =V child -V1, the tenth memristor M 10 The resistance of the tenth memristor M 10 The resistance value R M10 When it rises to a certain value, V ABS1 is less than the threshold voltage of the first NMOS tube N1, N1 is turned off, V U1 The output is low level, and the second NMOS transistor N2 is turned off, and the above process is repeated. The frequency and duty cycle of the output pulse of the input module I can be determined by the tenth memristor M 10 The working process of input module II and input module III is similar to that of input module I.

[0034] The voltage selection module includes a first logic AND gate D1, a second logic NOT gate D2, a first voltage-controlled switch S1, a twenty-third resistor R 23 , the fifth adder SUM5, the sixth adder SUM6, the seventh adder SUM7, the negative voltage -V 10 The first logic AND gate D1 receives the output V of the input module I. U1 , port 2 of D1 receives the output V of input module II U2 , port 3 of D1 receives the output V of input module III U3 , when V U1 、V U2 、V U3When both inputs are low, D1 outputs a low level, the second logic NOT gate D2 outputs a high level, the first voltage-controlled switch S1 is turned on, and the negative voltage -V 10 The voltage is transmitted to the input terminal 1 of the fifth adder SUM5, the input terminal 1 of the sixth adder SUM6, and the input terminal 1 of the seventh adder SUM7. SUM5, SUM6, and SUM7 output a negative voltage V SUM5 =V SUM6 =V SUM7 =-V 10 When childhood memories begin, the output V of input module I U1 is high, the output V of input module II U2 is low level, the output V of input module III U3 is low, D1 outputs high, D2 outputs low, S1 is off, and SUM5 outputs high. Similarly, when the old age begins to remember, the output voltage V U2 is high, the outputs of the other two input modules are low, and SUM6 outputs high; when the youth begins to memorize, the output voltage V U3 is high level, the outputs of the other two input modules are low level, and SUM7 outputs high level.

[0035] In the memristive synaptic module, when there is no age period memory, the output V of input modules I, II, and III U1 、V U2 、V U3 All are low level, the fifth adder SUM5, the sixth adder SUM6, and the seventh adder SUM7 output negative voltage VSUM5 = VSUM6 = VSUM7 = -V 10 , the positive terminal voltage of memristors M1, M2, M3, M4, M5, M6, M7, M8, and M9 is negative, so the resistance of memristor M1 is R M1 、M2 resistance R M2 、M3 resistance R M3 、M4 resistance R M4 、M5 resistance R M5 、M6 resistance R M6 、M7 resistance R M7 、M8 resistance R M8 、M9 resistance R M9 All remain unchanged, the output voltage of the first operational amplifier OP1 is V OP1 =-(R 13 / R M1 +R 13 / R M4 +R 13 / R M7 )*V SUM5, the output voltage of the second operational amplifier OP2 is V OP2 =-(R 14 / R M2 +R 14 / R M5 +R 14 / R M8 )*V SUM6 , the output voltage of the third operational amplifier OP3 is V OP3 =-(R 15 / R M3 +R 15 / R M6 +R 15 / R M9 )*V SUM7 When childhood memories begin, V U1 is high level, V U2 、V U3 The input is low, D1 outputs high, D2 outputs low, S1 is turned off, SUM5 outputs high, SUM6 and SUM7 output low, and the resistance of memristors M1, M4, and M7 begins to decrease. OP1 Continuously decreasing, V OP2 =V OP3 = 0. Similarly, when memory begins in old age, the output voltage V U2 is high, the resistance of memristors M2, M5, and M8 begins to decrease, and V OP2 Continuously decreasing, V OP1 =V OP3 =0; when the memory starts in youth, the output voltage V of input module III U3 is high, the resistance of memristors M3, M6, and M9 begins to decrease, and V OP3 Continuously decreasing, V OP1 =V OP2 =0.

[0036] In the memristor learning module, the output V from the memristor synaptic module is received. OP1 、V OP2 、V OP3 , V OP1 To the sixteenth resistor R 16 One end, R 16 The other end is connected to the inverting input terminal of the fourth operational amplifier OP4, the seventeenth resistor R 17 One end of the twenty-fourth resistor R 24 One end of the twenty-fifth resistor R 25 One end, V OP2 To the twenty-fourth resistor R 24 One end, V OP3 To the twenty-fifth resistor R 25One end of the seventeenth resistor R 17 The other end is connected to the output end of the fourth operational amplifier OP4 and the IN port of the fourth absolute value operator ABS4. The output of the fourth operational amplifier OP4 is V OP4 =-(V OP1 *R 17 / R 16 +V OP2 *R 17 / R 24 +V OP3 *R 17 / R 25 ), the output after the fourth absolute value operator ABS4 is V ABS4 =|V OP4 |, the OUT port of the fourth absolute value operator ABS4 is connected to the gate of the seventh NMOS tube N7, when V ABS4 When the voltage V7 is greater than the threshold voltage of N7, N7 is turned on, and the voltage V7 is transmitted to the port 1 of the third logic OR gate D3, the input end of the fourth logic NOT gate D4 and the port 1 of the fourth adder SUM4. The output port of SUM4 is connected to the thirteenth memristor M 13 The positive end, M 13 The negative terminal of the 22nd resistor R 22 and the IN terminal of the fifth absolute value operator ABS5, the OUT terminal of the fifth absolute value operator ABS5 is connected to the positive input terminal of the first comparator COM1, and the negative input terminal of COM1 is connected to the comparison voltage V th , the thirteenth memristor M 13 The resistance is R M13 , M 13 The negative terminal voltage Va=(R 22 / R M13 )*V SUM4 , after the operation of the fifth absolute value operator ABS5, V ABS5 =|V a |, when |V a | is greater than the comparison voltage V at the inverting input terminal of the first comparator COM1 th , output signal V OUT Output high level, indicating memory formation; when |V a | is less than the comparison voltage V at the inverting input terminal of the first comparator COM1 th , output signal V OUT Outputting low level indicates that no memory is formed or forgotten.

[0037] Figure 3 This is the simulation result of the childhood memory forgetting process, where the input module I works and the input signal V child High level, input module II and input module III do not work, RM13 Represents the weight of the memristor memory module, V OUT Indicates the result of memory and forgetting. Figure 3 It can be seen that in the 0-50ms memory process, V child =High level, in the first 14ms, the resistance of the memristors M1, M4, and M7 in the memristor synapse module begins to decrease, and the output voltage of the fourth absolute value operator ABS4 begins to increase until V ABS4 The voltage V7 is greater than the threshold voltage of the seventh NMOS tube N7, and is transmitted to the port 1 of the fourth adder SUM4. At this time, the thirteenth memristor M 13 The positive terminal is a positive voltage, R M13 Starts to drop, and the voltage |V a | starts to rise until |V a | is greater than the comparison voltage V at the inverting input terminal of the first comparator COM1 th , output terminal V OUT Output high level at 37ms, indicating memory formation. 50-100ms is the forgetting process, V child Low level, negative voltage -V 10 is transmitted to the positive terminal of the memristor in the memristor synapse module, so the resistance of the memristor in the memristor synapse module begins to rise, and the output voltage of the fourth absolute value operator ABS4 begins to decrease until V ABS4 The negative voltage -V8 is smaller than the threshold voltage of the seventh NMOS tube N7, and is transmitted to the port 2 of the fourth adder SUM4. At this time, the thirteenth memristor M 13 The positive terminal is negative voltage, R M13 Starts to rise, and at the same time the voltage |V a | starts to decrease until |V a | is less than the comparison voltage V at the inverting input terminal of the first comparator COM1 th , output terminal V OUT The output is low at 56ms, indicating that forgetting has occurred. The simulation results show that the synaptic weights of children increase rapidly when stimulated by the memory signal, and decrease rapidly when the memory signal disappears.

[0038] Figure 4 This is the simulation result of the memory forgetting process in old age, where the input module II works and the input signal V old When it is high level, input module I and input module III do not work. During the 0-50ms memory process, V old The resistance of the memristors M2, M5, and M8 in the memristor synapse module decreases in the first 16ms until the output signal V OUT Output high level, indicating memory formation, 50-100ms, at 75ms the output terminal signal V OUTThe output is low, indicating that forgetting has occurred. The simulation results show that the weight of the synapses in the elderly rises slowly when stimulated by the memory signal, and decreases quickly when the memory signal disappears.

[0039] Figure 5 This is the simulation result of the memory forgetting process in youth, where the input module III is working and the input signal V young When it is high level, input module I and input module II do not work. During the 0-50ms memory process, V young The resistance of the memristors M3, M6, and M9 in the memristor synapse module decreases in the first 12ms until the output signal V OUT Output high level, indicating memory formation, 50-100ms, at 88ms the output terminal signal V OUT The output is low, indicating that forgetting has occurred. The simulation results show that the weight of the synapses in the youth period increases slowly when stimulated by the memory signal, and decreases quickly when the memory signal disappears.

[0040] from Figure 3 、 Figure 4 、 Figure 5 The simulation results show that the circuit simulates the memory and forgetting processes of people of different ages, as well as the differences in memory and forgetting time. Youth has the shortest memory time and the longest forgetting time, followed by old age. Children have the longest memory time and the shortest forgetting time, which is consistent with the memory patterns of the human brain.

[0041] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It is apparent to those skilled in the art that various changes, modifications, substitutions, and variations to these embodiments may be made without departing from the principles and spirit of the present invention, and these changes and modifications still fall within the scope of protection of the present invention.

Claims

1. A memristive neural network circuit that simulates the memory forgetting characteristics of different age stages, characterized by: Including input signal terminal V child 、V old 、V young , input module I, input module II, input module III, voltage selection module, memristor synapse module, memristor learning module and memory formation signal output terminal V OUT ; Input module I inputs signal terminal V child Converts the signal into a pulse signal, and the input module II inputs the signal to the V old Converts the signal into a pulse signal, and the input module III inputs the signal to the V young Converted into pulse electrical signal; Input module I, input module II, and input module III are connected to the voltage selection module respectively, which selects the signal from the three pulse voltages to drive the memristor; the output of the voltage selection module is connected to the memristor synapse module, which simulates the signal transmission function of the biological synapse through the change of the memristor resistance; the output of the memristor synapse module is connected to the memristor learning module, which adjusts the weight based on the synaptic signal and outputs the memory formation signal output terminal V OUT .

2. The memristive neural network circuit for simulating the memory forgetting characteristics of different age stages according to claim 1, characterized in that: In the input module I, the tenth memristor M 10 The positive end of M is connected to the output end of the first adder SUM1, 10 The negative end of the second resistor R2 is connected to one end of the second resistor R2 and the IN end of the first absolute value operator ABS1, the other end of the second resistor R2 is connected to ground, the OUT end of the first absolute value operator ABS1 is connected to the gate of the first NMOS transistor N1, the drain of the first NMOS transistor N1 is connected to the voltage V2, the source of the first NMOS transistor N1 is connected to port 1 of the first logic OR gate D1, the gate of the first PMOS transistor P1, the gate of the second NMOS transistor N2 and one end of the third resistor R3, the other end of the third resistor R3 is connected to ground, the drain of the second NMOS transistor N2 is connected to the negative voltage -V1, the source of N2 is connected to port 1 of the first adder SUM1 and one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to ground, port 2 of the first adder SUM1 is connected to the source of the first PMOS transistor P1 and one end of the first resistor R1, the other end of the first resistor R1 is connected to ground, and the drain of the first PMOS transistor P1 is connected to the input signal terminal V child .

3. The memristive neural network circuit for simulating the memory forgetting characteristics of different age stages according to claim 2, characterized in that: In the input module II, the eleventh memristor M 11 The positive end of M is connected to the output end of the second adder SUM2. 11 The negative end of the sixth resistor R6 is connected to one end of the sixth resistor R6 and the IN end of the second absolute value operator ABS2, the other end of the sixth resistor R6 is connected to ground, the OUT end of the second absolute value operator ABS2 is connected to the gate of the third NMOS transistor N3, the drain of the third NMOS transistor N3 is connected to the voltage V4, the source of the third NMOS transistor N3 is connected to port 2 of the first logic OR gate D1, the gate of the second PMOS transistor P2, the gate of the fourth NMOS transistor N4 and one end of the seventh resistor R7, the other end of the seventh resistor R7 is connected to ground, the drain of the fourth NMOS transistor N4 is connected to the negative voltage -V3, the source of N4 is connected to port 1 of the second adder SUM2 and one end of the eighth resistor R8, the other end of the eighth resistor R8 is connected to ground, port 2 of the second adder SUM2 is connected to the source of the second PMOS transistor P2 and one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to ground, and the drain of the second PMOS transistor P2 is connected to the input signal terminal V old .

4. The memristive neural network circuit for simulating the memory forgetting characteristics of different age stages according to claim 3, characterized in that: In the input module III, the twelfth memristor M 12 The positive end of the M is connected to the output end of the third adder SUM3, 12 The negative end of the tenth resistor R 10 and the IN terminal of the third absolute value operator ABS3, the tenth resistor R 10 The other end of the third absolute value operator ABS3 is connected to the ground, the OUT end of the third absolute value operator ABS3 is connected to the gate of the fifth NMOS transistor N5, the drain of the fifth NMOS transistor N5 is connected to the voltage V6, and the source of the fifth NMOS transistor N5 is connected to the port 3 of the first logic OR gate D1, the gate of the third PMOS transistor P3, the gate of the sixth NMOS transistor N6, and the eleventh resistor R 11 One end of the eleventh resistor R 11 The other end is connected to the ground, the drain of the sixth NMOS tube N6 is connected to the negative voltage -V5, and the source of N6 is connected to the No. 1 port of the third adder SUM3 and the twelfth resistor R 12 One end of the twelfth resistor R 12 The other end of the third adder SUM3 is connected to the ground, the port 2 of the third adder SUM3 is connected to the source of the third PMOS tube P3 and one end of the ninth resistor R9, the other end of the ninth resistor R9 is connected to the ground, and the drain of the third PMOS tube P3 is connected to the input signal terminal V young .

5. The memristive neural network circuit for simulating the memory forgetting characteristics of different age stages according to claim 4, characterized in that: In the voltage selection module, port 1 of the fifth adder SUM5 is connected to the output end of the first voltage-controlled switch S1, port 1 of the sixth adder SUM6, port 1 of the seventh adder SUM7, and the twenty-third resistor R 23 One end of the twenty-third resistor R 23 The other end of the SUM5 is connected to the ground, the port 2 of the SUM5 is connected to the output of the first logic OR gate D1 and the input of the second logic NOT gate D2, and the port 2 of the sixth adder SUM6 is connected to the port 2 of the first logic OR gate D1 and the output of the input module II V U2 The port 2 of the seventh adder SUM7 is connected to the port 3 of the first logic OR gate D1 and the output terminal V of the input module III. U3 The two input terminals of the first voltage-controlled switch S1 are connected to the output terminal of the second logic NOT gate D2 and the ground respectively, and the control terminal of S1 is connected to the negative voltage -V 10 .

6. The memristive neural network circuit for simulating the memory forgetting characteristics of different age stages according to claim 5, characterized in that: In the memristor synapse module, the positive end of the first memristor M1 is connected to the output end of the fifth adder SUM5, the positive end of the fourth memristor M4 and the positive end of the seventh memristor M7, and the negative end of M1 is connected to the negative end of the fourth memristor M4, the negative end of the seventh memristor M7, the inverting input end of the first operational amplifier OP1 and the thirteenth resistor R 13 The positive input terminal of the first operational amplifier OP1 is connected to the ground, and the output terminal of OP1 is connected to the thirteenth resistor R 13 The other end and the sixteenth resistor R 16 The positive end of the second memristor M2 is connected to the output end of the sixth adder SUM6, the positive end of the fifth memristor M5 and the positive end of the eighth memristor M8, and the negative end of the second memristor M2 is connected to the negative end of the fifth memristor M5, the negative end of the eighth memristor M8, the fourteenth resistor R 14 and the reverse input terminal of the second operational amplifier OP2, the positive input terminal of the second operational amplifier OP2 is connected to the ground, and the output terminal of OP2 is connected to the fourteenth resistor R 14 The other end of the 24th resistor R 24 The positive end of the third memristor M3 is connected to the output end of the seventh adder SUM7, the positive end of the sixth memristor M6 and the positive end of the ninth memristor M9, and the negative end of the third memristor M3 is connected to the negative end of the sixth memristor M6, the negative end of the ninth memristor M9, the negative end of the fifteenth resistor R 15 and the inverting input terminal of the third operational amplifier OP3, the positive input terminal of the third operational amplifier OP3 is connected to the ground, and the output terminal of OP3 is connected to the fifteenth resistor R 15 The other end of the 25th resistor R 25 one end.

7. The memristive neural network circuit for simulating the memory forgetting characteristics of different age stages according to claim 6, characterized in that: In the memristor learning module, the thirteenth memristor M 13 The positive end of the thirteenth memristor M is connected to the output end of the fourth adder SUM4. 13 The negative terminal of the 22nd resistor R 22 and the IN terminal of the fifth absolute value operator ABS5, the twenty-second resistor R 22 The other end of the first comparator COM1 is connected to the ground, the positive input end of the first comparator COM1 is connected to the OUT end of the fifth absolute value operator ABS5, and the negative input end of the first comparator COM1 is connected to the comparison voltage V th The output terminal of the first comparator COM1 is connected to the memory formation signal output terminal V OUT The port 1 of the fourth adder SUM4 is connected to the port 1 of the third logic OR gate D3, the source of the seventh NMOS transistor N7, the eighteenth resistor R 18 and the input end of the fourth logic NOT gate D4, and port 2 of SUM4 is connected to the output end of the second voltage-controlled switch S2 and the twenty-first resistor R 21 One end of the twenty-first resistor R 21 The other end of the second voltage-controlled switch S2 is connected to the ground, the two input ends of the second voltage-controlled switch S2 are connected to the output end of the fifth logic AND gate D5 and the ground respectively, the control end of S2 is connected to the negative voltage -V8, and the port 1 of the fifth logic AND gate D5 is connected to the output end of the third logic OR gate D3, the port 2 of the third logic OR gate D3 and the nineteenth resistor R 19 One end of D5, port 2 is connected to the output end of the fourth logic NOT gate D4 and the twentieth resistor R 20 One end of the 20th resistor R 20 The other end of the nineteenth resistor R 19 The other end of the seventh NMOS transistor N7 is connected to the ground, the gate of the seventh NMOS transistor N7 is connected to the OUT end of the fourth absolute value operator ABS4, the drain of N7 is connected to the voltage V7, and the eighteenth resistor R 18 The other end of the fourth operational amplifier OP4 is connected to the ground, and the output end of the fourth operational amplifier OP4 is connected to the IN end of the fourth absolute value operator ABS4 and the seventeenth resistor R 17 The positive input of OP4 is connected to the ground, and the negative input of OP4 is connected to the seventeenth resistor R 17 The other end of the sixteenth resistor R 16 One end of the twenty-fourth resistor R 24 One end of the twenty-fifth resistor R 25 one end.

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