Transverse varied doped P well region MOS (Metal Oxide Semiconductor) grid-control thyristor and manufacturing method thereof

Abstract

The invention relates to a semiconductor technology, in particular to a lateral varied doping P well region MOS (Metal Oxide Semiconductor) grid control thyristor and a manufacturing method thereof. On the basis of a traditional P well region MOS grid control thyristor structure, a P well region is changed to be formed by injecting P-type impurities into a plurality of windows at the same time and pushing junctions, and therefore the P well region variably doped in the transverse direction is formed. According to the structure, the transverse resistance of the P well region of the device is increased, the highest potential difference between the P well region and the N well region is increased during conduction, the conversion of the device from an IGBT conduction mode to a thyristor conduction mode is accelerated, and the conduction performance of the device is optimized only by regulating and controlling the size of a doping window while the complexity of the original process is kept unchanged.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, in particular to a lateral variable doping P well region MOS gate controlled thyristor and a manufacturing method thereof. Background Art

[0002] Power semiconductor devices, as switching devices, can be used in power electronics and pulse power applications. The MOS-controlled thyristor (MCT) is a composite power semiconductor device that combines MOS gate control technology with the characteristics of a thyristor. While traditional thyristors offer the advantages of high voltage, high current, and low on-state voltage drop, they suffer from difficulty in quickly shutting down. MCTs integrate a MOS gate element within a PNPN thyristor structure and utilize MOS gate voltage signals to control the device's on and off state. This approach retains the high withstand voltage and low conduction loss characteristics of thyristors while achieving fast switching capabilities similar to MOSFETs. The core of this approach lies in the creation of controllable carrier injection and extraction paths within the thyristor through the MOS structure, thus resolving the complex commutation circuitry required for traditional thyristors to switch off. MCTs are suitable for applications requiring high withstand voltage and low conduction losses, such as high-voltage direct current transmission and industrial motor drives, and are currently a key area of ​​exploration in the development of power semiconductor technology.

[0003] Cathode shorting technology is widely used in power semiconductor devices such as thyristors and insulated-gate bipolar transistors. This technology introduces a low-resistance short-circuit point in the device's cathode region, providing an additional hole extraction path when the device is on, thereby improving the device's turn-off characteristics and dynamic performance. While maintaining the device's forward conduction characteristics, it effectively reduces turn-off time and switching losses, making it particularly advantageous in high-frequency switching applications.

[0004] Variable doping technology achieves varying doping effects by varying the doping window. By controlling the size and position of the impurity window, while maintaining other doping conditions unchanged, this technique can construct interconnected regions with varying junction depths and doping concentrations in a single doping step. This technique can reduce the number of process steps required for complex structures of the same type. Summary of the Invention

[0005] The object of the present invention is to provide a structure of a cathode P region laterally variable doping MCT device and its implementation process, wherein the structure can improve the snapback effect during forward conduction.

[0006] The technical solution of the present invention is:

[0007] A lateral variable doping P-well region MOS gate-controlled thyristor, comprising an anode metal 9, a P+ region 8, an FS layer 7, and an N-drift region 6 stacked in sequence from bottom to top, a P-well region 5 at one end of the upper layer of the N-drift region 6, an N-well region 4 at the upper layer of the P-well region 5, the lateral width of the N-well region 4 being smaller than the lateral width of the P-well region 5, and a gap between the two ends of the upper surface of the N-well region 4 and the two ends of the upper surface of the P-well region 5; a gate oxide layer 2 is provided on the upper surface of the other end of the upper layer of the N-drift region 6, and the gate oxide layer 2 extends along the upper surface of the N-drift region 6 to cover the N-well region 4 and the P-well region 5. The upper surface of the P-well region 5 between the N-drift region 6 and the upper surface of part of the N-well region 4 have a gate electrode 1 on the upper surface of the gate oxide layer 2; a cathode metal 3 is provided on the upper surface of the N-well region 4, one end of the cathode metal 3 is spaced from the gate oxide layer 2, and the other end of the cathode metal 3 extends toward the side away from the gate oxide layer 2 to cover the upper surface of the P-well region 5; the bottom of the P-well region 5 is composed of multiple arc sections connected end to end, and the P-well region 5 between each arc section and the bottom of the N-well region 4 has a different doping concentration, and the doping concentration of the P-well region 5 is gradually changed along the lateral direction.

[0008] A method for manufacturing a MOS gate-controlled thyristor with a laterally variable doped P-well region comprises the following steps:

[0009] a. N-type impurities are injected into the back side of the N-drift region 6 and the junction is pushed to form the FS layer 7;

[0010] b. Flip the N-drift region 6, form a gate oxide layer 2 on the front side and deposit polysilicon, and then etch to form a gate electrode 1;

[0011] c. Disposing multiple P-well region injection windows on the front surface of the N-drift region 6, and simultaneously injecting P-type impurities into the multiple injection windows and pushing junctions to form the P-well region 5; the injection windows must meet the following requirements: the width of a single injection window is greater than the maximum lateral diffusion length after the implanted ions are diffused, the spacing between the windows is less than twice the maximum lateral diffusion length after the implanted ions are diffused, the number of windows is less than or equal to the total width of the dopable windows divided by the preset window width, and rounded up, and the windows must be evenly arranged to ensure uniform current flow;

[0012] d. Injecting N-type impurities into the front of the N-drift region 6 and pushing the junction to form an N-well region 4;

[0013] e. Depositing an insulating dielectric layer on the front side of the N-drift region 6 and etching an ohmic contact hole;

[0014] f. Depositing metal on the front side of the N- drift region 6 to form a cathode metal 3;

[0015] g. Depositing a passivation layer on the surface of the N- drift region 6;

[0016] h. P-type impurities are injected into the back of the N- drift region 6 and ion activation is performed to form a P+ anode region 8;

[0017] i. Metal deposition is performed on the back of the N-drift region 6 to form an anode 9.

[0018] The P-well region variable doping structure described in the present invention includes a three-dimensional structure in addition to a two-dimensional structure. Figure 13 The figure shows the schematic diagram of extending the half cell to a three-dimensional structure, and the gray part at the top is the injection window in the three-dimensional structure. Figure 14 The special structure 2 shown is an improvement thereof, which further reduces the size of the injection window in a three-dimensional structure.

[0019] The beneficial effect of the present invention is that the introduction of the structure increases the lateral resistance of the device P-well region 5, increases the maximum potential difference between the P-well region 5 and the N-well region 4 when conducting, and accelerates the transition of the device from the IGBT conduction mode to the thyristor conduction mode. Figure 2 The structure shown avoids the problem of reducing the amount of ion implantation or the diffusion depth in the P-well region 5 in order to increase the lateral on-resistance, thereby maintaining the threshold voltage unchanged. Special structure 1 can regulate the gate threshold voltage without changing the process. Special structure 2 further accelerates the conduction of the device in three dimensions. The advantage of the present invention is that while maintaining the original process complexity, the device conduction performance is optimized simply by regulating the size of the doping window. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic diagram of the traditional cathode short-circuited planar gate MCT cell structure;

[0021] Figure 2 This is a schematic diagram of the cathode short-circuited planar grid type MCT cell structure of the present invention;

[0022] Figure 3 It is a schematic structural diagram of forming the FS layer 7 in the manufacturing process of the present invention;

[0023] Figure 4 It is a schematic diagram of the structure after forming gate oxide and depositing polysilicon and then etching in the manufacturing process of the present invention;

[0024] Figure 5 This is a schematic diagram of the structure of forming a P-well region 5 by ion implantation of P-type impurities in the manufacturing process of the present invention;

[0025] Figure 6 It is a schematic structural diagram of forming an N-well region 4 by ion implantation of N-type impurities in the manufacturing process of the present invention;

[0026] Figure 71 is a schematic diagram of the structure after cathode metallization in the manufacturing process of the present invention;

[0027] Figure 8 This is a schematic diagram of the structure after P-type impurities are injected into the back surface and ion activation is performed to form a P+ anode region 8 in the manufacturing process of the present invention;

[0028] Figure 9 It is a schematic diagram of the structure after forming the P-type collector region and the back metal in the manufacturing process of the present invention;

[0029] Figure 10 is a schematic diagram of ion implantation in the P-well region 5;

[0030] Figure 11 It is a schematic diagram of parameter annotation during ion implantation in the P-well region 5;

[0031] Figure 12 It is a special structure 1 schematic diagram of adjustable threshold voltage;

[0032] Figure 13 It is a three-dimensional expanded schematic diagram of the basic structure of the present invention;

[0033] Figure 14 Schematic diagram of a special structure 2 that optimizes conduction performance based on a three-dimensional structure;

[0034] Figure 15 This is a schematic diagram comparing the pressure resistance of the basic structure of the present invention and traditional MCT;

[0035] Figure 16 It is a schematic diagram comparing the conduction capabilities of the basic structure of the present invention and the traditional MCT. DETAILED DESCRIPTION

[0036] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments:

[0037] The present invention proposes a laterally doped cathode short-circuited MCT, the structural diagram of which is shown in FIG. Figure 2 , including polysilicon gate 1, gate oxide 2, cathode metal 3, N-well region 4, P-well region 5, N-drift region 6, FS layer 7, P+ region 9, and anode metal 10. Polysilicon gate 1 is in contact with gate oxide 2; the gate oxide is also in contact with N-well region 4, P-well region 5, and N-drift region 6; the other sides of N-well region 4 and P-well region 5 are in contact with cathode metal 3; P-well region 5 includes N-well region 4 and is adjacent to N-drift region below; below the N-drift region are FS layer 7, P+ region 8, and anode metal 9.

[0038] The present invention and Figure 1Compared to the conventional cathode short-circuit MCT shown in the figure, the bottom structure of the P-well region is different. The prior art uses a self-aligned method to simultaneously dope the entire P-well region. The present invention is an improved solution to the prior art method. Without changing the process flow, a mask is added during ion implantation in the P-well region. In the two-dimensional structure, the device uses a single injection window with a length of 4μm, a window spacing of 3μm, a total length of 65μm for the half-cell injection window, and nine separate injection windows. On this basis, multiple separate windows are simultaneously ion-implanted and pushed-junctioned to form a variable-doped lateral P-well region 5.

[0039] Compared to traditional cathode-shorted MCTs, this invention reduces the amount of P+ ions doped beneath the doping mask in the P-well region 5 by properly separating the doping windows in the P-region. This increases the lateral resistance of the P-well region 5 and, under pre-conduction conditions, increases the maximum potential difference between the P-well region 5 and the N-well region 4, effectively accelerating the device's transition from IGBT conduction mode to thyristor conduction mode. By properly controlling the distance between the doping windows in the P-well region 5, the doped P-well regions 5 are interconnected and prevent breakdown during normal operation due to the expansion of the depletion region at the interface between the P-well region 5 and the N-drift region.

[0040] like Figure 12 As shown, the special structure 1 controls the distance between the left side of the mask 10 and the right side of the gate to regulate the channel doping of the MOSFET structure formed by the planar gate, adjust the ion concentration of the P well region 5 below the gate, and thus adjust the threshold voltage without changing other process steps. Figure 13 As shown, the structure obtained by expanding the present invention in three dimensions.

[0041] like Figure 14 As shown, Special Structure 2 separates the continuous rectangular doping windows into square doping windows in a three-dimensional structure, thereby reducing the overall doping window size, further increasing the lateral on-resistance of the P-well region and accelerating the device conduction mode transition. However, the values ​​of x and d must be adjusted so that the maximum distance between the square implantation windows is less than twice the maximum lateral diffusion length dw after the implanted ions are diffused.

[0042] Conventional methods reduce the overall doping concentration of the P-well region 5 to increase lateral on-resistance. However, the method described in this invention improves device conduction performance without changing the original process flow by simply controlling the doping window of the P-well region.

[0043] Figure 15 The figure shows a comparison of the breakdown characteristic curves of the present invention and a conventional cathode short-circuited MCT device. The two curves essentially overlap. This result demonstrates that the structural changes in the present invention have a negligible impact on the device's withstand voltage performance.

[0044] Figure 16 The figure shows a comparison of the forward conduction characteristics of the basic structure of the present invention and a conventional cathode short-circuited MCT device. As can be seen from the figure, the snapback voltage of the basic structure of the present invention is lower than that of the conventional MCT. This result fully demonstrates that the present invention significantly improves the snapback effect during the device's forward conduction process.

Claims

1. A lateral variable doping P-well region MOS gate-controlled thyristor, comprising an anode metal (9), a P+ region (8), an FS layer (7) and an N-drift region (6) stacked in sequence from bottom to top, a P-well region (5) at one end of the upper layer of the N-drift region (6), an N-well region (4) at the upper layer of the P-well region (5), the lateral width of the N-well region (4) being smaller than the lateral width of the P-well region (5), and a spacing between the two ends of the upper surface of the N-well region (4) and the two ends of the upper surface of the P-well region (5); a gate electrode at the upper surface of the other end of the upper layer of the N-drift region (6) An oxide layer (2), and the gate oxide layer (2) extends along the upper surface of the N-drift region (6) to cover the upper surface of the P-well region (5) between the N-drift region (4) and the N-drift region (6), and a gate electrode (1) is provided on the upper surface of the gate oxide layer (2); a cathode metal (3) is provided on the upper surface of the N-well region (4), one end of the cathode metal (3) is spaced from the gate oxide layer (2), and the other end of the cathode metal (3) extends toward a side away from the gate oxide layer (2) to cover the upper surface of the P-well region (5); characterized in that The bottom of the P-well region (5) is composed of multiple arc segments connected end to end, and the P-well region (5) between each arc segment and the bottom of the N-well region (4) has a different doping concentration, and the doping concentration of the P-well region (5) is gradually changed along the lateral direction.

2. A method for manufacturing the lateral variable doping P-well MOS gate-controlled thyristor according to claim 1, characterized in that: The following steps are involved: a. Inject N-type impurities into the back of the N-drift region (6) and push the junction to form the FS layer (7); b. Flipping the N-drift region (6), forming a gate oxide layer (2) on the front side and depositing polysilicon, and then etching to form a gate electrode (1); c. multiple P-well region injection windows are provided on the front side of the N-drift region (6), and P-type impurities are simultaneously injected into the multiple injection windows and then pushed to form a P-well region (5); the injection windows must meet the following requirements: the width of a single injection window is greater than the maximum lateral diffusion length after the implanted ions are diffused, the spacing between the windows is less than twice the maximum lateral diffusion length after the implanted ions are diffused, the number of windows is less than or equal to the value of the total width of the doped windows divided by the preset window width and rounded up, and the arrangement is uniform to ensure uniform current flow; d. Injecting N-type impurities into the front of the N-drift region (6) and pushing the junction to form an N-well region (4); e. depositing an insulating dielectric layer on the front side of the N-drift region (6) and etching an ohmic contact hole; f. depositing metal on the front side of the N-drift region (6) to form a cathode metal (3); g. depositing a passivation layer on the surface of the N-drift region (6); h. Injecting P-type impurities into the back of the N-drift region (6) and performing ion activation to form a P+ anode region (8); i. Metal deposition is performed on the back side of the N-drift region (6) to form an anode (9).

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