Preparation method of silicon-based photonic crystal defect waveguide and phototransistor integrated chip

Abstract

The invention provides a preparation method of a silicon-based photonic crystal defected waveguide and phototransistor integrated chip. Sequentially epitaxially growing an N-type Si layer, a P-type Si < x > Ge < 1-x > layer, a P-type Si layer and an N-type polycrystalline Si layer on the SOI substrate; in the transistor part, an N-type polycrystal Si emitter region, a double-base region and an N-type Si collector region are made into strip shapes; respectively manufacturing electrode contact holes on the N-type polycrystal Si layer and the SOI substrate top Si layer, and preparing metal electrodes on the N-type polycrystal Si layer and the SOI substrate top Si layer; and a nano air hole array and a defect waveguide channel are manufactured at the defect waveguide part of the photonic crystal. The photoelectric integration is easy, and the cost is low; the photonic crystal defect waveguide can be conveniently coupled with an optical fiber, and a photonic forbidden band and a light trapping effect are generated through the periodic nanopore array and line defect characteristics so as to control the transmission path of incident light. Incident light is limited in the photonic crystal defect waveguide, and the incident light of 850-940 nm is transmitted in a photonic crystal defect waveguide channel, so that the coupling accuracy and the light absorption efficiency are improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a method for preparing a silicon-based photonic crystal defect waveguide and phototransistor integrated chip. Background Art

[0002] At present, common silicon-based detectors can be divided into PIN type, APD and other diode type devices and phototransistor type devices based on the detector structure. Among them, the phototransistor (HPT) type detector has the advantages of high internal gain and low operating voltage. According to the different directions of the incident light entering the absorption layer of the device, it can be divided into vertical incidence type and side coupling type, that is, the incident light enters the device from the top light window and the side light window respectively. For light detectors, especially Si / SiGeHPT devices with side-incident structure, precise alignment between the optical fiber and the chip is crucial. Only by achieving high-precision coupling can the light absorption efficiency of the device be effectively enhanced, thereby improving the light response. On the contrary, if there is a deviation in the alignment, even a small offset may lead to large insertion loss, reduce the transmission efficiency of the optical signal, and thus reduce the light absorption efficiency of the device. Therefore, how to realize a side-incident Si / SiGe HPT structure that helps to align the optical fiber and the chip with high precision has become a key technical problem that urgently needs to be broken through. Summary of the Invention

[0003] In response to the shortcomings of the existing technology, the purpose of the present invention is to provide a method for preparing a silicon-based photonic crystal defect waveguide and phototransistor integrated chip, aiming to solve the problem of difficult precise alignment between optical fiber and side-incident Si / SiGeHPT and chip, thereby improving the absorption efficiency of the light detector.

[0004] To achieve the above object, the present invention provides a method for preparing a silicon-based photonic crystal defect waveguide and phototransistor integrated chip, comprising the following steps:

[0005] (1) Select SOI substrate, which includes bottom Si layer, silicon dioxide BOX layer and top Si layer. N - Type Si layer, P-type Si x Ge 1-x layer, a P-type Si layer, and an N-type polycrystalline Si layer.

[0006] (2) The phototransistor structure includes an N-type polycrystalline Si emitter region, a double base region (P-type Si base region, P-type Si x Ge 1-x Base), N - The N-type polysilicon collector region and SOI substrate are connected, and the device height is H1. -The collector region is made into a stripe to form the ridge portion, with a height of h1 and a width of w. The SOI substrate forms the mesa portion, with a height of H1-h1 and a width of W.

[0007] (3) In the transistor part, electrode contact holes for the emitter region and collector region are made on the N-type polycrystalline Si layer and the top Si layer of the SOI substrate respectively.

[0008] (4) In the transistor part, metal electrodes are made to form ohmic contacts.

[0009] (5) In the defect waveguide part, nano air hole arrays and defect waveguide channels are made.

[0010] Furthermore, the resistivity of the top Si layer in step (1) is less than 0.05Ω·cm, and the P-type Si x Ge 1-x The material composition of the layer is Si 0.84 Ge 0.16 .

[0011] Furthermore, the manufacturing method in step (2) adopts dry etching (ICP).

[0012] Furthermore, in step (3), a SiO2 film with a thickness of 145 nm is deposited on the surface of the device as an insulating layer by PECVD, and then contact holes are etched by wet etching.

[0013] Furthermore, in step (4), Ti / Pt / Au is deposited by electron beam evaporation, and the wafer with the metal vapor deposition is placed in an acetone solution and ultrasonically stripped with adhesive to prepare a contact electrode, and the metal electrode forms an ohmic contact with the device.

[0014] Furthermore, the nano-air hole array in step (5) has a length of 8P, a width consistent with the mesa width of the phototransistor, a period P ranging from 386nm to 406nm, a nano-hole radius R ranging from 177nm to 187nm, and a nano-hole depth h2 consistent with the ridge height h1 of the transistor. The photonic crystal defect waveguide channel is aligned with the center of the ridge portion of the phototransistor, and the defect waveguide channel width D is 3P-2R, and D ≥ w.

[0015] Furthermore, in step (5), the height H2 of the photonic crystal defect waveguide is the same as the height H1 of the phototransistor.

[0016] Furthermore, in step (5), electron beam lithography (EBL) is used to fabricate periodically arranged nanometer air hole arrays and photonic crystal defect waveguide channels.

[0017] Compared with the prior art, the beneficial technical effects of the present invention are:

[0018] This invention provides a method for fabricating a silicon-based photonic crystal defect waveguide and phototransistor integrated chip. The method has the following advantages: the SiGe / SiHBT fabrication process is compatible with BiCMOS technology, facilitating optoelectronic integration and meeting low-cost requirements. The photonic crystal defect waveguide facilitates optical fiber coupling, and through the periodic nanohole array and linear defect properties, it generates a photonic bandgap and light trapping effect to control the transmission path of incident light. Incident light is confined within the photonic crystal defect waveguide, allowing 850-940 nm incident light to propagate within the photonic crystal defect waveguide channel, enabling precise transmission of the incident light to the side optical window of the phototransistor. This improves the device's coupling accuracy and light absorption efficiency by approximately 70%-80%.

[0019] In summary, the present invention provides a silicon-based photonic crystal defect waveguide and phototransistor integrated chip, which has the advantage of being easy to align and couple with optical fibers, and has a simple process flow, low cost, easy implementation, and can be promoted on a large scale. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The present invention sequentially epitaxially grows N on the SOI substrate. - Type Si layer, P-type Si x Ge 1-x Schematic diagram of the epitaxial structure after the layer, P-type Si layer and N-type polycrystalline Si layer;

[0021] Figure 2 A top view of the silicon-based photonic crystal defect waveguide and phototransistor integrated chip of the present invention;

[0022] Figure 3 A side view of the silicon-based photonic crystal defect waveguide and phototransistor integrated chip of the present invention;

[0023] Figure 4 A three-dimensional structural diagram of the silicon-based photonic crystal defect waveguide and phototransistor integrated chip of the present invention;

[0024] Description of the accompanying drawings: 1—SOI substrate; 101—Si substrate; 102—SiO2 layer; 103—top Si layer; 2—N - Type Si layer; 3—P type Si x Ge 1-xLayer; 4—P-type Si layer; 5—N-type polycrystalline Si layer; 6—nano-air hole array; 7—photonic crystal defect waveguide channel input; 8—nano-air hole; 9—photonic crystal defect waveguide channel output; 10—emitter; 11—collector; P—nano-air hole period; R—nano-air hole radius; D—photonic crystal defect waveguide channel width; w—phototransistor ridge width; W—phototransistor mesa width; h1—phototransistor ridge height; H1—phototransistor height; h2—nano-air hole depth; H2—photonic crystal defect waveguide height. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0026] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0027] The present invention provides a method for preparing a silicon-based photonic crystal defect waveguide and phototransistor integrated chip, comprising the following steps:

[0028] (1) N is epitaxially grown on SOI substrate 1 (101-Si substrate; 102-SiO2 layer; 103-top Si layer) in sequence. - Type Si layer 2, P-type Si x Ge 1-x layer 3, P-type Si layer 4 and N-type polycrystalline Si layer 5.

[0029] (2) In the transistor part, the N-type polycrystalline Si layer 5, the P-type Si layer 4, and the P-type Si 0.84 Ge 0.16 Layer 3 and N - The Si layer 2 is formed into a stripe shape to form a ridge portion with a height of h1 and a width of w. The SOI substrate forms a mesa portion with a height of H1-h1 and a width of W.

[0030] (3) In the transistor part, electrode contact holes for the emitter region and the collector region are made on the N-type polycrystalline Si layer 5 and the top Si layer 103 respectively.

[0031] (4) In the transistor part, make metal electrodes (10-emitter; 11-collector).

[0032] (5) In the photonic crystal defect waveguide part, a nano air hole array 6 and a defect waveguide channel (7 - photonic crystal defect waveguide channel input end; 9 - photonic crystal defect waveguide channel output end) are made.

[0033] Example

[0034] The present invention provides a method for preparing a silicon-based photonic crystal defect waveguide and phototransistor integrated chip, comprising the following steps:

[0035] (1) A 6-inch diameter (100) face Si wafer with a thickness of about 550 μm was selected. Oxygen ion implantation was performed in the Si wafer to form a high-concentration oxygen implantation layer. Then, high-temperature annealing was performed to allow the implanted oxygen to react with silicon to form a SiO2 insulating layer. Finally, the SOI substrate 1 was obtained after grinding and polishing. Low-pressure chemical vapor deposition (LPCVD) was used to grow N with a thickness of 480 nm on the SOI silicon wafer. - Type Si layer 2, whose doping concentration is 1×10 17 cm -3 , SiH4 as Si source, growth temperature is 700℃; As as N-type doping impurity source. 0.84 Ge 0.16 Layer 3 is made by reduced pressure chemical vapor deposition (RPCVD) on N - The thickness of the Si layer is 40 nm and the doping concentration is 1×10 19 cm -3 The reaction sources are SiH4 and GeH4, the growth temperature is 600℃, and B is used as the P-type dopant source. Low pressure chemical vapor deposition (LPCVD) is used to deposit P-type Si 0.84 Ge 0.16 A 40 nm thick P-type Si layer 4 is grown on the surface of layer 3, with a doping concentration of 1×10 18 cm -3 , the reaction source is SiH4, and the P-type doping impurity source is B. Finally, low pressure chemical vapor deposition (LPCVD) is used to grow an N-type polycrystalline Si layer 5 on the P-type Si layer 4 with a thickness of 150nm and a doping concentration of 1×10 20 cm -3 SiH4 is used as the Si source at a growth temperature of 700°C; As is used as the N-type doping impurity source.

[0036] (2) Based on the above, photolithography is performed on the transistor part and dry etching (ICP) is used to etch the N-type polycrystalline Si layer 5 to a depth of 150nm. Dry etching conditions: ICP power 900W, RF power 15W, etching gas SF6, flow rate 75cm 3 / min, etching passivation gas C4F8, flow rate 40cm 3 / min, etching time 40 seconds. Then dry etching the base region, the etching depth is 80nm. ICP conditions: source power 900W, RF power 15W, etching gas SF6, flow rate 75cm 3 / min, etching passivation gas C4F8, flow rate 40cm 3 / min, etching time 30 seconds.

[0037] (3) Based on the above, photolithography and dry etching (ICP) were performed to etch the collector mesa to a depth of 480 nm. Etching conditions: source power 900 W, RF power 15 W, etching gas SF6, flow rate 75 cm 3 / min, etching passivation gas C4F8, flow rate 40cm 3 / min, etching time 150 seconds.

[0038] (4) A 145 nm thick SiO2 film was deposited on the surface of the structure in step (3) by PECVD as an insulating layer. Contact holes were then formed on the SiO2 film by photolithography and wet etching. The etching solution was a BOE solution composed of a mixture of 49% (mass percent concentration) HF aqueous solution and 40% (mass percent concentration) NH4F aqueous solution in a volume ratio of 1:6. The etching time was 35 s.

[0039] (5) Based on step (4), photolithography was performed and Ti / Pt / Au was deposited by electron beam evaporation to prepare contact electrodes to form ohmic contacts with the device. The thickness of each metal layer was: Ti (50 nm) / Pt (50 nm) / Au (100 nm). The deposition conditions were: voltage 5 kV, electron beam current 5 mA, temperature 180°C. Finally, thermal annealing was performed at 450°C for 30 seconds.

[0040] (6) Based on step (5), electron beam exposure (EBL) is used to produce a periodically arranged nano-air hole array 6 and a photonic crystal defect waveguide channel. The period P of the nano-air hole array 6 is 400nm, the radius of the nano-air hole is 184nm, the depth is 670nm, and the width D of the photonic crystal defect waveguide channel is 832nm. It needs to be carried out under the following conditions: the electron beam photoresist type is selected: AR-P672.08, the coating speed is 2000r, the pre-baking condition is 145℃, and the baking is carried out on a hot plate for 3min. The electron beam acceleration voltage is 15kV, the aperture is 20μm, and the electron beam dose required for exposure is 100μC / cm 2 The film was immersed in AR-600-56 solution at room temperature for 150 seconds, fixed with isopropyl alcohol for 30 seconds, and then post-baked on a hot plate at 130°C for 1 minute. The result was a silicon-based photonic crystal defect waveguide and phototransistor integrated chip.

[0041] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A method for preparing a silicon-based photonic crystal defect waveguide and phototransistor integrated chip, characterized in that: The following steps are involved: (1) Select SOI-based substrate, which includes a bottom Si layer, a silicon dioxide BOX layer, and a top Si layer; epitaxially grow N on the SOI-based substrate in sequence. - Type Si layer, P-type Si x Ge 1-x layer, a P-type Si layer and an N-type polycrystalline Si layer; (2) The phototransistor structure includes an N-type polycrystalline Si emitter region, a double base region, and an N - Type Si collector region and SOI substrate, the device height is H1; N-type polycrystalline Si emitter region, double base region and N - The collector region is made into a strip to form a ridge part with a height of h1 and a width of w; the SOI substrate forms a mesa part with a height of H1-h1 and a width of W; the double base region includes a P-type Si base region and a P-type Si x Ge 1-x base region; (3) In the transistor part, electrode contact holes for the emitter region and the collector region are made on the N-type polycrystalline Si layer and the top Si layer of the SOI substrate respectively; (4) In the transistor part, metal electrodes are made to form ohmic contacts; (5) In the photonic crystal defect waveguide part, a nano air hole array and a defect waveguide channel are made.

2. The preparation method according to claim 1, characterized in that The resistivity of the top Si layer in step (1) is less than 0.05Ω·cm, and the P-type Si x Ge 1-x The material composition of the layer is Si 0.84 Ge 0.16 .

3. The preparation method according to claim 1, characterized in that The manufacturing method in step (2) is dry etching, etching the N-type polycrystalline Si layer, the P-type Si layer, the P-type Si layer, x Ge 1-x Layer and N - Type Si layer, etching conditions: source power 900W, RF power 15W, etching gas SF6, flow rate 40-75cm 3 / min, etching passivation gas C4F8, flow rate 40cm 3 / min.

4. The preparation method according to claim 1, characterized in that In step (3), a 145 nm thick SiO2 film is first deposited on the device surface as an insulating layer by PECVD, and then contact holes are etched by wet etching. The etching solution is BOE solution, which is a mixture of 49% HF aqueous solution and 40% NH4F aqueous solution in a volume ratio of 1:

6. The etching time is 35s.

5. The preparation method according to claim 1, characterized in that In step (4), Ti / Pt / Au is first deposited by electron beam evaporation, and then the metal-deposited wafer is placed in an acetone solution and ultrasonically stripped to prepare a contact electrode, and the metal electrode forms an ohmic contact with the device; the deposition conditions are: voltage 5kV, electron beam current 5mA, temperature 180°C; finally, thermal annealing is performed at 450°C for 30s.

6. The preparation method according to claim 1, wherein: The length of the nano-air hole array in step (5) is 8P, the width is consistent with the width of the phototransistor table, and the period P ranges from 386nm to 406nm; the nano-hole radius R ranges from 177nm to 187nm, and the nano-hole depth h2 is the same as the ridge height h1 of the transistor; the photonic crystal defect waveguide channel is aligned with the center of the ridge portion of the phototransistor, the defect waveguide channel width D is 3P-2R, and D≥w.

7. The preparation method according to claim 1, wherein: In step (5), the height H2 of the photonic crystal defect waveguide is the same as the height H1 of the phototransistor.

8. The preparation method according to claim 1, wherein: In step (5), electron beam exposure (EBL) is used to produce the nano-air hole array and defect waveguide channel. The process needs to be carried out under the following conditions: the electron beam photoresist type is AR-P672.08, the coating speed is 2000r, the pre-baking condition is 145℃, and the baking is carried out on a hot plate for 3min; the electron beam acceleration voltage is 15kV, the aperture is 20μm, and the electron beam dose required for exposure is 100μC / cm 2 ; Select AR-600-56 solution to soak at room temperature for 150s, use isopropyl alcohol to fix for 30s, and then bake on a hot plate at 130℃ for 1min.

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